Instead of disabling all GPEs during PMC init in bootblock, this
change moves it to pmc_fill_power_state which allows romstage to
correctly fill up GPE_EN registers in chipset_power_state. This is
essential for correctly identifying the wake source.
Disabling all GPEs was added recently in change 74145f76
(intel/common/pmc: Disable all GPEs during pmc_init) because keeping
GPEs enabled in coreboot while enabling SMI could lead to
side-effects as explained in the change. Moving pmc_disable_all_gpe to
pmc_fill_power_state should be safe as that happens before SMI is
enabled in coreboot.
TEST=Verified that GPE-based wake source is correctly
identified. Also, no issues observed while resuming from S3.
Change-Id: I8e992ad09ffdefba62de11fa572e783715776bf1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22033
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
bc is one of the standard posix utilities. I'm surprised that it's
not in the debian docker image by default.
Change-Id: I02f2d5296e7f87876b236af119965d1f4e6a0bc0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is already selected in `src/cpu/amd/agesa/Kconfig`.
Change-Id: I691a2ade10ee461b6bc34ea24d57a911281791f3
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
DRAM Controller is always 00.0. No need to check its PCI ID.
Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It's more consistent to re-initialize EBDA in all boot paths.
That way, the data living in EBDA is cleared prior to be
accessed (assuming it's after setup_ebda()).
Change-Id: I05ff84f869f7b6a463e52b4cb954acc5566475cd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
It's possible for chipsets utilizing ebda to cache the cbmem_top()
value to be called prior to the object being entirely setup. As
such it's important to check the signature to ensure the object
has been initialized. Do that in a newly introduced function,
retrieve_ebda_object(), which will zero out the object if the
signature doesn't match.
Change-Id: I66b07c36f46ed9112bc39b44914c860ba68677ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add hexdump.c to Makefile.inc and change an elog_debug format to
use %z for size_t arguments. This corrects build errors when ELOG_DEBUG
is used.
Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Reviewed-on: https://review.coreboot.org/21769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the support for Cannonlake U DDR4 board to Cannonlake U LPDDR4
platform.
TEST=Able to boot up on CNL U LPDDR RVP.
Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Also change the tarball from .tar.bz2 to .tar.xz.
Change-Id: I25134dbadf07a2f0cb356c8ac8f2c612a957d176
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
> Could you make in a separate, independent change a update from the
> completely outdated LIBELF (from mr511.de/software/libelf ) to recent
> libelf? Those highly outdated libelf from this unmaintained mr511.de
> webpage should not be used any more since years. There are also a ton
> of security issues like for example: CVE-2017-7607, CVE-2017-7608, ...
> CVE-2017-7613. Recent version of this software is included in the
> elfutils that are available here: https://sourceware.org/elfutils/ ->
> download link:
> https://sourceware.org/elfutils/ftp/0.170/elfutils-0.170.tar.bz2
Remove the obsolete patch, which doesn’t apply anymore, and only
affected the build system, which is different now.
Increment the buildgcc version string as a tool version is changed.
TEST=Running `make crossgcc-i386` succeeds.
Change-Id: Iadd320a18c5d9fe2a82a347e39f01d8b7f8806c2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/21435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The code used to split up ranges >64MiB into 64MiB-aligned and
unaligned parts. However in its current state the next step,
calc_var_mtrr_range(), results in the same allocation, no mat-
ter if we split the range up before. So just drop the split-up.
Change-Id: I5481fbf3168cdf789879064077b63bbfcaf122c9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables.
Use Kconfig for reversable configuration if using old OS.
BUG=b:62241143
Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
If FSP 2.0 is used, then postcar stage is used and the flashconsole
as well as spi drivers needed to be added.
Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch address problem with Tianocore compilation in coreboot-sdk
container. Without it compilation fails asking for nasm installation.
Change-Id: I546f9d42b380799d1cd80a70f33be2a768745080
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable CQOS on Geminilake.
In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF.
Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK.
Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right
bits.
BUG=None
TEST= Build for Geminilake platform i.e., glkrvp & check for successful
CAR setup. Even verified the same on APL platform i.e., on Reef
Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com
Reviewed-on: https://review.coreboot.org/21701
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use GENERIC_SPD_BIN method of adding the SPD bins to final rom.
Change-Id: I242e393bafac41aa7743f83b52cadf027019ee6e
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The Stoney Ridge APU has only two internal UARTs. Add checks for
invalid settings. When enabling the UART, return if the console is
on any UART not equal 0 or 1. The base address returned is 0 if an
invalid configuration is used. All callers check the return value
before using the returned value. Finally, provide an assert at the
earliest availability of the console to get the notice into the
cbmem console.
BUG=b:62201567
TEST=Build with UART = -1, 0, 2. Inspect objdump and boot to OS.
Build without ST UART and inspect with objdump.
Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Before adding a new UART to the coreboot/lb table, verify that it
has a non-zero base address. This is consistent with all other
functions that use the uart_platform_base() function.
This was tested on google/kahlee by using an invalid UART number
and forcing the base address to 0. Execution was able to complete
through depthcharge and into the OS.
Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21996
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Don't force the selection of placing the firmware outside of cbfs
when using vboot.
- Set a prompt to allow the option of placing it outside of cbfs.
- Leave all Kconfig defaults the same.
- Place the AMD firmware directory table in the specified location
even when using the 'outside of cbfs" option.
- Print where the firmware is being placed when placing it outside
of cbfs.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test. Firmware shows up
inside CBFS. Set 'outside of cbfs' option, verify firmware gets
written to the correct location.
Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For Kahlee, the AMD firmware directory should be in the 1MB location
so that it's in the RO cbfs section.
BUG=b:65484600
TEST=Build & boot
Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22003
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Find the PmControl register's I/O address by checking the hardware in
PMx62. Don't rely on the address being the coreboot default. PmControl
is the first register in the AcpiPm1CntBlk.
Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Let the developer or user know that a callout isn't supported.
Change-Id: I73a6c6930a6661627ad76e27bbb78be99e237949
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/wizpig (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new wizpig variant
- Add new shared SPD file to the baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/ultima (Lenovo Yoga 11e G3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new ultima variant
Sourced from Chromium branch firmware-ultima-7287.131.B,
commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode""
Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add support for google/setzer (HP Chromebook 11 G5) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new setzer variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Factor out the code into separate functions.
Create set_lpc_resource that will set the resource for a particular child while
lpc_enable_childrens_resources finds all children and calls set_lpc_resource
for each child found. This creates well defined boundaries for each function.
Change-Id: I265cfac2049733481faf8a6e5b02e34aadae11f5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This updates board info of PC Engines platforms, changes board names
to official manufacturer's names and adds info about ROM. Removing
"Clone of" option for ALIX platforms makes them independent.
Change-Id: Ie76d65ea84f14b9043a8e5b86678a9da4c187cc9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Martin Roth <martinroth@google.com>
SPI mode needs to be set early to normal and Quad I/O disabled
on this board for some reason
Change-Id: I4dbc52010eebf492087d0b1c155a24a307bcc8b0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
TESTED on Biostar A68N-5200: boots to GNU/Linux
With proprietary VBIOS, even the gfx works in SeaBIOS.
Change-Id: Id44b81345ba189f82413042760d570a746294a1e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Enable the use of the SataPortsEnable and SataPortsDevSlp registers
which were being ignored from the devicetree and were not affecting
the resulting UPD parameters.
SataPortsEnable was only being copied for the first SATA port, while
the other ports were left ignored.
Change-Id: Iae70a4d6375fa5d1b05ee89f6b97c65dbbf28dda
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Support the required AGESA_DO_RESET in bootblock.
BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.
Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The AGESA RESET_WHENEVER request were never doing a reset in coreboot.
We don't have a way to collect a whenever and reset at some later time,
so just do the reset immediately.
BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.
Change-Id: If2654ec0c5c5dbdcea6fc9374371c3388d29fdc7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21978
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are changing the bootstraps in the EVTs so that the SOC
communicates with cr50 over SPI instead of cr50. SPI is more reliable
than I2C. Thus, disabling cr50 over I2C and enabling cr50 over SPI.
BUG=b:65056998, b:62456589
BRANCH=None
TEST=make sure that we can boot into kernel
run cold_reset and warm_reset and make sure both
boot successfully.
CQ-DEPEND=CL:714237
Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch moves out LTR programming under L1 substate
to pchexp_tune_device function, as substate programming
and LTR programming are independent.
LTR programming scheme is updated to scan through entire
tree and enable LTR mechanism on pci device if LTR mechanism
is supported by device.
BRANCH=none
BUG=b:66722364
TEST=Verify LTR is configured for end point devices and max
snoop latency gets configured.
Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/21868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for google/relm (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new relm variant
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ife10f5f75435f356cd896588dd6f425e54f3c88e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add support for google/kefka (Dell Chromebook 11 3180) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new kefka variant
- Add new shared SPD file to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram
Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
buildgcc -B (--bootstrap-only) builds only a bootstrap compiler. That
useful if you want to package the cross compilers: first build the
bootstrap compiler, then all required cross compilers in a separate
directory (using the bootstrap compiler through an adjusted PATH).
Change-Id: I089b51d1b898d4cf530845ba51283997fd229451
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Martin Roth