Name the common part of GNVS initialisation as soc_fill_gnvs().
It is also moved before the call to acpi_create_gnvs(), which
followup will rename to mainbord_fill_gnvs() to reflect that
implementation is under mb/.
Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48706
Reviewed-by: Lance Zhao
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards without ChromeEC do not set ACTIVE_EC_RW
flag as part of the gnvs_assign_chromeos() function.
Create abstraction to avoid <vendorcode/chromeos/x> include.
Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.
Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of hard-coding function names in strings, use the __func__
constant for better maintainability.
Change-Id: I151560cd5a135e00f494eda3f9d3b592ee9d984a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a space after each comma to fix linter issues.
Change-Id: I5533c4fc7aa0e986da4350ec56b84903b3111a07
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Macros should not use a trailing semicolon.
Change-Id: Ibbcd589c7afa72e9e468e5f4b557bb2c665bbec0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Align the bytes of picr_data[] and intr_data[] with 8 bytes per line and
add spaces after commas so that the linter doesn't complain.
Also, remove spaces before the postfix '++' operator.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I90bec7fdfabca6f8afd1508c673241e0742e2ee9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49191
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop VR configuration since it matches the platform defaults.
Change-Id: I92007f4ff9d093c9573bb1ee13e64eb2f38af4f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin
board. This update configures these USB2 ports for Type C which will
allow USB2 port reset message upstream from PCH to CPU to recover a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Booted to kernel on Delbin board and verified usb2 port reset
message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE
where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4.
Validated various USB3 devices enumeration.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without this target some spurious errors occurred when running make
distclean at the top level of coreboot.
Change-Id: I3d3061b386fc5b4a043cfc7ff8fd3c0da33c0e83
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49227
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:174118027
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Signed-off-by: Marco Chen <marcochen@google.com>
Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
This change adds internal USB camera into devicetree for sasuke
BUG=None
TEST=Built and checked camera device existence with lsusb
Change-Id: I51b9bb174205d984f1d060afd603f1d087095645
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49162
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds ELAN touchpad into devicetree for sasuke.
BUG=None
TEST=Built and verified touchpad function
Change-Id: If9c25f23ee1c0e88382fff036f77a6753775b81e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change adds DA7219 audio codec and MAX98360A amplifier for sasuke.
BUG=None
TEST= Built and heared speaker sound on OS
Change-Id: Ib48eb74fbfe171d46d0d23859057ba169b56bde2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Drop DEVICETREE from Kconfig since it matches the default value.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It doesn't make sense to configure that filename in Kconfig, since the
filename can be changed by the user. So remove it.
Change-Id: I3eed05637da29096bc1d134505d7335db5db1439
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49138
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
An API is added to get SSFC value from cros EC.
BUG=b:174118027
BRANCH=octopus
TEST=check SSFC value from EC is correct compared to value in CBI
Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
uart_common_init is not used outside of
soc/intel/common/block/uart.c. This change restricts the scope to this
file and drops the declaration from uart.h
Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49211
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the parameter passed into `lpss_set_power_state()`
from struct device * to pci_devfn_t. This allows the users in the
early stages to use pci_devfn_t instead of having to walk the device
tree to get a pointer to the relevant device structure. It is
important for optimizing out unnecessary components of the device tree
from the early stages.
Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49210
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops the parameter `struct device *dev` from the function
`soc_get_gen_io_dec_range()`. This function uses the parameter dev to
get a pointer to config structure for extracting the decode ranges
configured by mainboard in device tree. However, there is no separate
chip driver for the LPC device which means that the SoC code can use
`config_of_soc()` to get to SoC chip config instead of using the LPC
device.
This change is being done in preparation to clean up the device
tree/chip config access in early stages that allows for optimizing
the inclusion of device tree elements in the early stages.
Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change uses append operation (+=) instead of assignment (:=) for
smm-c-deps to ensure that any earlier assignment is not
overwritten.
Change-Id: Ic1d62b414cfe3f61ee2b80b026b7338faa186904
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is
implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI
USB2 port reset event issued by the xHCI driver shall trigger a message
upstream to CPU to wake it from the low power state which allows a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Built and booted to kernel on Voxel board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 8c99c27df1 removed util/genprof,
so it needs to be dropped here as well to avoid spurious breakages of
the build.
Change-Id: I420b5c43e2d97373a8e665f457463a06e16ecfb9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49226
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Different from mt8183, mt8192 doesn't need to trigger EC reboot on HW
initiated watchdog reset. Therefore, ec_reset_flags cannot be used to
determine AP watchdog reset. Instead we check the cause of the last AP
reset.
BUG=b:174443398
TEST=emerge-asurada coreboot
TEST=crash.WatchdogCrash passed on asurada
BRANCH=none
Cq-Depend: chromium:2607150
Change-Id: I761ecdd8811e5612b39e96c73442cc796361d0f0
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49113
Reviewed-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change copies ec_commands.h directly from the Chromium OS EC repo
at SHA afffc28f2, with the exception of changing the copyright header
to SPDX format.
Change-Id: Ie02e0295312050e803a7d701ec4eed1dadfa6c9a
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The _CST method is supposed to return a package. If a mainboard used
zero for all ACPI C-states, the generated _CST would return nothing,
which is invalid. Instead, return a package with no C-state entries.
This change is a no-op, since all mainboards have at least one valid
ACPI C-state. This is what `acpigen_write_CST_package()` does, too.
Change-Id: I1f531e168683ed108a8d6d03dee6f5415fd15587
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49092
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just a small change to follow the code style.
Change-Id: Ie838b82e12627478ea721f426efc4d557feb6ae3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49166
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt
DRAM Part Name ID to assign
MT53D512M64D4NW-046 WT:F 0 (0000)
H9HCNNNCRMBLPR-NEE 0 (0000)
MT53D1G64D4NW-046 WT:A 1 (0001)
H9HCNNNFBMBLPR-NEE 2 (0010)
BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the _PRT generates a GNB IO-APIC routing table we no longer
need to route the PCI interrupts through the FCH IO-APIC. This change
unmaps the IRQs since they are no longer used.
BUG=b:170595019
TEST=Boot with `pci=nomsi amd_iommu=off` and verify /proc/interrupts
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3467934bfcac14311505bec49a12652490554e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
At the moment neither verstage nor romstage has a generated assembly
stub. This was used when CAR was set up in romstage which is not the
case anymore.
Change-Id: Ia4a952f269cc2b3edf1290c80b7a63619c8c6c95
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Kyösti Mälkki