Commit Graph

3545 Commits

Author SHA1 Message Date
Pavel Sayekat cc48009631 util/superiotool/nuvoton.c: add NCT5539D register dump
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015).
Tested on ASUS-H110M-E/M.2 mainboard (Kabylake i3-7100 CPU).

Change-Id: Ib55068035ca574b22d0fea81e1a291f7cf0329d3
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-14 12:17:26 +00:00
Patrick Georgi 7945f75417 lint/clang-format: set to 96 chars per line
coreboot has decided to go with 96 characters per line.

Original Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651

Change-Id: I9c99e5cca6548e23cf755dc37193ff2aa669ac10
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-06-13 20:14:00 +00:00
Marshall Dawson 24f73d4f53 util/amdfwtool: Add multilevel PSP directory table
Add the ability to generate two PSP directory table levels.  The PSP
is capable of supporting two levels, with the primary intended to
remain pristine for the life of the system, and the second updatable.
In the event the second becomes corrupted, the primary is still
sufficient to allow a recovery of the other.

This patch modifies no directory table structures currently in use.
The soc or southbridge must pass an argument to force building the
secondary table.

BUG=b:126593573
TEST=Used with WIP Picasso

Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13 18:01:07 +00:00
Marshall Dawson 7c1e1428ad util/amdfwtool: Align PSP NVRAM
Align the PSP's NVRAM item since it's intended to be updateable
in the flash device.

Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13 18:00:27 +00:00
Marshall Dawson ef79fccf4e util/amdfwtool: Add argument for soft fuse override
Allow the soc build to pass a soft fuse value to the utility.  This
helps maintain compatibility across PSP generations.

Add a generic 'other' item to the amd_fw_entry structure that may
be used by non-fuse entries in the future.

TEST=Verify google/grunt amdfw.rom unchanged before and after.
     Compare internal board using override before and after.

Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-13 18:00:05 +00:00
Felix Held e5b05d61df util/superiotool: clarify usage of MISC and NANA defines
Change-Id: I0b3c5c810bfb05eaec13511391ecd55d7b9eb4e8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13 14:07:57 +00:00
Iru Cai cd980abe18 autoport: Generate a libgfxinit template when IGD is detected
Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-09 17:10:44 +00:00
Duncan Laurie 7775d67218 ifdtool: Enable GbE/PDR/EC region access only if they exist
Instead of assuming GbE/PDR/EC regions may exist or not, check if there
is a valid region defined in the descriptor and set the region access
permissions based on that.

The net effect change is to enable the use of the PDR region on the
sarien platform, which also uses the GbE and EC regions.

This results in the following example changes:

mb/google/sarien (GbE, PDR, EC)
.      DESC BIOS ME GbE PDR EC
-BIOS  r    rw      rw      r
-------------------------------
+BIOS  r    rw      rw  rw  r

mb/google/eve: (no GbE, no PDR, no EC)
.      DESC BIOS ME GbE PDR EC
-BIOS  r    rw      rw      r
-ME    r         rw r
-GbE   r            rw
-EC    r                    rw
-------------------------------
+BIOS  r    rw
+ME    r         rw
+GbE
+EC

BUG=b:134703987

Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33273
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-07 20:51:27 +00:00
Nico Huber ec017590e5 util/lint: Make usage of IS_ENABLED() an error
As long as we keep the IS_ENABLED() definition in libpayload for
compatibility, we should check that IS_ENABLED() usage doesn't
sneak back in.

Also remove all other IS_ENABLED() checks.

Change-Id: Id30ffa0089cec6c24fc3dbbb10a1be35f63b3d89
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-04 13:16:16 +00:00
Nitheesh Sekar 6681f05373 qcs405: util/qualcomm: Add T32 debug scripts
Add T32 scripts that allow debug of any coreboot stage
on qcs405.

Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29951
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:20:38 +00:00
Damien Zammit 9b5e8c1718 xcompile: Remove --rtlib switch from clang CFLAGS
Fix the following error from clang invoking gcc linker with wrong arg:

i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc';
did you mean '-static-libgcc'?
clang-4.0: error: linker (via gcc) command failed with exit code 1

Just remove --rtlib switch from CFLAGS relating to clang

Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-29 20:33:35 +00:00
Evgeny Zinoviev 3d90d3bfce util/autoport: Add info about rank 1 mirroring
inteltool can't detect whether address mapping is normal or
mirrored, which in turn may be cause RAM initialization to
fail when using spd.bin generated by inteltool.

Mention this in readme as it may help someone.

Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-29 20:07:10 +00:00
Alan Green 1470c7367b util/xcompile/xcompile: apply -march to clang as well as gcc
For x64 and x86_32 configurations, apply the -march flag to both GCC and
Clang flags.

This solves the problem of Clang-compiled coreboot failing due to Clang
emitting SSE instructions for code that is executed while SSE is not
enabled.

This patch takes functionality targeted for GCC configurations and moves
it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order
that it applies to both GCC and Clang.

This is an alternate patch to CB:32887.

Signed-off-by: Alan Green <avg@google.com>
Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-28 20:33:37 +00:00
Jacob Garber 298afb3140 util/romcc: Add extra null pointer check
It is possible that 'lnode->val' is set to 0 on a previous iteration of
the loop, so check that it is non-null here before dereferencing it.

Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:02:18 +00:00
Jacob Garber 9742ae1d11 util/romcc: Fix memory leak
The 'new_type' function already allocates memory, so it is only
necessary to clone the existing type if this function is not called.

Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity Scan CID 1129106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:02:07 +00:00
Jacob Garber 4b688ab3fe util/romcc: Add null check for filename
It is possible that 'filename' is still null in this if statement,
so we add an extra check to prevent a null dereference in strcmp.

Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1395330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:01:57 +00:00
Jacob Garber b4222a65ad util/romcc: Add extra NULL checks for member
In each of these cases it is possible that 'member' is NULL at the
beginning, which will skip the earlier while loops entirely and cause
a NULL dereference later on. Add extra error checks to prevent this.

Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129147, 1129152, 1129153, 1129154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:01:42 +00:00
Evgeny Zinoviev 7687617d00 util/autoport: Mention i2c-i801 module in readme.md
SMBus adapter will not appear if i2c-i801 module is not loaded.
Added it to the readme.

Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-23 08:59:48 +00:00
Elyes HAOUAS fa40e82270 util/sconfig: Move 'static' at beginning of declaration
When using -Werror=old-style-declaration, gcc reports an error:
"'static' is not at beginning of declaration"

Tested on 945G-M4 board.

Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-22 10:09:33 +00:00
Jacob Garber 9b0d8e7a1f util/romcc: Prevent out-of-bounds read
If 'class > LAST_REGC', then there will be an out-of-bounds read when
accessing 'regcm_bound'. Prevent this by skipping to the next iteration
of the loop. Note that this should not generally happen anyway, since
'result' represents a bitset for the indices of 'regcm_bound', and so
iterations where 'class > LAST_REGC' should already be skipped by the
previous continue statement (since those bits of 'result' should all be
zero).

Found-by: Covericy CID 1129122
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Id5f5adb0a292763251054aeecf2a5b87a11297b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-22 10:03:11 +00:00
Jacob Garber ae8301fddb util/romcc: Fix parsing of empty string literal
The corner case of an empty string literal was causing romcc to
segfault. This checks if the literal is empty, and if so allocates a
size one buffer for the terminating null character. A test case for
this is added to ensure it doesn't happen again.

Found-by: Coverity CID 1129099
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I067160a3b9998184f44e4878ef6269f372fe68bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21 09:28:36 +00:00
Jacob Garber b79d2dee2b util/romcc: Free variable after it is used
Free 'arg_type' after it is used to prevent a memory leak.

Found-by: Coverity Scan CID 1129114
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5e8661547bb7623463ed23fc45269049ffb8c50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21 09:27:57 +00:00
Jacob Garber 40a85f85c6 util/romcc: Use 64 bit integers when shifting
'used_indices' is 64 bits wide, so use a fixed-width type to make
that clear. As such, 'index' can have a value of up to 63, so use a
64 bit integer when doing the shifts to prevent overflow.

Found-by: Coverity Scan CID 1287090
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ibd089df6be60c8ea46da11e5e83cd58b2e2c54d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32854
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-21 09:27:03 +00:00
Elyes HAOUAS bd96a84300 util: Fix typo on plural form of index
Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-05-20 14:45:35 +00:00
Jett Rink 1eeb94ff4a util/scripts: update references to cross-repo-cherrypick
It appears that the rebase.sh script was renamed to
cross-repo-cherrypick and changed directories. Update comments to
reflect that change.

Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-20 14:44:08 +00:00
Alex James 7aeeb48390 util/lint/check-style: Don't hardcode clang-format path
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I688cb60c98370bf74aa8554bab43594ff84c4e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-15 19:46:39 +00:00
Elyes HAOUAS 65209de411 autoport: Remove unneeded include <arch/io.h>
Change-Id: I7cb4b47e2fd893274303bb20dc7fa895830b4493
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-15 17:58:20 +00:00
Christian Walter 9a8c5e7ac0 util/inteltool: Add Kabylake E3-1200 Support
Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-15 17:21:39 +00:00
Elyes HAOUAS c15e600490 crossgcc: Upgrade acpica to version 20190509
Changes: https://acpica.org/node/170

Change-Id: I6779a20005ffc0d4781bb60de3ba48759ef67d40
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-13 09:32:24 +00:00
Jacob Garber a75440739d util/inteltool: Use appropriate channel for printing timings
At least one channel must be present, so print an error if there is
not. However, we cannot always assume it will be the first channel,
so make the appropriate selection when printing the timings.

Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:24:14 +00:00
Jacob Garber 554e55b0f0 util/kconfig: Use snprintf to avoid buffer overflow
'name' and 'env' are supposed to be file system paths,
but could overflow the buffer if configured incorrectly.
Let's avoid that entirely.

Found-by: Coverity Scan #1362515
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I1aef36819d49ebcbde1c51995dc0961c85e74150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13 09:14:42 +00:00
Jacob Garber 4fbd22e38d util/intelvbttool: Add error checking for memory allocation
It is possible that 'malloc_fo_sub' and 'remalloc_fo' can
fail, so add appropriate error checks for those cases.
This incidentally fixes a possible memory leak when
'malloc_fo_sub' succeeds but 'remalloc_fo' does not.

Found-by: Coverity Scan #1396050
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:12:35 +00:00
Jacob Garber 2be617b58b util/intelvbttool: Free file object on error path
Prevents a memory leak.

Found-by: Coverity Scan #1396047
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:12:27 +00:00
Jacob Garber 9bb0461fbd util/ifdtool: Add find_fd null check
As the previous comment indicated, this null check is
currently superfluous, but adding it in makes Coverity
happy, and future-proofs the code in case someone changes
the internals of 'find_fcba' later and forgets/doesn't know
to update this error check.

Found-by: Coverity Scan #1395066
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:12:14 +00:00
Nico Huber 772a154d39 nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.

TEST=Played tint on kontron/ktqm77. Score 606

Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-12 15:03:03 +00:00
Joel Kitching 2eb89c8b14 vboot: include vb2_sha.h when required
Should include vb2_sha.h header when SHA library functions or
constants are required.  This replaces NEED_VB2_SHA_LIBRARY.

BUG=b:124141368, chromium:956474
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1583820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-09 06:32:44 +00:00
Elyes HAOUAS 1d3b3c3c09 {src,util}: Remove duplicated includes
Change-Id: Id09cec6b2aae58b131b208e96fec539d068ff68a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-07 16:15:56 +00:00
Patrick Rudolph ac24d3c311 sconfig: Add SMBIOS type 9 entries
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.

smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)

Example:

    device pci 1c.1 on
        smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
    end # PCIe Port #2 Integrated Wireless LAN

Tested on Lenovo T520.

Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-07 16:04:56 +00:00
Felix Singer 0a7543db2d inteltool: Add Sunrise Point-LP Skylake PCH IDs
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.

This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.

Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)

Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:38:49 +00:00
T Michael Turney 101098c41a sdm845: Combine BB with QC-Sec for ROM boot
TEST=build & run

Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03 21:59:05 +00:00
Furquan Shaikh 4d99b27018 util/sconfig: Throw an error if override tree has no devices
If override tree does not have any device, then the chip info
structure in it cannot be associated with the correct device and ends
up being added as a standalone chip info structure without any device
actually using it. This change prevents this condition by throwing an
error during compilation.

BUG=b:130342895

Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-04-24 16:23:51 +00:00
Patrick Rudolph e28fa4049d cbfstool: Fix cbfs_file_next_attr
The last attribute was never returned.
Fix size compare to retrieve all attributes.

Manually tested and seen all attributes, including the last one.

Change-Id: I08df073158a0f285f96048c92aa8066fa4f57e6f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23 10:23:56 +00:00
Elyes HAOUAS 5f28639a93 crossgcc: Update acpica to version 20190215
Support for ACPI specification version 6.3:

Add PCC operation region support for the AML interpreter. This adds PCC
operation region support in the AML interpreter and a default handler for
acpiexec. The change also renames the PCC region address space keyword to
PlatformCommChannel.

Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG.
These methods provide OSPM with health information and device boot
status.

PDTT: Add TriggerOrder to the PCC Identifier structure. The field value
defines if the trigger needs to be invoked by OSPM before or at the end
of kernel crash dump processing/handling operation.

SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT
is used for describing devices such as heterogeneous processors,
accelerators, GPUs, and IO devices with integrated compute or DMA
engines.

MADT: Add support for statistical profiling in GICC. Statistical
profiling extension (SPE) is an architecture-specific feature for ARM.

MADT: Add online capable flag. If this bit is set, system hardware
supports enabling this processor during OS runtime.

New Error Disconnect Recover Notification value. There are a number of
scenarios where system Firmware in collaboration with hardware may
disconnect one or more devices from the rest of the system for purposes
of error containment. Firmware can use this new notification value to
alert OSPM of such a removal.

PPTT: New additional fields in Processor Structure Flags. These flags
provide more information about processor topology.

NFIT/Disassembler: Change a field name from "Address Range" to "Region
Type".

HMAT updates: make several existing fields to be reserved as well as
rename subtable 0 to "memory proximity domain attributes".

GTDT: Add support for new GTDT Revision 3. This revision adds information
for the EL2 timer.

iASL: Update the HMAT example template for new fields.

iASL: Add support for the new revision of the GTDT (Rev 3).

More changes in this version at https://acpica.org/node/166

Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-23 10:03:12 +00:00
Elyes HAOUAS b1f4d52580 crossgcc: Update CMake to version 3.14.2
Release Note :
https://cmake.org/cmake/help/v3.14/release/3.14.html
"The FindFontconfig module added by 3.14.0 accidentally used uppercase
FONTCONFIG_* variable names that do not match our conventions.
3.14.1 revises the module to use Fontconfig_* variable names.
This is incompatible with 3.14.0 but since the module is new in the 3.14
series usage should not yet be widespread"

Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23 10:03:06 +00:00
Elyes HAOUAS 095c2617a3 crossgcc: Upgrade GCC to version 8.3.0
Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23 10:03:01 +00:00
Thejaswani Putta 6f5225c7e0 Klocwork: Fix the Null pointer derefernce found by klocwork
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32290
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 09:56:37 +00:00
Robin Broda 21f9b3ecd7 util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to supported PCI devices
Signed-off-by: Robin Broda <robin@broda.me>
Change-Id: I0f9e83b3bdf35e3e3e119ffcb93b092121a67666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:55:31 +00:00
Elyes HAOUAS 75380d3a16 src/mb/Kconfig: Fix PCI subsystem IDs
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed
in commits

 dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem()
 00bb441 sb/intel/lynxpoint: Remove PCI bridge function

Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19 17:48:15 +00:00
Martin Roth 26c43b7a77 util/docker: Update JRE in coreboot-jenkins-node Dockerfile
openjdk-8-jre-headless is no longer available in the debian image we're
basing the coreboot-sdk off of.  Update it to 'default-jre-headless'.

Change-Id: I60f6ecbaedccc0da61f96e0bce4122406ba4bd91
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-17 14:48:32 +00:00
Patrick Georgi e8367c0c5e util/genbuild_h: Prefer iasl from .xcompile over a hard code
build.h provides iasl's version but right now assumes that it's kept in
util/crossgcc/xgcc/bin. Often true, but not always, so use the one found
in .xcompile to query the version as that's the version that is used in
coreboot builds.

Change-Id: Iaeedc22e0e14fa96b4f2a68127f405c7f0c9d5cc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-15 16:35:09 +00:00