The Alder Lake chipset has several more reserved memory regions that
are unavailable to the resource allocator than are currently marked
as such in the system agent code. This CL adds the following regions
(documented in Intel docs #626540, #619503):
1. TSEG
2. GSM
3. DSM
4. PCH_RESERVED
5. CRAB_ABORT
6. APIC
7. TPM
8. LT_SECURITY
Claimed regions before this change:
========================================================
base 0 size a0000 // 0 - > 0xa0000
base a0000 size 20000 // legacy VGA
base c0000 size 40000 // RAM
base c0000 size 76f40000 // 0xc0000 -> top_of_ram
base 77000000 size 9400000 // top_of_ram -> TOLUD
base c0000000 size 10000000 // PCIEXBAR
base f8000000 size 2000000 // MMSPI
base fb000000 size 1000 // REGBAR
base fed80000 size 4000 // EDRAMBAR
base fed84000 size 1000 // TBT0BAR
base fed85000 size 1000 // TBT1BAR
base fed86000 size 1000 // TBT2BAR
base fed87000 size 1000 // TBT3BAR
base fed90000 size 1000 // GFXVTBAR
base fed91000 size 1000 // VTVC0BAR
base fed92000 size 1000 // IPUVTBAR
base feda0000 size 1000 // DMIBAR
base feda1000 size 1000 // EPBAR
base fedc0000 size 20000 // MCHBAR
base 100000000 size 17fc00000 // 4GiB -> TOUUD
Claimed regions with this change:
========================================================
base 0 size a0000 // 0 - > 0xa0000
base a0000 size 20000 // legacy VGA
base c0000 size 40000 // RAM
base c0000 size 76f40000 // 0xc0000 -> top_of_ram
base 77000000 size 9400000 // top_of_ram -> TOLUD
base 7b800000 size 800000 // TSEG
base 7c000000 size 800000 // GSM
base 7c800000 size 3c00000 // DSM
base c0000000 size 10000000 // PCIEXBAR
base f8000000 size 2000000 // MMSPI
base fb000000 size 1000 // REGBAR
base fc800000 size 2000000 // PCH_RESERVED
base feb00000 size 80000 // CRAB_ABORT
base fec00000 size 100000 // APIC
base fed40000 size 10000 // TPM
base fed50000 size 20000 // LT_SECURITY
base fed80000 size 4000 // EDRAMBAR
base fed84000 size 1000 // TBT0BAR
base fed85000 size 1000 // TBT1BAR
base fed86000 size 1000 // TBT2BAR
base fed87000 size 1000 // TBT3BAR
base fed90000 size 1000 // GFXVTBAR
base fed91000 size 1000 // VTVC0BAR
base fed92000 size 1000 // IPUVTBAR
base feda0000 size 1000 // DMIBAR
base feda1000 size 1000 // EPBAR
base fedc0000 size 20000 // MCHBAR
base 100000000 size 17fc00000 // 4GiB -> TOUUD
BUG=b:149830546
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705. Also ran dmseg,
and saw the added regions in e820 prints.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I058a5c1cc59703e35ceddb8a7e26fb22a6a2b75e
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
see https://review.coreboot.org/c/coreboot/+/65072/8
BUG=b:149830546
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.
Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64677
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mch_id is set to zero and then unnecessarily tested.
TEST=build and boot image on ADL RVP board
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I20734e1638714027b976043b3a0457cbf3cd8442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65121
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MSR_VR_MISC_CONFIG2 is not used by AlderLake code.
TEST=compilation check
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Alder Lake S CPUs do not have IPU device.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I79b084273f407119d903ed6f0cadf0084e8dda6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
On some systems, the Chrome EC controls both the USB Type-C mux as well
as the retimer. Introduce a boolean property "mode-switch" to denote
switches which act as a mode-switch.
BUG=b:235834631
TEST=None
BRANCH=None
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: If209a8529ff7ec424f23fd96875ac95a1fe6267d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
GCC_CFLAGS_<arch> contains only the flags that are GCC specific, iow.
flags that don't work with Clang.
CFLAGS_<arch>, OTOH, contains all flags that should be used and auto-
matically includes GCC_CFLAGS_<arch> if GCC is selected.
Change-Id: I5ec15f169d51c7a32ca86e54a98a2ce0e3b51e6d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62248
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Payloads often just use one of the defconfigs for libpayload. When
the `Makefile.payload` was introduced, it also added dependencies
to pass a `make oldconfig` or `make defconfig` for the payload on
to libpayload. Turned out, this creates some dependency madness
when, for instance, `make oldconfig` gets called without a libpay-
load `.config` available, or when we try to include the `.config`
in the `Makefile`.
To make things worse, Kconfig's `Makefile` that is imported from
Linux contains some rarely used paths that are generally incompa-
tible to our environment. So let's get rid of the hard-to-control
automatism.
Payloads that don't want to use a libpayload defconfig need to
clear the `$(LIBPAYLOAD_DEFCONFIG)` variable and manually run
the respective config target to generate a `.config`. To fully
support this, the rule to create a `.config` via `defconfig` is
guarded by `$(LIBPAYLOAD_DEFCONFIG)`. Otherwise we'd have a
spurious, broken recipe when the variable is unset.
We keep the option to call libpayload targets with an `lp-` prefix
for convenience. The existing, explicit targets `lp-defconfig` and
`lp-oldconfig` are replaced with a pattern match, so all config
and other targets should work.
Change-Id: Ie3fcce58d98e248c7182cd47f2a797fe066dd18a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Warnings are treated as errors in build.
UBAR is declared inside APRT method which throws warning as follows
"Static OperationRegion should be declared outside control method"
Move UBAR outside APRT method to fix warning.
TEST=build brya with following changes without any warnings
1. Select ACPI_CONSOLE
2. Include <soc/intel/common/acpi/acpi_debug.asl>
3. Add APRT function in any asl file.
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I40c676fd0bbd529bcbded18dd248b918f47324d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Some SKUs of crota have VNN 1.05v bypass rails for additional
power savings in S0ix states. This patch uses FW_CONFIG to enable
that feature when run on the applicable SKUs.
BUG=b:233175019
BRANCH=none
TEST=emerge-brya coreboot and verified pass
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Iaade50f4fe821b7114b3e2d44bda0747816da11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This fixes following errors when building GA-945GCM-S2L with clang 14.0.5.
CC ramstage/cpu/x86/smm/smm_module_loader.o
src/cpu/x86/smm/smm_module_loader.c:180:10: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat]
region_offset(&cpus[i].stub_code), i);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/cpu/x86/smm/smm_module_loader.c:184:20: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat]
__func__, region_offset(&cpus[0].stub_code),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/cpu/x86/smm/smm_module_loader.c:185:10: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat]
region_offset(&cpus[i].stub_code), size);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
src/cpu/x86/smm/smm_module_loader.c:349:52: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat]
printk(BIOS_DEBUG, "%-12s [0x%lx-0x%lx]\n", name, region_offset(®ion),
~~~ ^~~~~~~~~~~~~~~~~~~~~~
%zx
src/cpu/x86/smm/smm_module_loader.c:350:9: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat]
region_end(®ion));
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I59f20aacf91cb50fb194a84082a643b34c6c1ae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65154
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
enable_cnvi_ddr_rfim enables DDR RFI mitigation feature, this feature
needs to be enabled for all brya variants. Currently, it's not enabled
for brya4es.
BUG=b:201724512
TEST=Build, boot brya4es and check function 3 in _DSM method under
\_SB.PCI0.WFA3
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6cc9d3e4721188dcbc8584596c9f3f89a737206f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65110
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Set the speed to I2C_SPEED_FAST in each speed_config so that the
speed_config is actually applied. Currently, the speed_config isn't
applied, so the hcnt/lcnt calculation falls back to rise_time_ns and
fall_time_ns, which are 0 since they're not set. This results in
frequencies around 300 kHz.
- Move the data hold time to the speed_config, ensuring that the
resulting sda_hold value remains the same.
- For nivviks and nereid, tune scl_lcnt and scl_hcnt for each bus to
give a frequency around 390 kHz.
- In the baseboard, keep default scl_lcnt and scl_hcnt values. These
work well for buses with a rise time around 100 ns, and can be used as
a starting point before tuning them for a specific variant.
BUG=b:229547183
TEST=Measure the clock frequency, tHIGH, tLOW and tVD;DAT on nivviks
and nereid and check they meet the spec.
nereid clock frequencies:
I2C0 - 387.9 kHz
I2C1 - 392.7 kHz
I2C3 - 386.3 kHz
I2C5 - 383.6 kHz
nivviks clock frequencies:
I2C0 - 387.67 kHz
I2C1 - 380.47 kHz
I2C2 - 388.51 kHz
I2C3 - 384.03 kHz
I2C5 - 389.09 kHz
Change-Id: I88a6cfcc893183385eb85a89489e5d270277e537
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64942
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
- MT53E512M32D2NP-046 WT:E
- H9HCNNNBKMMLXR-NEE
- K4U6E3S4AA-MGCR
- MT53E512M32D1NP-046 WT:B
- H54G46CYRBX267
- K4U6E3S4AB-MGCL
- K4U6E3S4AA-MGCL
BUG=b:235303242
BRANCH=dedede
TEST=build
Change-Id: Ie0ffdfed47b1791b990affd9eee262faede4b0c8
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65081
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Introduce a new field in the board settings EEPROM region to control
whether BIOS menu is to be enabled. This field will be used in EDK2
payload.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I0af81c9e70a0088caea6bc7e2b81eab9a123c0f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
change clk_src and clk_req to 4 for LAN_I225V based on
ADL_Moli_SC_MB_20220601.pdf.
BUG=b:235768639
TEST=emerge-brask coreboot and check LAN_I225V can connect.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I323726df84d07703402da9da44b1882a0cdc1e33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Remove the cnvi_bt_audio_offload because it is already probed in
variant.c for moli.
BUG=b:235426221
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I15077ca161b6283e764105d1c2fbc59ead1fd761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Apparently all nine HP Sandy/Ivy laptop variants select
MAINBOARD_USES_IFD_GBE_REGION. So let's move it to the COMMON section.
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: I48e0d03c59d3ba013b479b59df8a15a0f8d23c50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch implements API to sync between core
PRMRR(Processor Reserved Memory Range Registers).
Read PRMRR base and limit value from BSP and apply it on the
rest of the cores.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I720669139429afc3d8c8d15c0ce15f1524f22e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Currently, ADL FSP headers and RPL FSP headers differ. Set a RPL only
upd for adlrvp with Raptor Lake silicon. This code can be removed once
ADL and RPL start using the same FSP.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4e69323949233aa8c325a757b28b9d80cbdf4322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The general purpose PCIe clock outputs 0, 1 and 3 are used with their
corresponding clock request pins, so set the gpp_clk_config to
GPP_CLK_REQ for those and disable the unused output 2. This matches the
DXIO descriptor in port_descriptors.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In x86 processor as per Software Developer's manual there are 2 ways to
get CPU topology by querying the processor. BIOS can use CPUID
instruction using CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) as input or
CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) as an input. Both will return
valid CPU topology data.
While CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) returns data related to number
of threads, core and package, CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F)
provides more granular information regarding Die, package etc.
coreboot uses V2 to in order to query and return CPU topology data as of
now since that's the highest instruction of CPUID which is supported,
there is a mismatch in the way FSP processes the data.
FSP queries coreboot MP services to get CPU topology data which uses
structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or
CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since coreboot returns V2 data in
structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there
is hang observed on ADL_N CPUs.
To solve this problem coreboot should assign CPUID_EXTENDED_CPU_TOPOLOGY
data to processor_info_buffer->Location structure so remove use of
CPUID_EXTENDED_CPU_TOPOLOGY_V2
Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202
Files:
MdePkg/Include/Protocol/MpService.h#L182
UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127
UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120
Ref doc: Software Developer’s Manual volume 3 CH 8.9
BUG=b:220652104
TEST=Build and boot ADL-N RVP with debug FSP and verify CPU topology
value and observe system boots (no hang).
Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
`make clean` never thoroughly removed LinuxBoot build artifacts. This
change checks for kernel directories present in the project directory
and deletes all of them, if found.
Signed-off-by: Patrik Tesarik <patrik.tesarik@9elements.com>
Change-Id: Ia056ac6608e3631dfc270ba5c2f32216c3e1ac50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65098
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In addition to change CB:40316 this commit proposes a change of default
behavior inside of the LinuxBoot toolchain.
Currently the defaults build a LinuxBoot payload which boots into the
u-root shell and waits for input. In fact it does not deliver any
bootloader with it, but the build image is on the other hand rather
small.
This commit changes the defaults in a way that the LinuxBoot
bootloader will actually be able to boot a local or remote system image.
In consequence the build payload size is rather big, but accepted for a
working out-of-the-box startup behavior.
See discussion on that topic in the above mentioned change.
Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de>
Change-Id: Ieaba7e523aef10c467a8bea29ae323e22324b225
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40527
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the file template for creating a new variant of Nissa.
BUG=b:229550821
Signed-off-by: Shou-Chieh Hsu <shouchieh@google.com>
Change-Id: I04f75ff91f9851b82641f703ba950b04c22e2e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This change fixes wrong type-C port number for voxel. Voxel
uses tcss_usb3_port1 not tcss_usb3_port3.
BUG=b:231344977
BRANCH=volteer
TEST=Check the transactions are happening on correct port. Also checked
retimer firmware update on both the ports.
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Iba7b3b15296bed99d3626a6d53dfd59e8d20fe5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64022
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update configs for NixOS 22.05.
pulseaudio-modules-bt has been abandoned, and is superseded by
pulseaudio's native Bluetooth functionality. Thus, remove it.
Change-Id: Ic3b1dbc3c2ab092b576ba2151c93c74d4f298efc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Sabrina only has 4 PCIe clock outputs with corresponding clock request
pins available, so only make those 4 configurable in devicetree and
disable the rest unconditionally.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The u-root toolkit dropped the original uinit bootloader in the master
branch and respectively the systemboot-option in templates.go. In
consequence the LinuxBoot builds will boot into the u-root shell and
waiting for input. This commit enables the reuse of the -uinitcmd flag
to specify a command, which runs after the u-root init-process.
Systemboot as a bootloader wrapper will mimic a BIOS/UEFI boot device
selection. Other preselections, i.e. stboot and boot2 are implemented as
well. Custom strings or programs can be set as well, but they cannot
contain program flags. E.g. 'fbnetboot -class linuxboot' will not work,
because they aren't symlinkable.
This commit and its respective LinuxBoot builds with systemboot, none
and one custom option have been tested successfully on a UP squared
single board computer with the intended behavior.
Change-Id: I4ac3409040ea77a1836f90f43fba07d2cd05a952
Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is a breaking change for now when using latest u-root main, which
is the default behavior in LinuxBoot.
u-root switched to golang modules and therefore `go get` is not the
standard behavior anymore. The workaround for this is to pull the
repository and build directly in the directory for now. Another apporach
would be to use `go install $pkg@latest` to install the binary at that
particular version into the golang binary path.
Currently missing is a control structure to enable the build process for
legacy versions <v0.8.0.
Signed-off-by: Patrik Tesarik <patrik.tesarik@9elements.com>
Change-Id: Ifa03504da6fa321ffc6d2506b27ebd2e3ed9961b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65090
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Update SoC GPIO setting of unused I2C camera pins according to beadrix
schematics.
GPP_H6 : NF1 -> NC (AP_I2C_CAM_SDA)
GPP_H7 : NF1 -> NC (AP_I2C_CAM_SCL)
BRANCH=dedede
BUG=b:235005592
TEST=on beadrix, validated by beadrix's camera still working properly.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I8be57406a44096c764c1faa8f45267d08c4694fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64971
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel LPC devices have generic and fix IO decode ranges. This CL is
smarter about using generic ones, by using the fixed ones first.
Change-Id: Ifd98bcc639ee08d068956a33b0e12cc70211ca2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65097
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The APOB data in DRAM is larger than the 96 kBytes of RW_MRC_CACHE, so
it won't fit in the flash and makes soc_update_apob_cache return early
before writing the APOB data from DRAM into the flash with this warning:
[WARN ] RAM APOB data is too large 1db18 > 18000
Increasing the RW_MRC_CACHE size to 120 kByte fixes this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I763d20f504d4f5b7cea68f21f409de9a1035f440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64555
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The T6 of PS8640 power on sequence should be larger than 0ms, but it's
-0.062ms now. Add 100us delay between VRF12 and VCN33. The PS8640
power-on sequence is described in the "PS8640_DS_V1.4_20200210.docx".
BUG=b:235448279
BRANCH=None
TEST=The sequence T6 is larger than 0ms when power on.
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I0b8a37d6119dc027a9d1c0a62c087b0a7ef14cac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Some eMMCs (for example, Kingston-EMMC64G-TX29-HP) may enter the ready
state by sending CMD1 twice. If it is in the ready state, then the
payload (for example, depthcharge) will not send CMD1, but the access
mode is only available from the response of CMD1.
Therefore, we need to pass the access mode to the payload by defining
the following types:
- MMC_STATUS_CMD1_READY: in ready state and access mode is byte mode.
- MMC_STATUS_CMD1_READY_HCS: in ready state and access mode is sector
mode.
BUG=b:234672726
BRANCH=cherry
TEST=boot ok
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: Iad905781d8ba0105911cf87a6b845cd8df57521e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65054
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The TBT device can't be recognized after we re-plug it at DB type-c
port. Intel found that tbt_pcie_rp0 has mapping error after each
re-plug. From Intel suggestion, we enable TBT PCIe RP0 to fix this
problem and take this as short term solution. Intel will implement
re-mapping mechanism in ACPI for long term solution.
BUG=b:230141802
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I61429033dfe64d67916167bb901bdd8246db953e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make the config file reflect reality instead of using the old cezanne
copy.
TEST=Build chausie
BUG=b:220848549
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I8362bc19875ae152e0deab7f64d5b1c50929b95b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Modify the config file, consumed by amdfwtool, to use "sabrina" and
"SBR" named files.
TEST=build chausie using updated amd_blobs
BUG=b:220848549
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ia993644e67d14792d753cc74a957529d15be18f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM
features from RTD3.
TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3
are generated under the root port.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I74434d833086f639927d8369f8a6e3af31dd99e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64648
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Until FSP for RPL and ADL align, mainboards using RPL should select
SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together.
Currently, ADL FSP headers and RPL FSP headers differ. Use RPL FSP
header with Raptor Lake silicon. This code can be removed once ADL
and RPL start using the same FSP.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Iaf95352b9cafb81f23522bcf63753d199c0420eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The Sabrina APU has a maximum configuration of 4 physical cores with 2
threads each, so a total of 8 CPU cores.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I627ed78ffba6098726c9c8ec55b60665503240ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65068
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Eran Mitrani