Implements support code for talking to IPMI hardware that uses
a KCS style interface.
Change-Id: I9895cc1bf29676115b167081b63b8a430e23eee5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1190
Tested-by: build bot (Jenkins)
The Kconfig file for this board contains a bogus option called
CORE_GLIU, this change removes it.
Change-Id: I4ea069bdd76be53085ebc9c0fb3dd71ffb2a12e1
Signed-off-by: Ricardo Martins <rasmartins@gmail.com>
Reviewed-on: http://review.coreboot.org/1179
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
This is mostly necessary for reboot, but it doesn't hurt the boot process.
On reboot explicitely reset the integrated graphics, otherwise the VGABIOS
might not be able to reinitialize it properly, and you either have a still
of the last pre-reboot image, garbage or an empty screen, but no text-mode.
Change-Id: Ic3d6932fbaf720d88daaac7e4b09c3c0b9f0b0e2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1178
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The superiotool Makefile extracts a version string from SVN. This does not work
with a git repository, and results in an empty version string. Use the output of
'git describe' as version string instead.
Change-Id: Idf92c02753b28ef5bcdd3b6df4a08d79ae974434
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-on: http://review.coreboot.org/1151
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
PCI Type 2 config was a strange and never-used config mechanism.
It is unlikely that in the 13 years of coreboot's existence that
type 2 was ever used; it just made life complicated for everyone.
It lived long enough in coreboot to be replaced by mmioconf.
Prior to making the device tree visible in romstage we want to
get rid of type2.
Delete two files we don't need any more (yay!).
Replace two functions with one: pci_config_default, which returns
a pointer to the default config method. At some future time this
may change to mmio but for now it is old type1 style.
Change-Id: Icc4ccf379a89bfca8be43f305b68ab45d88bf0ab
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1159
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
The SIPI vector copy can use a static location below 1MB, aligned
to 4kB. Jump out of the copy once in protected mode.
Change-Id: I6299aa3448270663941cf2c4113efee74bcc7993
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1165
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set
in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup
would not cover the bottom 4 MB when ramstage is decompressed.
Verify CACHE_ROM_SIZE is power of two.
One may set CACHE_ROM_SIZE==0 to disable this cache.
Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1146
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Diff between model_106cx and model_6ex CAR codes suggests currently
used model_106cx CAR is not optimal - destination RAM and source ROM
of ramstage copy_and_run are only partly set cacheable.
It appears variable MTRR setting for XIP cache is left enabled on
model_106cx code, where it should have extended to cover all of Flash.
Introduces untested functional change on boards:
intel/d945gclf
iwave/iWRainbowG6
Deletes file:
model_106cx/cache_as_ram.inc
Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/642
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
A diff from model_6fx to model_106cx suggests there is little
CORE2 specific code that was once considered useful to have.
In its current status however, sockets supporting model_6fx use
model_6ex CAR init, so that specific code is actually
never used.
Deletes file:
model_6fx/cache_as_ram.inc
Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/640
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Used for automatic generation of IOAPIC interrupt entries.
Change-Id: Ia746f01906c840800956ce551306f864e440b6ec
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1137
Tested-by: build bot (Jenkins)
Default CPU_ADDR_BITS is 36.
For Atom (model_106cx) use 32. This model is known to
fail execution-in-place (XIP) with the default 36.
Pentium M should use 32, but doesn't even with this patch.
Some Xeon and CORE(2) models should use 38 or 40.
Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/639
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
used for fan control and thermal management on that board.
Change-Id: I4e5c986ab6174b7a356d682e21732c46181af211
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1167
Tested-by: build bot (Jenkins)
awk on Cygwin created the UTF-8 value for the 0xff code point,
which makes it two bytes wide. This broke the build.
Change-Id: I4937ae7ce1136ba7a76d05b42f9dd2771203175d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1164
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
With this change it is possible to define serial number
and version of the mainboard. These informations are used
in SMBIOS tables.
Change-Id: I1634882270f6cb94e00aceb7832e7fd14adc186b
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1163
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The error message from romstage is annoying and misleading:
"Do not use global variables in romstage"
Because it can occur even when global variables are not used
in some circumstances, but also because it gives you only a rough
idea where to look. This change sucks but sucks less. We still don't
know which file the problem is in but at least we know if it is data
or bss.
Replace the error message with something that provides more information
and less guessing on the part of the script:
".bss is non-zero size in romstage which is not allowed -- global variable?"
or
".data is non-zero size in romstage which is not allowed -- global variable?"
To test: build coreboot as normal. It builds.
Add
char d[32];
to romstage.c and get the first error message; add
int x = 32;
to romstage.c and get the second.
Change-Id: I300ec05bdb4b30d7ef3f5112e6cc09b1fafe8263
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1160
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The wrapper for Trinity. Support S3. Parme is a example board.
Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1156
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The new broadcast code doesn't support serial init - if a CPU
needs serial init, this should be handled in the model specific CPU
init code.
Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1140
Tested-by: build bot (Jenkins)
The current code for initializing AP cpus has several shortcomings:
- it assumes APIC IDs are sequential
- it uses only the BSP for determining the AP count, which is bad if
there's more than one physical CPU, and CPUs are of different type
Note that the new code call cpu->ops->init() in parallel, and therefore
some CPU code needs to be changed to address that. One example are old
Intel HT enabled CPUs which can't do microcode update in parallel.
Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1139
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Early HT-enabled CPUs do not serialize microcode updates within a core.
Solve this by running microcode updates on the thread with the smallest
lapic ID of a core only.
Also set MTRRs once per core only.
Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1142
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Correct registers base (PCI BAR) reading to be
more specification friendly. Registers base
only in [31-12] bits, all other proposed to be 0
but that not true for some motherboards. So
adding mask to use only valid bits.
Change-Id: I2e9a4997e016dab812ccfe654e966bc91d42a625
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1143
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As we using 16-bit reading and writing in UHCI drive,
so all variables related to that must be 16-bit too.
Change-Id: Ib1abb03d054c167512e21f24f3c3da688c7fd01f
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1144
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
They used MP_IRQ_TRIGGER_LEVEL, but it should be MP_IRQ_TRIGGER_EDGE.
While at it, uses mptable_lintsrc() instead.
Change-Id: Ie71311b8bf865889cf0d8808467df98af4b0132d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1136
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This adds basic supported for the Supermicro X7DB8. Basic means that
almost all onboard peripherals are working. Known problems are:
- mptable needs to be written dynamically. If you plan to use Add on
cards, modify mptable.c according to your needs. A patch to add generic
mptable autogeneration based on devicetree is coming up.
Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/493
Tested-by: build bot (Jenkins)
Required for Supermicro X7DB8, which needs the FBDIMM clock generator
setup during romstage.
Change-Id: I30ca8354087e851487aee0614595782131d4d9bc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1116
Tested-by: build bot (Jenkins)
Here's a quick demonstration on how to use it(tested on M4A785T-M).
(gdb) file ./build/cbfs/fallback/coreboot_ram.debug
Reading symbols from [...]/build/cbfs/fallback/coreboot_ram.debug...done.
(gdb) set remotebaud 115200
(gdb) target remote /dev/ttyUSB0
Remote debugging using /dev/ttyUSB0
_text () at src/arch/x86/lib/c_start.S:85
85 call hardwaremain
Change-Id: Ia49cbecc41deb061433bc39f5b81715da49edc98
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/1134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The length was not accounted for correctly.
Change-Id: If34f288ba9dee1cd19d60da1b9f3647b9593ac1f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1135
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
This sets the timeout for control and bulk transfers to 2s per
transfer descriptor (like we set it in the EHCI driver). It also adds
delays around the disabling of control and bulk list access to
overcome some race conditions.
Change-Id: Ia2d1db890fca51c7d9477de163d55030e0c5a04a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1127
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
commit 57cd1dd296 added this attribute,
but with wrong length, so it actually never matched.
Change-Id: Ibcc7816b5fa895faa66710cc29de38f129be6a2b
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1133
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
This adds a simple check if a device is really configured before
returning it's address to the usb hub driver who wants to attach it.
Change-Id: I6fea140217c3e7468cc48ef7c3cbf2be8d11f47a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1131
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This lets the init of usb mass storage return if the device
configuration is unusable. Also add some checks for proper shutdown so
we don't free/remove an uninitialized device.
Change-Id: I6daf9b38e632b6e381bcd5a7717f0f1a3150b64a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1130
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This makes it easier to use the same code on romcc and gcc.
Specifying attribute((unused)) on romcc does nothing.
Change-Id: If9a6900cad12900e499c4b8c91586511eb801987
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1132
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This adds support for usb interrupt transfers to the OHCI driver.
Basically this enables support for HID keyboard devices.
For each interrupt transfer endpoint, two queues of transfer
descriptors (TDs) are maintained: the first with initialized TDs
is linked to the periodic schedule of the host controller (HC), the
second holds processed TDs which will be polled by the usb class
driver. The HC moves processed TDs from its schedule to a done queue.
We periodically fetch all TDs from the done queue, to put them on the
queue associated with the endpoint, where they can be polled from.
Fully processed TDs (i.e. which have gone throuch all of this) will be
reinitialized and put on the first queue again.
Change-Id: Iaab72c04087b36c9f0f6e539e31b47060c190015
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1128
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This fixes some memory corruption, leaking and padding issues within
the initialization of the OHCI driver.
Change-Id: If6891f2a53e339d32c4324f4c9e0b1ed07596a60
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1126
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This adds correct processing of the done queue of the OHCI host
controller (HC). We will always process the done queue after a control
or bulk transfer. Unfortunately, it's hard to tell when the HC will
write out the done queue, so we have do free the transfer descriptors
later and have to allocate them one by one.
To distinguish different types of TDs (e.g. async vs. interrupt
transfers) on the done queue, they are flagged in the lsb of there
.config field. We can utilize this bit for our own purpose, as it's
reserved and the host controller won't interpret it and preserves its
state.
Change-Id: I3b2271ae6221cdd50fc0f94582afdfe52bf7e797
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1125
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
In ohci_private.h some invocations of a MASK macro were called with
its parameters interchanged. This fixes it with the hope not to break
anything nasty.
Change-Id: I56cb483b208442b497dbd32ce993cc53d1fba1e5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This enables logical detachment of unresponsive usb devices (i.e.
devices not responding to control transfers) in the usb mass storage
driver. Without the detection of unresponsive devices we wait way too
long for the device to become ready.
Change-Id: I8b8cf327f49dde25afaca4d3066f16ea86b99d3d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1121
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This introduces a dummy queue head in the interrupt frame list of the
EHCI host controller. It's a workaround for broken controllers which
follow pointers from this list even if the terminate bit is set.
Fortunately, they do honor the bit in queue heads and having an empty
QH in the list doesn't violate the standard.
The linux kernel has a similar workaround for AMD SB700, SB800, and
Hudson-2/3 platforms. We observed this bug with an AMD SB600.
Change-Id: Ibbb66dea5fddc89c7995a24d746bedf6bfa887be
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1124
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
If the queue of an interrupt transfer runs out, we have to reset
the queue head. This also introduces the use of a spare transfer
descriptor (TD) in interrupt queues, which assures, that a processed
TD won't be reused until the host controller has written it back
from his overlay.
Change-Id: Id0eeb2808b77f1c187f164eb34bd66f8f399938b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1123
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Tested with a bunch of usb flash sticks. The slowest non-TUR (test
unit ready) turn around took about 1.3s, so this commit increases the
timeout to 2s.
Change-Id: Iec64b5cc48d51912b2bdeeebb5885399a71311b2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1120
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
i3100/i5000 have a second IOAPIC which handles IRQs for PCI-X.
Add code to enable it.
Change-Id: Ib447628f501b152c8adc9c7c89bd09b5615b9e5a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1118
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Added reading registers base address for USB EHCI driver
in ehci_init() function.
Change-Id: I59443ca9823588d70822b4f14486caf217a5ac26
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The constant value 0x100000000 is used in linker scripts to calculate
offsets from the end of 32-bit-addressed memory. There is nothing
wrong with it, but 32-bit versions of ld do the calculation wrong.
Change-Id: I4e27c6fd0c864b4d98f686588bf78c7aa48bcba8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1129
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
As Mathias Krause pointed out, using movw/outw on %al is clearly invalid.
Let's do another typo fix...
Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1119
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
This implements status transport (CSW) more closely to the standard
(usbmassbulk_10).
Change-Id: Ife516316e054d4e87ebe698dc487eeb9ebcfd38d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1072
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Sven Schnelle