Just do it already.
The two SCSI-specific options for p2b-{ls,ds} will be wired up in a
followup. They will be ignored by boards without the hardware.
Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These p-suffixed helpers allow dropping pointer casts in call-sites,
which is particularly useful when accessing registers at an offset from
a base address. Move existing helpers in chipset code to arch/mmio.h and
create the rest accordingly.
Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 023fdaffd1 (mb/asus/p2b: Refactor southbridge ACPI stuff)
moved the southbridge ACPI stuff to its own file. It also
(prematurely) listed PM and SMBus I/O port ranges as a #defined
fixed value.
Since these two ranges are not expected to change at runtime anyway,
we can simply drop the ASL code doing the read.
Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Haswell MRC.bin can return zero even when raminit did not complete
successfully. When this happens, the memory controller will not have
acknowledged raminit: the mc_init_done_ack bit in the MC_INIT_STATE_G
register will be zero, and memory accesses will lock up the system.
To handle this situation more gracefully, check the mc_init_done_ack bit
after running MRC. If the bit is not set, log a fatal error and halt.
Tested on Asrock B85M Pro4:
- With badly-seated DIMMs, MRC raminit fails and coreboot dies.
- After reseating the DIMMs, the board still boots successfully.
Change-Id: I144bf827f65cd0be319c44bf3d407ddc116b129d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is locking up the OS. For now this will unblock booting.
BUG=b:183971103
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Add definitions to describe GPIOs in generated ACPI objects.
The method allow either write a GpioInt() or Interrupt() descriptor.
Signed-off-by: Seven Lee <wtli@nuvoton.com>
Change-Id: I37fec7b0b9324dbfb61b7a8bea80f45026c54409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51922
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using brackets here seems to break the build for _some_ environments.
Removing the brackets fixes it and works just fine.
Change-Id: I965b0356337fe74281e7f410fd2bf95c9d96ea93
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The define for color keyboard setting has never been used, as it was
added as a Kconfig selection when ec/system76/ec was introduced.
Change-Id: Iec9134e226382d32783342ef1d37c6f6f6caeb6e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The define for color keyboard setting has never been used, as it was
added as a Kconfig selection when ec/system76/ec was introduced.
Change-Id: I6c8f17b398fb4645feb830c2ad28ac98fb744280
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The define for color keyboard setting has never been used, as it was
added as a Kconfig selection when ec/system76/ec was introduced.
Change-Id: Ib83d4510c14ddf083660e42175ab093403792cac
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow.
This change ensures that SD3C is updated for the TCSS DMA devices
corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0
is updated, else for DMA1.
BUG=None
TEST=Built Alderlake image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current get panel_id is over sku_id() >> 4, but sku_id is combined with
wfc_id/lcm_id/sku_id, so the panel_id value is wfc_id << 4 | lcm_id()
in fact. When wfc_id is not 0, the panel_id will be wrong. So only get
the low 4 bits for the panel_id.
BUG=b:183779755
BRANCH=kukui
TEST=emerge-kukui
Change-Id: I63e0c8a2719462a9b979afe52a27c78b9fc804e8
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The EDID and initial code are provided by STA (the vendor).
BUG=b:183969078
TEST=Boots on Chromebook Katsu and displayed developer firmware screen
successfully.
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is a bug acknowledged by Intel (IPS case 00600003) that has been
fixed for SRP but won't be fixed for CPX.
This fixes field offsets for fields that follow SYSTEM_STATUS.RcVersion
Change-Id: I5248734e2f086d39bb75b7b1359e60dfd8704200
Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
VENDORCODE_ELTAN_MBOOT should not be used when VBOOT is enabled.
Hide VENDOCODE_ELTAN_MBOOT when VBOOT is enabled.
BUG = N/A
TEST = run `make menuconfig` and boot Facebook FBG1701
Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
All known on-chip PCI devices are disabled in the chipset devicetree.
So they are removed from the mainboard devicetree.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Ie67cd8afc9ea92e9fd7caed4338cb25a68d94cb1
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The romstage does not fit in RO_SECTION.
Increase the CBFS size in RO_SECTION.
BUG = N/A
TEST = Boot Facebook FBG1701 with VBOOT enabled.
Change-Id: I2f1020acb3ec99d4cddbaa05b0998fe32b470d3e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some functions/macros like assert() require redefinition for testing
purposes. ENV_TEST is introduced to make it possible without using
bypass hacks.
This patch also adds a global __TEST__ define to TEST_CFLAGS for
all test targets in order to enable ENV_TEST.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ib8f2932902a73a7dbe181adc82cc18437abb48e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48671
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST
complete" to the BMC. According to the schematics and the code in
`ramstage.c`, the signal is active-low. There is an external pull-up
resistor.
To make the signalling work as it should, set the initial output value
to `high`.
Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48670
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TPM_INIT depends on VBOOT but should also depend on
VENDORCODE_ELTAN_xBOOT.
Add dependency. TPM_INIT will be enable for measured boot only.
BUG = NA
TEST = Boot Facebook FB1701 with possible combinaties of VBOOT, measured
boot and eltan security.
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I03f8457731c73c653bd82b1042bda3fc2d797feb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
The ERROR() and LOG() macros both used BIOS_ERR as the error level.
The messages generated by the LOG() macro are informational items.
Change to BIOS_INFO to reflect that.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I3827a7d65a9d70045a36fb8db4b2c129e1045122
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The tree is clean at the moment.
Change-Id: I1be3b6c2f3b54b5c10ad3d5c6f0a6fd7e490c6bc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52066
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The recent refactor of console UART GPIOs to mainboard's bootblock
caused brya boards to lose the first ~5 lines of the logs from
bootblock. Rename bootblock_mainboard_init to
bootblock_mainboard_early_init so that the UART pads will be ready
by the time the console is initialized.
BUG=b:184319828
TEST=First lines from report_platform.c are now seen in UART output
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The calloc() function is useful in addition to malloc and friends, so
add the obvious definition.
Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51949
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To pack a struct, the `__packed` attribute must come after the `struct`
keyword. Moreover, unions cannot be packed (structs inside unions can,
though). Correct uses of `__packed` so that EEPROM structs get packed.
Change-Id: I39d2c9ebc370605d5623b134189aa95a074ec7c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Background story (I think that's what great in opensource -
ppl leave there part of their lives): ;-)
While trying to fix audio jack not working with coreboot and
Windows 10 with some help from hell__ and nico_h on IRC nico_h
discovered that t420 and t430 hda_verb.c are the same:
<nico_h> oddly, in coreboot source T420 and T430 have the same
numbers for very different codecs... I suspect copy-pasta
Difference between /sys/class/sound/cardX/hwCXDY/init_pin_config
in vendor BIOS helped with the updated config. Connecting audio
jack now works flawless both in Linux and Windows.
Audio-related keyboard buttons: volup, voldown, mute works fine
both in Linux (Debian-based) and Windows 10. mutemic button works
(tested ie. with xev) but both in Linux and Windows 10 wont light
up or makes any effect.
+-----------------------------------+
| init_pin_config dump from: |
+----= VENDOR =---+---= coreboot =--+
| 0x19 0x04211040 | 0x19 0x04211040 |
| 0x1a 0x61a19050 | 0x1a 0x61a19050 |
| 0x1b 0x04a11060 | 0x1b 0x04a11060 |
| 0x1c 0x6121401f | 0x1c 0x6121401f |
| 0x1d 0x40f001f0 | 0x1d 0x40f001f0 |
| 0x1e 0x40f001f0 | 0x1e 0x40f001f0 |
| 0x1f 0x90170110 | 0x1f 0x90170110 |
| 0x20 0x40f001f0 | 0x20 0x40f001f0 |
| 0x22 0x40f001f0 | 0x22 0x40f001f0 |
| 0x23 0x90a60170 | 0x23 0x90a60170 |
+-----------------+-----------------+
Tested-by: Piotr Szymaniak
Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl>
Change-Id: Ie5eba84e5ea590b7db00e189cd68e714bee7e410
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51612
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The only FSP 1.1 platform with MMA support is Skylake. As it now uses
Kaby Lake FSP 2.0, this code is no longer useful. Drop it.
Change-Id: I819c3152bdea0fdad629793d96136ef134429fbd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add SPD support for Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb
BUG=b:184024142
TEST=none
Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The Intel FSP 2.0 driver contains a custom construct that basically
serves the same purpose as the new CBFS allocator concept: a callback
function to customize placement of a loaded CBFS file whose size is
initially unknown. This patch removes the existing implementation and
replaces it with a CBFS allocator.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0b7b446a0d2af87ec337fb80ad54f2d404e69668
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Right before CB:49334 was submitted, I changed the signature of
cbfs_allocator_t function pointers to include another argument passing
in the already loaded CBFS metadata (to allow for the rare edge case of
allocators needing to read CBFS attributes). This interface is not meant
to be able to modify the passed-in metadata, so to clarify that and
prevent potential errors, we should declare the argument const.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7e3756490b9ad7ded91268c61797cef36c4118ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable I2C2 in devicetree and fill ACPI information for Codec and
Speaker amplifiers. Pass correct IRQ GPIO for headset jack.
BUG=None
BRANCH=None
TEST=Ensure that the Codec and Speaker Amplifiers are detected in
i2cdetect.
Change-Id: I1ae52a8bbaa0181c906cd14a94de22e0250ed4c1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52046
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the BT disable GPIO to logic low in order to enable Bluetooth.
Add USB ACPI configuration for BT device.
BUG=b:182201890
TEST=Build and boot to OS.
Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is a copy of picasso.
BUG=b:184151560
TEST=Compared with the cezanne PPR.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia4bc40daa971c126c2596837155312d411b91a06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Configure camera power GPIO to high
BUG=b:182207799
TEST=Build and boot to OS then checked camera device existence with lsusb
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Initialize all eSPI signals including PCIE_RST0_L early for EC
communication.
- Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is
a temporary workaround until PCIE_RST_L comes up on its own.
- Make sure all GPIO muxes initialized early are re-initialized.
BUG=b:183340503
TEST=Boot Guybrush
Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Keith Hui