The `ramtop` can be obtained from the `option.h`, so remove the
hardcoded value. Keep the check for the value being byte aligned.
Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74511
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid
logo.bmp file if `BMP_LOGO` config is enabled.
TEST=Able to see splash screen while booting google/marasov
with BMP_LOGO config enable.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I421da2b4dadb892f17a859ce0ec586a2880469eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75294
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid
logo.bmp file if `BMP_LOGO` config is enabled.
TEST=Able to see splash screen while booting Intel Meteor Lake RVP
with BMP_LOGO config enable.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaba187456dd4dfb2f69d3532e83a3850f31783ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75198
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
To match the rest of coreboot, also change this ACPI_CPU_STRING Kconfig
setting to use hexadecimal CPU numbers for the ACPI CPU objects. Since
this SoC has a maximum of 4 cores, this change will make no difference
in the runtime behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I58f9c4672f34de0defafc300d2d291f4ad6196ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75251
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both the AMD AGESA reference code and the default coreboot
ACPI_CPU_STRING use hexadecimal numbers in the ACPI CPU object names, so
change the ACPI_CPU_STRING format string in the both the Stoneyridge
Kconfig and the common non-CAR AMD SoC config Kconfig which covers all
other AMD SoCs in soc/amd. All platforms where the P state and C state
SSDT from binaryPI (Stoneyridge) or FSP (Picasso) was used in coreboot
before it got replaced by native code, had at most 8 cores/threads, so
the mismatch never became apparent.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d6822c5df01786ee541ce90734b75ed1a761fca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75250
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the chromeec driver to use the EC host command API. Large blocks
of repetitive code to set up EC calls are replaced with single function
calls to perform the same operation.
BUG=b:258126464
BRANCH=none
TEST=booted on rex
Change-Id: I0317405b1ed0c58568078133c17c8cfbc7c21d80
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73325
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The new util/chromeos/update_ec_headers.sh utility is used to update
ec_commands.h and introduce ec_cmd_api.h from the chrome EC repo.
ec_cmd_api.h is a new file from the chrome EC repo which defines the API
for communicating with the EC. It is a companion to the existing
ec_commands.h by defining functions corresponding to EC host command
opcodes and request/response struct definitions.
See $EC/docs/ec-host-command-api.md for details.
Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
3e35858003 ec: Add another #line directive
The original include/ec_cmd_api.h version in the EC repo is:
59de61f2db zephyr: Add support for RNG devices
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: I30f20e34d31b7e19cf03f65fefd58ae64eef1d41
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73324
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a new utility for copying ec_commands.h and ec_cmd_api.h from
the chrome EC repo with the appropriate copyright header adjustment.
It is invoked as:
util/chromeos/update_ec_headers.sh [EC-repo]
where EC-repo is the top of the EC repo from which header files are to
be obtained.
The corresponding files in src/ec/google/chromeec are updated but not
committed. Also, a commit message is suggested with the original git
versions for reference.
BUG=b:258126464
Change-Id: Ib43c75d807dd925b2c4bff425c07a36b4b4582c4
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Traditionally, display init during vboot "verified/secure/normal
boot mode" relies on the VB2_CONTEXT_DISPLAY_INIT. This is the
default behavior for vboot, meaning skip display init during verified
boot mode.
However, if the intention is to show the OEM splash screen (using
BMP_LOGO config) during boot, then the policy enforced by vboot needs
to be overridden. This can be done by setting the BMP_LOGO config flag.
If BMP_LOGO is not enabled, then the vboot policy will be followed and
display init will be skipped.
This change was made to allow OEMs to show their splash screen during
boot, even if the system is in verified/secure/normal mode.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ice1f02ad5c02a6a7e74a97ed23c5f11c7ecfb594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75197
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Generate formatted string and ACPI code to print debug string.
For example (with pcie_rp = 1):
acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp);
generates the following ACPI code:
Debug = "calling _ON for RP: 1"
With this new function, the following functions are not needed anymore
and therefore are removed by this patch.
- acpigen_concatenate_string_string()
- acpigen_concatenate_string_int()
- acpigen_write_debug_concatenate_string_string()
- acpigen_write_debug_concatenate_string_int()
BRANCH=firmware-brya-14505.B
TEST=Add above functions in the acpigen code and check the generated
SSDT table after OS boot. Check the debug messages is in the
kernel log when /sys/modules/acpi/parameters/aml_debug_output is
set to '1'.
Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Musse Abdullahi <musse.abdullahi@intel.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Fix the error below when running a coreboot image built with
`CONFIG_UBSAN=y`.
PCI: pci_scan_bus for bus 00
shift out of bounds src/arch/x86/include/arch/pci_io_cfg.h:13:20
ubsan: unrecoverable error.
GCC with `-fsanitize=shift` also flags this:
runtime error: left shift of 1 by 31 places cannot be represented in type 'int'
So, make the constant unsigned.
TEST=emulation/qemu-i440fx with `CONFIG_UBSAN=y` stops later with
[ERROR] unaligned access src/lib/rmodule.c:152:27
[EMERG] ubsan: unrecoverable error.
Change-Id: Ib05d225ab9f22078d765009b4ee6ef0c63231eed
Found-by: UBSAN
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Taniks uses a 4-channel output config, rather than 2-channel.
Update the SOF speaker topology accordingly.
TEST=build/boot Win11 on taniks, verify speaker output functional.
Change-Id: I3c08b12b11464dcada014289174e0cc468d1c39d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Will allow boards using this speaker configuration to correctly specify
their output type.
TEST=tested with rest of patch train
Change-Id: Iefcfc928e2611f533af1a2962ec2761ec1b7bf3a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
By moving certain FW UI assets from RO to RW sections, 4 MiB is
sufficient for RO section. Split the resultant available 4 MiB equally
between 2 RW sections. This will help in getting to 16 MiB SPI flash for
the mainboard.
BUG=b:281567816
TEST=Build Myst BIOS image with the updated layout.
Cq-Depend: chromium:4519688
Change-Id: I09948ceac0a6a1cb109322fc4856b8b486318664
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75184
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Update USB port macros:
- change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1,
HUB to USB 2.0 headers, HUB to rear USB 2.0
- change USB type C header to LONG which caused hard lockups on the
port making it unable to enumerate in UEFI Payload and Linux
- add empty definitions for USBr ports
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69820
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
copy from dibbi since taranza base on dibbi,this is only for first
initial configuration, will update the more setting afterward.
BUG=b:277664211
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
BUG=b:277664211
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I6bbb67ccdd8ebc21719921d00320907f8dbb285f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74933
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since it's not obvious, add comments to acpigen_resource_word,
acpigen_resource_dword and acpigen_resource_qword to clarify out what
the magic number in byte 0 means. The most significant bit of byte 0
indicates if it is a small or large resource data type. In the case of
the MSB being 0, it's a small resource data type (aka type 0), and the
other bits encode bit the type and size of the item; if the MSB is 1,
it's a large resource data type (aka type 1), and the other bits just
encode the type and there are two separate bytes to encode the size.
Beware that the large resource's data type values in the ACPI
specification don't include the MSB that's set, but only the 7 lower
bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6a6c9fb1bcde232122bb5899b9a0983ef48e12b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The detachable Starmie will use MIPI panels, which require reading
serializable data from the CBFS. So we add MIPI panel support to the
display configuration and align the configuration sequence with the
panels that use MIPI bridges.
The PMIC Datasheet:
TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf
BUG=b:275470328
BRANCH=corsola
TEST=emerge-corsola coreboot chromeos-bootimage and display normally
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I6f079e54f0317ff2f685f0e3834ebd1ceb8e9fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Error message ´Cannot map compressed file config without cbfs_cache' is reported.
Compressed parts of CBFS can not be used during bootblock stage.
Remove config from mb_log_list.
Will be added to verified items by CB:74752.
BUG=NA
TEST=booting and verify log on facebook FBG1701
Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set the default soft fuse bits to the recommended values
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2354aefe90a08eaef95a68926806d11a9118c3de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
When using a 32-MiB ROM chip, the ABL leaves the SPI flash in 4-byte
addressing mode, so ensure the driver exits that mode for regular
operation.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9a846be743a65ffe5b3ef94e20e0b5fc5e273961
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Clang was already warning about this. Synchronize the behaviour between
both compilers.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I3331a7437b17ab5ac97cef94511bb29c020bdff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75032
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
TPM IRQ should be A20 not A13. RAM table is correct.
BUG=b:282164589
TEST=able to boot up
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I82a709cc280288d612c65697b8da3c4274d4cd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75191
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow schematic to correct I2C bus.
BUG=b:282164589
TEST=able to boot up
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I277e5190302c98dbce809d09c1a32fac758aa8e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Rather than requiring another Kconfig symbol to be set, reuse the same
`make V=1` command argument. This simplifies rebuilds with a single
point of reference.
Also, this means that coreboot doesn't have to be rebuilt due to Kconfig
changes.
Change-Id: I9eba86b234768641a215095b8657e9d07832b1b5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add _STA field entry for r8168 ACPI device and set to
ACPI_STATUS_DEVICE_HIDDEN_ON in order to hide device from
OS (Windows) as there is no driver needed (or available).
Windows correctly attaches drivers to the PCIe device, the
separate ACPI device is unused and unneeded.
Linux is unaffected as it does not use the ACPI device status.
Change-Id: Ib7ae99fffcb00e71421b93c2794119841aa239d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75177
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach. Change the interrupt type
from EDGE to LEVEL.
TEST=build/boot samsung/lumpy, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.
Change-Id: Ie4268b4de5779ee148699c7bef8c700a99816f1e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach.
TEST=build/boot google/parrot, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.
Change-Id: Ic164244eceb52221653bd60f7217f9a09e38c1b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach. Change the interrupt type
from EDGE to LEVEL.
TEST=build/boot google/butterfly, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.
Change-Id: I971795becfb05fb42921ff6f40a20892f4f5654a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use board-specific ASL for PS2-attached trackpad rather than the EC/SIO
default, so that Windows installs a multitouch-capable driver rather
than the standard PS2 mouse driver.
TEST=build/boot Win11 on google/stout, verify trackpad is multitouch
capable.
Change-Id: Id93bbe53f35b1e2c35e36d8175889786b9f5de8b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75176
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add _HID to parent SIO device so Windows can find the PS2K, and
remove _ADR since HID and ADR are mutually exclusive.
TEST=build/boot Win11 on samsung/lumpy, verify keyboard functional.
Change-Id: I7b6b09da1a3fdc34ef43789c699f7fd22b4b655b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add _HID to parent SIO device so Windows can find the PS2K, and
remove _ADR since HID and ADR are mutually exclusive.
TEST=build/boot Win11 on google/butterfly, verify keyboard functional.
Change-Id: I772ceef1b439cfd4e2740e53362bee9d494fb36d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In ACPI 1.0 the processor objects were inside the \_PR scope, but since
ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some
firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS
compatibility, but apart from that the \_PR scope is deprecated.
coreboot already uses the \_SB scope for the processor devices
everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the
format string inside the 3 snprintf statements that use the
ACPI_CPU_STRING.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Don't set bit 2 of the return value of the _STA method in order for
Windows not to show a warning about an unknown device in the device
manager for this device.
TEST=The unknown device with device instance path ACPI\AMD0040\3
disappeared from the device manager in Windows 10 build 19045 on a
Mandolin board with a Picasso APU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If005f06843956004c281fd70cf364171148cb9ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68962
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 396fb3db74 ("soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB
device") didn't only change the visibility of the device, but also
changed the _STA method to a name. While this worked, the specification
says that _STA is supposed to be a method, so change it back to being a
method.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0932b2875aaf563a4dbd860bdd11a04272e3780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75169
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sean Rhodes