This maintains a 32bit monotonically increasing boot counter
that is stored in CMOS and logged on every non-S3 boot when
the event log is initialized.
In CMOS the count is prefixed with a 16bit signature and
appended with a 16bit checksum.
This counter is incremented in sandybridge early_init which is
called by romstage. It is incremented early in order notice
when reboots happen after memory init.
The counter is then logged when ELOG is initialized and will
store the boot count as part of a 'System boot; event.
Reboot a few times and look for 'System boot' events in the
event log and check that they are increasing. Also verify
that the counter does NOT increase when resuming from S3.
171 | 2012-06-23 16:02:55 | System boot | 285
176 | 2012-06-23 16:26:00 | System boot | 286
182 | 2012-06-23 16:27:04 | System boot | 287
189 | 2012-06-23 16:31:10 | System boot | 288
Change-Id: I23faeafcf155edfd10aa6882598b3883575f8a33
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1315
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
MRC returns specific error codes; print the according error
message if we know what it means.
Change-Id: Iaaf1512b9d577d4291fccfb94d879043ab5b11b5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1289
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The count was only incrementing for a wake from S5 and
it was not incrementing in the normal reboot case.
Change-Id: I73bc6db6bd02e6c4677f7e44a5c098c6dcb51747
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1328
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge
and 0x20 for sandybridge. Move this code to ramstage
and set it per-chipset.
Power Aware Interrupt Routing is supported in ivybridge,
enable it and set fixed priority.
Boot on ivybridge device and read MCHBAR 0x5f10:
mmio_read8 0xfed15f10
0x30
And verify PAIR is enabled (bit4=1):
mmio_read8 0xfed15418
0x24
Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1303
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Ivybridge B0+ CPUs are capable of supporting multiple TDP levels.
This complicates the default case because now the registers that
were reporting max non-turbo ratio are reporting that value for
the highest possible TDP level.
For now this change just forces everything to use the Nominal TDP
values instead of the higher (or lower) levels.
- When building P-state tables, determine the P[1] (max non turbo)
ratio based on the Nominal ratio if available.
- Set the turbo activation ratio to the Nominal max ratio.
- Mirror the power level settings in new MCHBAR register after
they are written, which happens after BIOS_RESET_CPL is set.
- Set the current ratio to Nominal ratio at boot.
1) Verify that P-state table is generated properly with
P[0]=1801MHz (ratio 0x1C) and P[1]=1800MHz (ratio 0x12)
PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00
PSS: 1800MHz power 17000 control 0x1200 status 0x1200
2) Verify power limits in MCHBAR match PKG_POWER_LIMIT:
> rdmsr 0 0x610
0x800080aa00dc8088
> mmio_read32 0xfed159a4
0x000080aa
> mmio_read32 0xfed159a0
0x00dc8088
3) Verify turbo activation ratio is set to nominal ratio:
> rdmsr 0 0x64c
0x0000000000000012
4) Check that proper ratio was set at boot on one core only:
> grep 'frequency set to' /sys/firmware/log
model_x06ax: frequency set to 1800
model_x06ax: frequency set to 1800
model_x06ax: frequency set to 1800
model_x06ax: frequency set to 1800
Change-Id: I592e60a7740f31b140986a8269dca91b4adbb270
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1304
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
... and don't require it to specify a cache type.
This function is only used on romcc boards, and should go away
(because all boards should be switched to CAR)
Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1288
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
On systems with socketed CPUs we want to be able to
drop in a Sandy Bridge or Ivy Bridge CPU without recompiling the
firmware. Hence, detect the north bridge dynamically. In order
for this to work, we need Ivy Bridge MRC and coreboot configured
for Ivy Bridge.
Change-Id: I635bef2c61d47d36a3fdd87f8ecb6e69097ba969
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1281
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The function is empty (a left-over from i945) and should be removed.
Change-Id: I91e573b5e37cb9133ea1037aef7e6daf3c292864
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1290
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This lets the SPI driver and the LPC driver know about HM70 and NM70.
Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1300
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Right now, if we have an unknown PCH, coreboot will print something like
this:
PCH type: Unknown rev id 4
Instead, it should also print the PCI ID of the device, so we can add it
to the list of known PCHes.
Change-Id: Ib0b96e287c36d2895d1287b1734ca13d75e7985a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1287
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This is as per Intel's suggestion on how to display their name strings.
Change-Id: Ie82341305e58baa8041e50a61a11b395fa7d9582
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1298
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
When no valid MRC cache area is found, the mrc_cache data structure
was used without prior initialization. This sometimes caused a long
delay when booting because compute_ip_checksum would checksum up to
4GB of memory.
Change-Id: I6a0ca1aa618838bbc3d042be425700fc34b427f2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1277
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- The unneeded poll on non-MT force-wake bit was timing out
and causing the gma_pm_init_pre_vbios() function to exit
early so it was not preparing PM registers properly.
I changed the gtt_poll() calls to not return on timeout
unless it can't proceed so we don't see half-initialized
registers.
- RC6+ (Deep Render Standby) is not working reliably so we
can just enable RC6 in the BIOS and let the kernel decide
if it wants to enable RC6+ later.
This Kernel message is new in kernel 3.4:
[drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off
Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1268
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It's shut down, but UMA memory is not reclaimed. A later extension
could optionally do the magic register dance that allows initialization
of IGD as secondary graphics device.
Change-Id: I2a92bb71755005b886a8e1825325c678a9991bf2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1252
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Set the default location of hudson firmware to 3rdparty.
Move UMA code from mainboard to northbridge.
Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1241
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It defaults to true, and isn't disabled anywhere in the tree.
I also couldn't think of a case where it's actually useful.
Change-Id: I126a47625d5294f3cfff225629f2a948a83c9b7e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1250
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
One could not pass a device of type APIC to PCI resource functions.
The correct CPU model specific cpu->ops is set at later time in
cpu_initialize().
Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Northbridge code incorrectly adjusted the last cacheable memory
resource to accomodate room for UMA framebuffer. If system had
4GB or more memory that last resource is not below 4GB and not
the one where UMA is located.
There are three consequences:
The last entry in coreboot memory table is reduced by uma_memory_size.
Due the incorrect code in northbridge code state.tomk,
end of last resource below 4GB, had not been adjusted.
Incrementing that by uma_memory_size diverts a region
possibly claimed for MMIO to RAM, as TOP_MEM is written.
Since the UMA framebuffer did not have IORESOURCE_CACHEABLE,
it was ignored from the MTRR setup and not set uncacheable.
The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs,
should be copied from BSP to all APs instead of deriving the data
separately for each Logical CPU.
Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1217
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
These boards had identical UMA code:
amd/dbm690t
amd/pistachio
technexion/tim5690
technexion/tim8690
The ones below had whitespace or debug level change
compared to the one above:
kontron/kt690
siemens/sitemp_g1p1
These boards use AMDFAM10 guidelines in code:
asrock/939a785gmh
amd/mahogany
Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1210
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Following boards had identical code:
advansus/a785e-i
amd/bimini_fam10
amd/mahogany_fam10
asus/m5a88-v
avalue/eax-785e
gigabyte/ma78gm
iei/kino-780am2-fam10
jetway/pa78vm5
Following boards had identical code:
amd/tilapia_fam10
asus/m4a78-em
asus/m4a785-m
gigabyte/ma785gm
gigabyte/ma785gmt
In between the two, only whitespace difference.
Change-Id: Iaa48cc7b0038ebcc81be49219b4fc87670aa9941
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Following boards had identical code:
amd/inagua
amd/persimmon
The following had only whitespace or debug level changes
compared to ones above.
amd/union_station
amd/south_station
asrock/e350m1
Change-Id: I11ee46e06e1dd510cba551166189ebcaa144464b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.
It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.
Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Like ram_resource(), but reserved and not cacheable.
Switch all AMD northbridges to use this one.
Change-Id: I88515c6a0f59f80fd8607c390d0d4a2a35d805f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The current code didn't reserve static resource the right way.
Also reduce TOLM to 0xd0000000, because those boards have so many PCI
devices that 0xe0000000 isn't sufficient.
Change-Id: Ia75a81905eea1a096aed464b63ac154e044bc99c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1220
Tested-by: build bot (Jenkins)
Don't stop if RAM init fails at first try. It's better to restart
and try again instead of failing on the first try if the second
try would have worked.
Change-Id: Ib5660265d5b10a01588f2e4022dac2ee34f2c6d0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1191
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
This is mostly necessary for reboot, but it doesn't hurt the boot process.
On reboot explicitely reset the integrated graphics, otherwise the VGABIOS
might not be able to reinitialize it properly, and you either have a still
of the last pre-reboot image, garbage or an empty screen, but no text-mode.
Change-Id: Ic3d6932fbaf720d88daaac7e4b09c3c0b9f0b0e2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1178
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The wrapper for Trinity. Support S3. Parme is a example board.
Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1156
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The constant value 0x100000000 is used in linker scripts to calculate
offsets from the end of 32-bit-addressed memory. There is nothing
wrong with it, but 32-bit versions of ld do the calculation wrong.
Change-Id: I4e27c6fd0c864b4d98f686588bf78c7aa48bcba8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1129
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
As Mathias Krause pointed out, using movw/outw on %al is clearly invalid.
Let's do another typo fix...
Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1119
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Peter and Ron pointed out two typos. They have no side effects, but
it's still worth to fix them.
Change-Id: I9aecccdbc72beb2623fbe558a06e4f1b050f6e74
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1117
Tested-by: build bot (Jenkins)
Not doing a hard reset leaves the BOFL0 register cleared, which
prevents the BSP selection from working. To make sure we start
with known values, use the SPAD0 register for soft reset detection.
If there's a value other than 0, do a hard reset.
Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1103
Tested-by: build bot (Jenkins)
Originally, ChromeBooks would get the offset of the MRC cache
from an entry in the u-boot device tree. Not everyone wants to
use u-boot on Sandybridge systems, however.
Since the new code (based on Kconfig) is now fully working, we
can drop the u-boot device tree remnants.
Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1051
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The MRC region is described by Kconfig variables, no further math
or parsing is required at this point.
Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1046
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Remove all the repeated sections of code in cbtypes.h and place it
in a common location. Add include dir in vendor code's Makefile.
Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/912
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Requirements:
- must be in ramstage (locking flash while executing code from there
might not work)
- must be after cbmem is reinitialized (so the mrc cache copy of the
current run can be found)
Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Separate Sandybridge from ChromeOS a bit
The Sandybridge code depends on chromeos features a whole lot.
As a first step, provide a code path to look up the MRC cache
without depending on u-boot.
- Move mrc cache handling to separate file
This enables us to handle the MRC cache from ramstage,
where we can write the flash safely (eg. to update the
cache).
Also teach it to lookup the current MRC cache from CBMEM,
as the original data block isn't available anymore.
After all the preparations, finally write to the SPI
as necessary. It's a simple round robin wear levelling
that erases the entire MRC cache region when it's full
and starts from the beginning.
Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} +
(manual tweak since it hit a false positive)
Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} +
Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1006
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This fixes my build when specifying an absolute path to the binary.
Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/987
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
It is important to have the system configuration reported as early as
possible to have a better idea what exact chipset the platform is
running with.
This change adds code to have an early coreboot module report the CPU
and PCH information. CPU info includes the 32 bit feature information
word, the symbolic processor brand string, and information about some
features support, as obtained through CPUID instructions.
The PCH information includes the symbolic device name and PCI device
version.
Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/975
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
- New table for GT1
- Updates to GT2 17W table
- New table for GT2 35W SKU
- New table for GT2 Other
This also includes a workaround to poll on a different register
when deasserting force wake. On some SKUs the kernel is hanging
when bringing up graphics unless this register is also polled.
Change-Id: I2badf62b464e901cfb0eaf4fc196f59111c71564
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/974
Tested-by: build bot (Jenkins)
zbao