Commit Graph

15883 Commits

Author SHA1 Message Date
Timothy Pearson 38629f51ad cpu/amd/model_10xxx: Clean up debugging statements
Change-Id: I6dff74b3857e1fb384aefc87b44e7679bd4aab07
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11948
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-10-23 19:59:40 +02:00
Timothy Pearson 76d4636e61 northbridge/amd/amdmct/mct_ddr3: Fix curly brace style violations
Change-Id: Ic27d404a7ed76b58043037e8b66097db6d664501
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11942
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-10-23 19:58:48 +02:00
Timothy Pearson 964aa839ca include/smbios: Update SMBIOS memory structures to version 2.8
Change-Id: Icda915933c4ebf3a735d9e1d4e4dbb1138a06b39
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11955
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
2015-10-23 19:58:17 +02:00
Patrick Georgi efb9d95523 intel/cougar_canyon2: fix build
The reintroduction of cougar_canyon2 crossed beams with the
moving the GMA display brightness data in ACPI into individual
mainboards.

Make things build again by having the board use the same default values
that it used to use automatically. They may be wrong, but no worse than
what was there before.

Change-Id: Id788034c38b42e1c35d9cd17e9bbb2ce49e3e91c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12132
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-23 11:38:53 +02:00
Stefan Reinauer 1ecf252c38 MAINTAINERS: Add script to test database and find maintainers
This utility should make it easier to complete and maintain
the database of coreboot subsystem maintainers (MAINTAINERS
file)

This will need a bit of tender love and care to print information
in an easily machine readable output for the build system, but its
a first start to query the maintainers database.

Build with:
   $ go build util/scripts/maintainers.go

Find a maintainer for a set of files with:
   $ ./maintainers Makefile Makefile.inc
   Makefile is in subsystem BUILD SYSTEM
   Maintainers:  [Patrick Georgi <patrick@georgi-clan.de>]
   Makefile.inc is in subsystem BUILD SYSTEM
   Maintainers:  [Patrick Georgi <patrick@georgi-clan.de>]

Check the maintainer database with:
   $ ./maintainers
   .gitignore has no subsystem defined in MAINTAINERS
   .gitmodules has no subsystem defined in MAINTAINERS
   .gitreview has no subsystem defined in MAINTAINERS
   3rdparty/arm-trusted-firmware has no subsystem defined in MAINTAINERS
   3rdparty/blobs has no subsystem defined in MAINTAINERS
   3rdparty/vboot has no subsystem defined in MAINTAINERS
   COPYING has no subsystem defined in MAINTAINERS
   Documentation/AMD-S3.txt has no subsystem defined in MAINTAINERS
   Documentation/CorebootBuildingGuide.tex has no subsystem defined in MAINTAINERS
   Documentation/Doxyfile.coreboot has no subsystem defined in MAINTAINERS
   [..]

Change-Id: I49c43911971152b0e4d626ccdeb33c088e362695
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12119
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-23 01:47:39 +02:00
Timothy Pearson 33fb4cf0ff northbridge/amd/amdfam10: Fix typo in comment
Change-Id: I0a9b3a66231052622c862bae32b900f52f6efba9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11944
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-10-23 01:19:20 +02:00
Stefan Reinauer 3a043c47a9 cbfstool: Fix tolower() calls on Cygwin
Cygwin complains:

cbfstool.c: 1075:5 error: array subscript has type 'char' [-Werror=char-subscripts]

so add an explicit cast.

Change-Id: Ie89153518d6af2bacce3f48fc7952fee17a688dd
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11666
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-23 01:07:01 +02:00
Nico Huber 8193b068d4 allocator: Page align memory mapped PCI resources
To help hypervisors to assign PCI devices individually to virtualization
guests, page align dynamically allocated MMIO resources.

Tested with kontron/ktqm77 which has dynamically configured onboard
devices on the root bus and secondary buses. Booted Linux and checked
the configuration with `lspci -v`. Got the configuration through Muen's
tools which are very picky about overlapping and alignment. Booted a
Muen based system that uses many onboard devices. GMA, xHCI and one NIC
(on a secondary bus) were verified to function properly.

Change-Id: I2b7115070e1ccad64565feff025289732c3b5e66
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12111
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-22 23:04:55 +02:00
Nico Huber 37743a913f cbfstool/Makefile: Also rm fmd_(parser|scanner).[ch] in clean
Change-Id: I783aa4b2319aaedd57ce9a67ca935392a611298f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12127
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22 23:02:40 +02:00
Nico Huber 5e731a7cfc cbfstool/Makefile: Drop unused, irritating definition of `obj`
Change-Id: Id8dda8a973dcf991ac494c2d50258d1b51e43c6a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22 23:02:01 +02:00
Nico Huber 954a55b950 gma ACPI: Make brightness levels a per board setting
Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.

Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-22 23:01:36 +02:00
Jonathan A. Kollasch 3404625bcc model_fxx/powernow: add dual core Socket F TDPs
Values based on correlation of brand strings, brand numbers and the TDP
listings on AMD's web site (Wikipedia for Athlon 64 FX-7x TDPs).

Change-Id: I7e6d12d0b6cc4fefc3f84076234c62c40e08304c
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10926
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-10-22 22:41:52 +02:00
Martin Roth bf6b83abe0 Revert "Remove sandybridge and ivybridge FSP code path"
Please don't remove chipsets and mainboards without discussion and input
from the owners. Someone was asking about cougar canyon 2 just a couple
of weeks ago - there's obviously still interest.

This reverts commit fb50124d22.

Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/12128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22 21:51:01 +02:00
Stefan Reinauer a4ffe8aa49 MAINTAINERS: Fix format for file entries (F:)
According to the documentation further up in the file:

F:   drivers/net/    all files in and below drivers/net
F:   drivers/net/*   all files in drivers/net, but not below
F:   */net/*         all files in "any top level directory"/net

Add trailing slashes to directory names.

Change-Id: I7bfd2eb2528a75fb6af79a990acb89f5e4251383
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12118
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-22 20:20:48 +02:00
Patrick Georgi 744729a4f0 libpayload: Add ptrdiff_t typedef
vboot2 in payloads (eg depthcharge) needs it.

Change-Id: I4e79ae29cc282c8680f21686befd35c4ff461b3a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-20 16:50:25 +02:00
Patrick Georgi 5c406459e8 Enable MULTIPLE_CBFS_INSTANCES on x86, too
It works there, we want it, disable that restriction.

Change-Id: Idc023775f0750c980c989bff10486550e4ad1374
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/12094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-20 16:39:00 +02:00
Nico Huber 0859991c4b Revert "coreboot_table: don't add CMOS checksum twice."
This reverts commit e660651824.

After some discussion on IRC we decided to revert it as libpayload can
only read the copy that was removed (and other users like nvramtool can
only read the other copy). So we need both copies at this time.

Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db
Reviewed-on: http://review.coreboot.org/11696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-20 16:35:12 +02:00
Patrick Georgi 821bcd6456 cbfstool: Fix typo in error message
Change-Id: Iaee7e2c74fe9f63d4d4878278bd445af393942f4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11920
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-19 21:09:35 +02:00
Patrick Georgi 087477fd0e vendorcode/google: Deal with MULTIPLE_CBFS_INSTANCES
We need to special-case filling out the vboot structures when
we use CBFS instead of vboot's custom indexed format, otherwise
(due to the way the CBFS header looks), it will try to write several
million entries.

Change-Id: Ie1289d4a19060bac48089ff70e5cfc04a2de373f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11914
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-19 21:09:30 +02:00
Paul Menzel d98471ccb4 Makefile.inc: Put every tool in `TOOLLIST` on separate line
This way, commit differences will be easier to read. Also sort the list
lexicographically.

Change-Id: I4ce3ac9018a3fddf5e30d7c1ac0c57090fac1d3d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12084
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-18 16:39:08 +00:00
Paul Kocialkowski 3414561f00 armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
Some registers only allow word-sized or half-word-sized operations and will
cause a data fault when accessed with byte-sized operations.
However, the compiler may or may not break such an operation into smaller
(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
32 bit read/write and half-word-sized operations for 16 bit read/write.

This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.

The definitions for byte-sized memory operations are also adapted to stay
consistent with the rest.

Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11698
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-17 18:10:29 +00:00
Aaron Durbin 285111f822 cbfstool: Fix removing and adding file with same name
Currently, cbfstool regressed that removing a file from CBFS the space
is marked as empty but the filename is still shown, preventing adding a
file with the same name again. [1]

```
$ echo a > a
$ echo b > b
$ ./util/cbfstool/cbfstool  test.rom create -m x86 -s 1024
Created CBFS (capacity = 920 bytes)
$ ./util/cbfstool/cbfstool test.rom add -f a -n a -t raw
$ ./util/cbfstool/cbfstool test.rom add -f b -n b -t raw
$ cp test.rom test.rom.original
$ ./util/cbfstool/cbfstool test.rom remove  -n
$ diff -up <(hexdump -C test.rom.original) <(hexdump -C test.rom)
--- /dev/fd/63  2015-08-07 08:43:42.118430961 -0500
+++ /dev/fd/62  2015-08-07 08:43:42.114430961 -0500
@@ -1,4 +1,4 @@
-00000000  4c 41 52 43 48 49 56 45  00 00 00 02 00 00 00 50  |LARCHIVE.......P|
+00000000  4c 41 52 43 48 49 56 45  00 00 00 02 ff ff ff ff  |LARCHIVE........|
 00000010  00 00 00 00 00 00 00 28  61 00 00 00 00 00 00 00  |.......(a.......|
 00000020  00 00 00 00 00 00 00 00  61 0a ff ff ff ff ff ff  |........a.......|
 00000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
$ ./util/cbfstool/cbfstool test.rom add -f c -n c -t raw

$ ./util/cbfstool/cbfstool test.rom print
test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
alignment: 64 bytes, architecture: x86

Name                           Offset     Type         Size
c                              0x0        raw          2
b                              0x40       raw          2
(empty)                        0x80       null         792
```

So it is “deteled” as the type changed. But the name was not changed to
match the *(empty)* heuristic.

So also adapt the name when removing a file by writing a null byte to
the beginning of the name, so that the heuristic works. (Though remove
doesn't really clear contents.)

```
$ ./util/cbfstool/cbfstool test.rom remove  -n c
$ ./util/cbfstool/cbfstool test.rom print
test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
alignment: 64 bytes, architecture: x86

Name                           Offset     Type         Size
(empty)                        0x0        null         2
b                              0x40       raw          2
(empty)                        0x80       null         792
```

[1] http://www.coreboot.org/pipermail/coreboot/2015-August/080201.html

Change-Id: I033456ab10e3e1b402ac2374f3a887cefd3e5abf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11632
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-17 06:57:50 +00:00
Paul Menzel 831bbe8446 cbfstool/cbfs_image.c: Just use one space before `=`
Change-Id: Id31c889d1e83e7ddfb0f0f98b78601f37b71cfa2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11631
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:57:42 +00:00
Maxime de Roucy 8190078ad5 coreinfo: reboot when finished
Behave as nvramcui.
Avoid a "General Protection Fault Exception" when launched by SeaBIOS on
pcengines APU1.

Change-Id: I00b1f859f76e693e8d49a38c1e02f4f49add85b7
Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com>
Reviewed-on: http://review.coreboot.org/11731
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:55:54 +00:00
Paul Menzel dc1b3c162e libpayload/Kconfig: Use official spelling for TinyCurses
TinyCursess is officially spelled in CamelCase [1].

[1] https://github.com/tommyettinger/TinyCurses

Change-Id: I7e0aa5af54140796a981c0f4c58950b25fdd67ba
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11727
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:53:52 +00:00
Paul Menzel aa98eec316 libpayload/configs: Add default configuration with TinyCurses enabled
Change-Id: Ib057e2b5f15b8d5bcdf45666f8761614317d25ee
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11726
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:53:37 +00:00
Martin Roth de9adebb10 Add junit.xml code to top Makefile.inc instead of utils
Instead of adding code to generate the junit.xml file for jenkins to
each of the util makefiles, add it once to the top level Makefile.inc.

Create a list of tools to run the test on.
Add nvramtool and inteltool to the list of utilities tested.

Note that the util builds depend on implicit rules, so MFLAGS and
MAKEFLAGS have to be cleared to get the builds to work.

Change-Id: Id7ee5ea41ce3bf4a40fb50942ae785bb838fa639
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11910
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:45:01 +00:00
Nico Huber ee09d9c658 kontron/ktqm77: Tag all four USB3 ports switchable and SS capable
With the introduction of these options in commit b26156e
(bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.)
the default regressed to disable these capabilities. Maybe other boards
regressed too. I didn't check.

Change-Id: I220896e656d00145618e61d55b74904517c7d855
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11287
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:28:30 +00:00
Martin Roth 8d226f2dbf enable lint-stable build on jenkins
This will run the lint-stable scripts on jenkins to block a commit with
obvious and known errors.

It runs in under a second on my system, so shouldn't contribute to any
real delay on jenkins.

Change-Id: I6ff3468ec29dc4ccd0c115f2c26e26b291c507df
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11892
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-17 06:16:56 +00:00
Martin Roth 606ca51530 lint: Fix shellcheck warnings, add comments
When the script was pulled out of the makefile, it was left as it was
written in the makefile to show the continuity with the original.  This
patch cleans up issues identified by shellcheck and adds comments.

Change-Id: I5e6573a4fdfbb397e15db38e2e3dfadeb3430573
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11931
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:16:49 +00:00
Martin Roth b6d739d449 lint: Add junit.xml output for jenkins
To add lint to jenkins testing, we need junit.xml output.  This adds an
optional --junit command line parameter to enable output to an xml file
in the lint directory.

Change-Id: I5588190cb050b9dbe99458cb18a71a147769f50e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11891
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:16:40 +00:00
Martin Roth e4fc407e3f lint: Move the lint script out of Makefile.inc
In preparation for adding junit xml to the lint tests, move the
script out of Makefile.inc and into its own file.

Add a copyright, usage, and error checking that was not needed
inside the Makefile.

Change-Id: I32bebc6a5f1f6fa652812c8a014d84006e2e6c8a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11890
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:16:05 +00:00
Shawn Nematbakhsh 5266fe4d97 auron: Remove duplicate pei_data assignment
Merge artifact -- don't check spd_index twice.

BUG=None
TEST=Build only
BRANCH=Auron

Original-Change-Id: I0cc372fec415646854aa931949ed0f57b473cb01
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234421
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>

(cherry picked from commit 850125141b52886c845161434a1320676e59534d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0070e3f26ebddba716905ebb934bcec4715c4b05
Reviewed-on: http://review.coreboot.org/11912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2015-10-16 23:13:57 +00:00
Nico Huber 7b2f9f6994 intel/southbridge/bd82x6x: Add option to set SPI VSCC registers
These are needed for the hardware-sequencing function of the PCH SPI
interface. Values are specific to the flash chip used on a board.

Change-Id: Id06766b4bac2686406bc09b8afa02f311f40dee7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11798
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-10-16 22:47:22 +00:00
Tim Chen f3214d0248 auron: fix can not recognize 4G memory
Part of the following patch was lost in the merge from chromium.
This patch fixes up the spd_index for the copy from the SPD file.

In spd.c "spd_index *= SPD_LEN" will change the original spd_index
from gpio and let the following if(spd_index>3) to misjudge and
disable channel 1 incorrectly. So we calculate the index for spd file
memcpy when calling memcpy().

BUG=chrome-os-partner:32879
TEST=Can get total memory 4G on yuna 4G SKU
BRANCH=Auron

Original-Change-Id: Iebc49e20e4ca15ef6db8c4defe43cc22382a28bf
Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234420
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>

(cherry picked from commit 3b1fce58b7b4b15e947b40fd011174d4e8e294bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I03f9d63623e083c99d349d938fd802d828858f70
Reviewed-on: http://review.coreboot.org/11911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Georg Wicherski <gw@oxff.net>
Tested-by: build bot (Jenkins)
2015-10-16 22:41:17 +00:00
Timothy Pearson cbda504eec southbridge/amd/sr5650: Remove unnecessary register configuration
Do not hardcode the CPU downstream non-posted request limit; the
value of this register is CPU family specific and is set appropriately
in the corresponding CPU driver code.

Change-Id: I432b942f114243cba23c9a8d916cf6d07bc4740b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11935
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-16 21:25:28 +00:00
Timothy Pearson cfbcba5db8 arch/x86/smbios: Add Crucial DIMM manufacturer ID
Change-Id: I975142351c0c033f9dc44670dcf819d296896921
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11934
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-16 20:26:01 +00:00
Timothy Pearson ace3525e75 arch/x86/boot/smbios: Add SPD IDs for Kingston and Corsair
Change-Id: I6a32b69d3b75d7d086dc7f8ea1e195473399f406
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11933
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-16 20:25:18 +00:00
Timothy Pearson bea714088b util/cbmem: Fix failure with certain cbmem base alignments
Change-Id: Icd28af388c49ad36d7a8e414b3c82e18e1f8f523
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11932
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-16 20:23:33 +00:00
Paul Menzel 2ea25552e9 bootblock: Link timestamp.c only with EARLY_CBMEM_INIT
Commit dbeedbef (arch/x86/bootblock: Link in object files selected with
bootblock-y) breaks building of x86 boards with
`CONFIG_EARLY_CBMEM_INIT` *not* selected but CBMEM time stamp collection
enabled.

Aaron Durbin explained as below [1] and provided this patch to fix it.

> That change actually processes bootblock-objs where before it never did
> such a thing. I'm sure this isn’t the only issue lurking. bootblock on
> x86 implied romcc and thus all the bootblock-y += rules that other
> architectures use worked, but now all the implied assumptions are no
> longer true on x86.
>
> timestamp stuff on x86 !CONFIG_EARLY_CBMEM_INIT is the issue you're
> seeing. In order to compile timestamp.c for bootblock under these
> conditions will mean there needs to be some more Makefile guarding.

[1] http://review.coreboot.org/11864

Change-Id: I3441b9fcdbbc8bbe82b9f2075e60668a846ecf09
Fix-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-16 11:58:45 +00:00
Timothy Pearson 24e6d0445c cpu/amd/model_10xxx: Install AMD-provided microcode files in CBFS
Change-Id: I208b012c6b612a94b3bbc8235d5a005028be8bcc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11832
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-16 02:41:37 +00:00
Paul Menzel 6a70dbc397 cpu/x86/mtrr: Add MTRR index and total MTRRs to error message
Change-Id: I626a11c17c9d05c174c507d50684e498c8604cbc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11905
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-15 23:31:38 +00:00
Georg Wicherski 49ee5efea7 soc/intel/broadwell: fix USBDEBUG copy-pasta
The broadwell soc code was upstreamed based off an old coreboot branch
and apparently never tested with USBDEBUG.
This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine
board, as verified with a FT232H setup. The fix is simply removing
outdated code that since branching off had been deduplicated in upstream
coreboot, anyway.

Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: http://review.coreboot.org/11874
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-15 17:48:17 +00:00
Martin Roth 615f69e53d Update 'what-jenkins-does' makefile target for junit filename
Instead of renaming the junit filename, send abuild the desired
name on the command line.

Change-Id: I779bc180343bd549908750d7128bedbab7f36266
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11879
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-15 12:21:23 +00:00
Martin Roth 21ca9beda4 abuild: add a command line parameter for junit filename
The 'what-jenkins-does' makefile target was renaming the junit filename
after abuild finished.  Instead, just add a command line parameter to
send it to a different filename.

Change-Id: I66f7d80d621573d77a5154f36f2db49d7b2e948a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-15 12:21:19 +00:00
Kyösti Mälkki cd32da425c pcengines/apu1: Fill serial number in SMBIOS
Serial number is derived from the MAC address of first NIC.

Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11901
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-10-15 12:11:05 +00:00
Kyösti Mälkki 164dbd6a5c pcengines/apu1: Fix CRCs in SPD file
Do this to wipe error message and hexdump of SPD from console log.

Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11900
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15 12:09:06 +00:00
Kyösti Mälkki c82ab0adf5 pcengines/apu1: Fix SPD for 4GB model
Value of tRFCmin was incorrectly using 2 Gigabit chip data.
There was no observed instability or bug reports because of this.

Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11899
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15 12:08:42 +00:00
Patrick Georgi f50603176b ec/google: Move label to BOL to satisfy lint-tests
Change-Id: I3a42ba9494b5174920e36e3110b8d62d721fe742
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11886
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15 07:36:26 +00:00
Patrick Georgi b864de5752 nvidia/tegra210: Drop FSF address
Change-Id: Ia158b4c6c12fb6e22ea7fed9035574a3abedf98c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11885
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-15 07:36:20 +00:00