Commit Graph

42203 Commits

Author SHA1 Message Date
Jakub Czapiga 5ab67f9ef8 tests/lib/memset-test: Add missing malloc check and free on error
Coverity found resource leak in test setup function in error block.
Add malloc result check and free in error handling to silence Coverity.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Found-by: Coverity CID 1446760
Change-Id: Icf746df27167047fa3cf8f5df09fced20863f76d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-26 12:33:25 +00:00
Kyösti Mälkki d2b2a18307 Add Kconfig TPM
Defined as TPM1 || TPM2.

Change-Id: I18c26d6991c2ccf782a515a8e90a3eb82b53b0e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-26 12:31:10 +00:00
Yu-Ping Wu 0ed04569d7 mb/google/asurada: Allow payloads to enable USB VBUS
Configure GPIO CAM_PDN5 (AP_XHCI_INIT_DONE) as output, so that
payloads (for example depthcharge) can assert it to notify EC to enable
USB VBUS.

BUG=b:187149602
TEST=emerge-asurada coreboot
BRANCH=asurada

Change-Id: I3bf63f91b8057e35be2780024a8b398c3044729b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54902
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26 12:30:29 +00:00
Rocky Phagura b46a9e5ddb acpi/acpi: fix invalid checksum
Incorrect size of the einj structure was being used, which created an
invalid checksum message by the OS. This patch fixes the issue.

Test=Booted to Linux on Deltalake mainboard and verified invalid checksum
message is not logged in syslog. Exact message -> 'ACPI BIOS Warning
(bug): Incorrect checksum in table [EINJ] - 0xDA, should be 0xD9'

Change-Id: I2b1722d6960d4a62d14fb02ac5e8838397e12f92
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54787
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26 12:28:28 +00:00
Angel Pons 07056feba0 option: Decouple API from CMOS backend
Prepare to allow using other backends to store options.

Change-Id: I3f838d27bf476207c6dc8f2c1f15c3fa9ae47d87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-26 12:26:36 +00:00
Angel Pons b2a4c27a2f option.h: Correct `get_uint_option` return type
Commit 88dcb3179b (src: Retype option API to use unsigned integers)
changed the option API to use unsigned integers, but missed this.

Change-Id: I5deb17157db41c40cc72078e2af9cf65bdbe0581
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-26 12:25:53 +00:00
Paul Menzel a081583e3d soc/intel/common/block/smbus: Use `pci_dev_read_resources()` in read resources
scan-build found a dead assignment, that the value stored to `res` is
never read. Use `pci_dev_read_resources()` instead, as done in
`sb/intel/common/smbus_ops.c` since commit 5f734327
(sb/intel/common/smbus_ops.c: Clean up read resources) avoiding the
assignment.

Change-Id: Ic59063b05a45dca411bf5b56c1abf3dd66ff0437
Found-by: scan-build (coreboot toolchain v0ad5fbd48d 2020-12-24 - clang version 11.0.0)
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26 12:25:13 +00:00
Angel Pons e882269c11 qemu-q35,xeon_sp: Drop HAVE_SMI_HANDLER conditional with smm-class
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.

Change-Id: I64bdcb28a996609111861ebafe172493b0650354
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54852
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Rocky Phagura
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26 11:57:19 +00:00
Angel Pons 0cda8d2c50 mb/lenovo/t430: Do not set unused GNVS fields
ACPI code for this mainboard uses none of these values.

Change-Id: I429bf8dc229fd830ae662034a8b733c9ee669140
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54851
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26 11:56:38 +00:00
Wisley Chen a17ffd2640 mb/google/dedede: add haboki variant
haboki/habokay is the same design as drawlat/drawcia, and differs only
 in replacing Cr50 with discrete TPM.

BUG=b:187094464
TEST=FW_NAME=haboki emerge-keeby coreboot

Cq-Depend: chrome-internal:3850094
Change-Id: Id866927b7041c5bf1c73fb4f0c03798eb61efa79
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54755
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26 11:39:24 +00:00
Raul E Rangel 8fef0b7010 soc/amd/common/block/espi: Fix typo in espi_setup_periph_channel
ESPI_SLAVE_CHANNEL_READY is a read-only bit from the host perspective.
It is set when the eSPI peripheral has configured the channel.

We actually want to set the ESPI_SLAVE_CHANNEL_ENABLE flag. This never
caused an issue before because the peripheral channel is enabled by
default after PLTRST# is deasserted. This does fix the case where
periph_ch_en == 0. It now properly clears the enable flag.

BUG=b:188188172, b:188935533
TEST=Boot guybrush to OS, perform warm reset

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I24e0734d5652601ae9c967da528fec5e3f780991
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-26 11:37:32 +00:00
alex.miao 4a2887f381 soc/mediatek/mt8195: Initialize MCUPM
Load MCUPM firmware and boot up MCUPM in ramstage.

TEST=can see MCUPM log from AP console

Signed-off-by: alex.miao <alex.miao@mediatek.corp-partner.google.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I9e8c45ce7166644b94319ec2e7836d3d3c8008dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-26 07:33:01 +00:00
Rex-BC Chen 9cf07f0cb9 soc/mediatek: Move the MT8192 MCUPM driver to common
The MPUCM drivers can be shared by MT8192 and MT8195.

TEST=emerge-asurada coreboot;

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I07a66bcf5a149582f34df1cfd08b5514fc5c2eb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-26 07:32:51 +00:00
chun-jie.chen a36a68b027 soc/mediatek/mt8195: Change fsrc source to ulposc
Set fsrc source to ulposc_d10 for 26m off low power scenario.

Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com>
Change-Id: Ifb02d32820944d7cfbbf23de638e9a0e82b5e84d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54870
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26 07:32:44 +00:00
Trevor Wu fb5fa1abe7 mb/google/cherry: Support audio
Add GPIO "beep enable" for switching on and off.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: Iddb781e30fa90f05767cceeb83e623432540dcc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-26 07:32:39 +00:00
Dtrain Hsu 3d2297e13d mb/google/dedede/var/cret: Generate new SPD ID for new memory
Add new memory MT53E512M32D1NP-046 WT:B in the mem_parts_used.txt and
generate the SPD ID for the parts.

BUG=b:183057749
BRANCH=dedede
TEST=Build the cret board.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib797af858e8f7ea275291e552102db74f4724aad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25 22:33:09 +00:00
Ivy Jian a28419afcc mb/google/guybrush: Add Goodix touchscreen
Add Goodix touchscreen according to the Programming Guide Rev.0.7

BUG=b:188872893
TEST=build and boot into OS.
     check dmesg trying to add GDIX0000:00 device.

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I38c9bbf6e1c1531bf3524552db58c0bf183acbb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-25 22:32:37 +00:00
Raul E Rangel 0318dc169e soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10ms
The ChromeEC might take longer than 1ms for the peripheral channel to be
enabled. The PLTRST# interrupt handler takes about ~539us.
This doesn't account for the time it takes for the interrupt handler
to be scheduled. Increasing the timeout to 10ms gives ample time.

BUG=b:188188172, b:188935533
TEST=Boot guybrush and no longer see channel enable errors

Suggested-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25 15:20:27 +00:00
Arthur Heymans 0d93ca48c0 cpu/intel/fit: Fix top swap fit
The set_ts_fit_ptr makefile target was never a dependency of another
target and therefore not used.

Change-Id: Ie6b20164fce0dc406a28b4c1b9f41a79c68c27d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-25 12:36:47 +00:00
Arthur Heymans 448c9e19c5 cpu/intel/fit: Remove broken ifittool argument
'-t' is not needed when setting the FIT pointer and breaks
it as '-t' needs an argument so the $(TS_OPTIONS) is not properly
decoded.

Change-Id: I61a3ac1eda42e04152a7d10953bfb8407813d0f3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-25 12:35:40 +00:00
Tim Wawrzynczak 827ff248d0 soc/intel/alderlake: Fix SA_DEVFN_CPU_PCIE6_*
Change-Id: I8849f6dd2a9fdb16642de423cc82dcefd5b192ac
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54682
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25 12:33:41 +00:00
Iru Cai 6e3f048111 autoport: add a go.mod file
Go 1.16 needs this when running `go build` without GO111MODULE=off.

Change-Id: I9dcb134a68b7a726f1466a472a415c9558f60524
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25 12:27:00 +00:00
Arthur Heymans 749d2d70aa cpu/intel/fit: Make make fit entries depend on fit pointer
Make sure the fit pointer is set up before entries are added.

Change-Id: I285fbb830a52e43cde5e8db9569a64dafb4408df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-25 12:25:44 +00:00
Tony Huang 043426c85a mb/google/puff/var/dooly: Update CPU PSV to 85 degrees.
BUG=b:189053502
BRANCH=puff
TEST=build image and verified by thermal team.

Change-Id: Ic2337b9eabef158633c5e6dfa935ed5c8d3d76d1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54718
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24 19:58:44 +00:00
Tim Wawrzynczak 71f69ddc79 Revert "mb/google/brya/brya0: Manually probe fw_config for DB_LTE"
This reverts commit 2f8a7046bb.

Reason for revert: CB:54752 makes this unnecessary

Change-Id: I3ad0bcafe50e3eafb9a106720c6c9ea5cb0efc4f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54789
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24 16:55:47 +00:00
Furquan Shaikh 7f6ae79280 device: Consider fw_config probing in `is_dev_enabled()`
With the introduction of fw_config support in coreboot, it is possible
for mainboards to control the state of a device (on/off) in ramstage
using fw_config probe conditions. However, the device tree in
immutable in all other stages and hence `is_dev_enabled()` does not
really reflect the true state as in ramstage.

This change adds a call to `fw_config_probe_dev()` in
`is_dev_enabled()` when device tree is immutable (by checking
DEVTREE_EARLY) to first check if device is disabled because of device
probe conditions. If so, then it reports device as being
disabled. Else, dev->enabled is used to report the device state.

This allows early stages (bootblock, romstage) to use
`is_dev_enabled()` to get the true state of the device by taking probe
conditions into account and eliminates the need for each caller to
perform their own separate probing.

Change-Id: Ifede6775bda245cba199d3419aebd782dc690f2c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54752
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24 16:55:39 +00:00
Furquan Shaikh 665891e3a8 fw_config: Add helper function `fw_config_probe_dev`
This change adds a helper function `fw_config_probe_dev()` that allows
the caller to check if any of the probe conditions are true for any
given device. If device has no probe conditions or a matching probe
condition, then it returns true and provides the matching probe
condition back to caller (if provided with a valid pointer). Else, it
returns false. When fw_config support is disabled, this function
always returns true.

Change-Id: Ic2dae338e6fbd7755feb23ca86c50c42103f349b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54751
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24 16:55:27 +00:00
Furquan Shaikh e59ad2e0da sconfig: Emit probe_list in all stages
`probe_list` member in `struct device` is present in all stages,
however, util/sconfig emits the list only when !DEVTREE_EARLY. This
change ensures that `probe_list` is emitted in all stages. In follow
up changes, this is used to get the correct device state using probe
conditions.

Change-Id: I61f7e909d48b616ac2127a5a9f36bdf4817a5165
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-24 16:55:14 +00:00
Furquan Shaikh 17298c09de fw_config: Return false in `fw_config_probe` in unprovisioned case
fw_config is unprovisioned in the factory for the first boot. This is
the only case where fw_config is left unprovisioned. On first boot in
factory, fw_config gets correctly provisioned by the factory
toolkit. When fw_config is unprovisioned, it is not always possible to
make a guess which device to enable/disable since there can be certain
conflicting devices which can never be enabled at the same time. That
is the reason the original implementation of fw_config library kept
fw_config as 0 when it was unprovisioned.

CB:47956 ("fw_config: Use UNDEFINED_FW_CONFIG to mean unprovisioned")
added support for a special unprovisioned value to allow any callers
to identify this factory boot condition and take any appropriate
action required for this boot (Ideally, this would just involve
configuring any boot devices essential to getting to OS. All other
non-essential devices can be kept disabled until fw_config is properly
provisioned). However, CB:47956 missed handling the
`fw_config_probe()` function and resulted in silent change in behavior.

This change fixes the regression introduced by CB:47956 and returns
`false` in `fw_config_probe()` if fw_config is not provisioned yet.

Change-Id: Ic22cd650d3eb3a6016fa2e2775ea8272405ee23b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54750
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24 16:55:08 +00:00
lizhi7 5621a1e567 mb/google/dedede/var/sasukette: Enable ELAN touchpad
Add ELAN touchpad into devicetree for sasukette.

BUG=b:188376649
BRANCH=dedede
TEST=built sasukette firmware and verified touchpad function

Signed-off-by: lizhi7 <lizhi7@huaqin.corp-partner.google.com>
Change-Id: I898aeda936eb10ef4ead679a1c087060fad71a08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54369
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-22 14:12:04 +00:00
Tony Huang aefc75a4e9 mb/google/dedede/var/drawcia: Support Synaptics touchpad
Drawper would use synaptics touchpad.

BUG=b:184878424
TEST=emerge-dedede coreboot and check touchpad function work.

Change-Id: I2d2c205e19d8e3472e0fa7ca20fd38e381ac0de0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-22 14:10:52 +00:00
Kangheui Won 4020aa7a66 soc/amd: reduce MCACHE size with psp_verstage
The default of CBFS_MCACHE_SIZE is increased to 0x4000 in CB:54146 but
we have limited space on the PSP thus cannot afford it.

BUG=b:177091575
BRANCH=none

Signed-off-by: Kangheui Won <khwon@chrmoium.org>
Change-Id: I94dd782ae00d0b18ad6dd2fc061e4318bda88579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-22 05:47:23 +00:00
Dtrain Hsu c8b22418aa util/spd_tools/lp4x: Add new memory part to to global memory definition
This new definition is for MT53E512M32D1NP-046 WT:B used on Cret.

BUG=b:183057749
TEST=Generate SPDs

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ica5df61d96d2c4cbe62a560a53bd3bd08eb121f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-22 05:42:45 +00:00
Ivy Jian 83faea00f5 mb/google/mancomb: Update AMD I2S Machine Driver
Update ACPI HID to 10025682 for Machine driver probe

BUG=b:187912480
TEST=Build and boot to OS in Mancomb. Ensure that the sound card probed.

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5dc87c7a8fb876adc26165655f8f2d4157aa68c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54749
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-22 05:42:01 +00:00
Felix Held 53c83897c4 soc/amd/cezanne,picasso/reset: use byte I/O read for NCP_ERR
NCP_ERR is a 1 byte register in I/O-space, so use inb and not inw. The
variable the result gets assigned to is also a uint8_t.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9fd8c139004111d6227c0316ba2a8b0281541654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-22 05:40:47 +00:00
Patrick Georgi b2b5781bb4 util/crossgcc: Update acpica to 20210331
Change-Id: Ic517a2b9c9b7122d2a65f67380d3ce368303d725
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2021-05-22 05:39:05 +00:00
madhusudanarao amara 224181e477 mainboard/google/brya: Add SCI event EC_HOST_EVENT_USB_MUX
Send USB_MUX host event for the connect/disconnect type C devices.

BUG=none
BRANCH=None
TEST=manual tested USB connect/disconnect

Change-Id: I5a720e1f1ea42f200e0e4c98f42894e4b92c67f8
Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54725
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21 15:06:46 +00:00
Karthikeyan Ramasubramanian a1a8c2c621 mb/google/mancomb: Enable S0ix
BUG=b:188446049
TEST=Build and boot to OS in mancomb. Ensure that the system can suspend
and resume successfully. Ensure that the sleep state GPIOs are
reflecting the state as expected.

Change-Id: I43e86a07075fe66f89c2c5665adc209e985e4f04
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-21 11:23:24 +00:00
Sumeet R Pawnikar dd4861ae04 soc/intel/common: Add Alder Lake device IDs
Add Alder Lake specific Host and Graphics device IDs.
As per latest document number: 619501, these IDs got an update.

Change-Id: I548a903714ccc7470f1425ac67c0c66522437365
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54674
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21 11:23:12 +00:00
Felix Held 7608ea0c9f soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver
commit ce0e2a0140 (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.

BUG=b:169934025
TEST=BERT table that gets generated in a follow-up patch for Picasso
points to expected BERT region and Linux is able to access, decode and
display it.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21 11:22:59 +00:00
Arthur Heymans b192af12e3 security/tpm/tspi: Always measure the cache to pcr
Most of the time when INIT_BOOTBLOCK is selected, the cache should be
empty here anyway, so this is a no-op. But when it's not empty that
means the bootblock loaded some other file before it got to the TPM
init part (which is possible, for example, if hooks like
bootblock_soc_init() load something).

Change-Id: I4aea86c094abc951d7670838f12371fddaffaa90
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-05-21 11:22:51 +00:00
Tim Wawrzynczak 0dc82cc80b soc/intel/common: Add function to lpc_lib to return PIRQ routing
In order to fill out static entries for a _PRT table for
soc/intel/common, the PIRQ<->IRQ mapping is required. This patch adds
a function lpc_get_pch_pirq_routing() which returns this mapping.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib215fba54573c50a88aa4584442bd8d27ae017be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-21 11:22:14 +00:00
Tony Huang fae418777d mb/google/dedede/var/drawcia: Support HDMI VBT for Drawper
Drawper support LTE+HDMI,
so use DB_PORTS_1A_HDMI_LTE to select HDMI VBT output for it.

BUG=b:186393848
BRANCH=dedede
TEST=Build and boot to OS check HDMI output works.

Change-Id: Ibf34cce1e3cbfce8a71dce880c50f85db9295b1e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-21 11:22:05 +00:00
Tony Huang 576f3d00f9 mb/google/dedede: Add DB_PORTS FW_CONFIG in devicetree
DB_PORTS_1C_1A_LTE 6
DB_PORTS_1C 7
DB_PORTS_1A_HDMI_LTE 8

BUG=b:186393848
BRANCH=dedede
TEST=build pass

Change-Id: I8632960d7e538402bf033d07402116dac848f5ac
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-21 11:21:56 +00:00
Arthur Heymans b0ccac0971 security/tpm/tspi/crtm: Fix FMAP TPM PCR
TPM_RUNTIME_DATA_PCR is for "for measuring data which changes during
runtime e.g. CMOS, NVRAM..." according to comments. FMAP does not
change during runtime.

Change-Id: I23e61a2dc25cd1c1343fb438febaf8771d1c0621
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-05-21 11:21:05 +00:00
Matt Papageorge d981c49038 mb/google/mancomb: Enable some PCIe power saving features
Enable ASPM, Common Clock and Clock Power Managment. Accomplish this
by adding the options in the platform Kconfig as well as dxio
descriptors.

BUG=b:187743927
TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci

Change-Id: I9d6e606763798afc6b797d7d24ee7cae09f9e33f
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21 06:35:26 +00:00
Matt Papageorge c46bb69495 mb/google/guybrush: Enable some PCIe power saving features
Enable ASPM, Common Clock and Clock Power Managment. Accomplish this
by adding the options in the platform Kconfig as well as dxio
descriptors.

BUG=b:187743927
TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci

Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54282
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21 06:35:17 +00:00
Angel Pons 76619b01c8 Doc/releases: Mention that Asus H61 boards got squashed
Not physically squashed, the coreboot code got turned into a variant
setup with override devicetrees to drop redundant boilerplate.

Change-Id: I7ae5530d2603d6d108ef3829004de7e1cad130f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-20 21:11:14 +00:00
Ben Zhang f8b0eb8f3e mb/google/puff/var/dooly: Add gpio_keys for mic mute switch
UI monitors this input event and sends global mic mute command to CRAS
when the physical switch is toggled.

BUG=b:184593945
BRANCH=puff
TEST=build image and verify with evtest on DUT.
Apply crrev.com/c/2870806 with chrome cmdline flag and verify global
mute is triggered.
Verify sequences of switch toggle and suspend/resume.

Change-Id: Id89947885fdd96c5b5d598bda6db127daf298dc3
Signed-off-by: Ben Zhang <benzh@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20 20:40:54 +00:00
Ben Zhang 3246c5803c drivers/gpio_keys: Add SW_MUTE_DEVICE
Added SW_MUTE_DEVICE event type for mic mute switch.

BUG=b:184593945
BRANCH=puff
TEST=build image and verify with evtest on puff:
/dev/input/event3:	mic_mute_switch
UI event_device_info receives the proper name.

Change-Id: I09c52dc3df63e266c73741b102a22f8a2b896791
Signed-off-by: Ben Zhang <benzh@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20 20:40:47 +00:00