The EC doesn't support these commands so sending them is
not working. We have had a default policy of wake on USB
for a long time now and this runtime config isn't really
needed any longer.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655
Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298233
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11652
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add common code for filling out the NVS fields that are used by
the ACPI _SWS methods. The SOC must provide a function to fill
out the wake source data since the specific data inputs vary by
platform.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I4f3511adcc89a9be5d97a7442055c227a38c5f42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cee5fa176c16ca44712bce8f3c8045daa5f07339
Original-Change-Id: I16f446ef67777acb57223a84d38062be9f43fcb9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298167
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11646
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There's no need to maintain two lists of dependencies that need to be
changed every. single. time.
Change-Id: I26bb8c884e98afe74fd9df11464bcf88e130cd92
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11674
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It was added to an unused variable.
Change-Id: I869ffdda7e04b5c615931473c760d66b803fb98b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11673
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If we use a linux payload/any payload that wants to manage virtual
memory, and the payload is a supervisor (thus requiring virtual
addressing before being started), we need to make sure that the page
table is mapped into the virtual address space. Move the start address
of the tables so the payload can manage virtual memory.
Change-Id: I1d99e46f38a38a163fb1c7c517b1abca80cde0dc
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11621
Tested-by: build bot (Jenkins)
Existing memlayout code placed sections in overlapping areas, and would
overwrite the payload if it was large enough. Update memlayout.ld in
src/mainboard/emulation/spike-riscv to represent the spike emulator, and
add sbi interface which now has room into src/arch/riscv/bootblock.S.
Add utility code to qemu-riscv, but emulator itself has yet to be
updated to new ISA and as such should not be used.
Update Makefile to include all the files necessary for sbi interface.
Clean up unused include in src/arch/riscv/include/atomic.h and
whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld
Fixed whitespace issues in spike_util.c
Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11370
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Kunimitsu has an ambient light sensor connected to the EC which
is presented to the OS as a standard ACPI0008 device.
BUG=chrome-os-partner:43493
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I7998c19e5514eda781cc20888cdb0732f81389ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a67e5ddfccea0776841fabe04be55c1854bf31f2
Original-Change-Id: I381dc9c5777370df2ea4c41c9e153b3277082718
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298252
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Glados has an ambient light sensor connected to the EC which
is presented to the OS as a standard ACPI0008 device.
BUG=chrome-os-partner:43493
BRANCH=none
TEST=test ALS functionality on glados P2 board
Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054
Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298251
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11644
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch will reset Deep S3 flag, hence S3 will work.
BUG=chrome-os-partner:40635
BRANCH=None
TEST=Build and Boot Kunimitsu and verify S3 is working.
Change-Id: Iad87b7a8f7bf560861a270a8c19153cfc3850bc4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbfaa29041be49e4c39d19cb94f01ad10d12c7d5
Original-Change-Id: I5ae1738c5de1bee1ad9a45ebde074a6a378492af
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297903
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This switches the final 4 Intel platforms that use ME firmware from
using code specific to the platform to the common IFD Kconfig and
Makefile.
braswell, broadwell, bd82x6x (cougar point & panther point) and ibexpeak
Change-Id: Id3bec6dbe2e1a8a90f51d9378150dbb44258b596
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10876
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The locate command was previously being used for x86 romstage
linking as well as alignment handling of files. The add command
already supports alignment so there's no more users of the
locate command. Remove the command as well as the '-T' (top-aligned)
option.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. Noted microcode being directly added.
Change-Id: I3b6647bd4cac04a113ab3592f345281fbcd681af
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11671
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now that cbfstool supports XIP for romstage utilize it.
This removes the double link steps with the cbfstool
locate and add-stage sandwich.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted on glados.
Change-Id: I1ec555f523a94dd4b15fe8186cbe530520c622c0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11670
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of going through the locate then add-stage
dance while linking romstage twice allow for adding romstage
with --xip flags to perform the relocation while adding it
into CBFS. The -P (page-size) and -a (alignment) parameters
were added as well so one could specify the necessary
parameters for x86 romstage.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted on glados.
Change-Id: I585619886f257e35f00961a1574009a51c28ff2b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11669
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The cbfs_locate_entry() function had a hack in there which
assumed a struct cbfs_stage data was being added in addition
to the struct cbfs_file and name. Move that logic out to the
callers while still maintaining the logic for consistency.
The only impacted commands cbfs_add and cbfs_locate, but
those are using the default 'always adding struct cbfs_stage'
in addition to cbfs_file + name. Eventually those should be
removed when cbfs_locate is removed as cbfs_add has no smarts
related to the cbfs file type provided.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi.
Change-Id: I2771116ea1ff439ea53b8886e1f33e0e637a79d4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11668
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to allow cbfstool to add XIP romstage on x86 without
doing the 'cbfstool locate', relink, then 'cbfstool add' dance
expose the core logic and of rmodule including proving an optional
filter. The filter will be used for ignoring relocations to the
.car.global region.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi.
Change-Id: I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11598
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The core logic of the rmodule parser is ideal for
processing romstage ELF files for XIP. To that
end start the work of exposing the logic from
rmodule so cbfstool can take advantage of it.
The properties that both need require:
- Single program segment
- Relocation information
- Filter relocation processing
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi.
Change-Id: I176d0ae0ae1933cdf6adac67d393ba676198861a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11595
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There's no need to whine about missing files, so test for them first.
Change-Id: I906fd04a315de70340ce76d7c38eaaf88cc6580a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11642
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We build the coreboot utilities in a separate step as a minor
optimization. When logging in junit format (for jenkins), we want to
have a report on those as well (instead of an xml error).
Change-Id: Ibcd3b02bce9a314c30b5f7414e9e4cf0149ffd6a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11641
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Variable expansion made abuild create board..foo/bar, which are annoying
on jenkins' web UI because it doesn't cope properly with the empty
namespace between the dots. make it create board.foo/bar or
board.$class.foo/bar.
Change-Id: Ifa79cbfd1f263e11a458b3cc320baeed6a3fbc98
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11640
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This is required the BLOB change Icb7a4f07
"AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)"
This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the
boards can boot to Windows 8.1. PCIe slots, USB and NIC work.
Change-Id: Ibe141c16f8f9eac2adc5d5f45a1f354fb2a7f33c
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11148
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This is required the BLOB change I67817dc59
AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1).
This is tested on Olive Hill Plus. The board can boot to Windows 7.
PCIe slot, USB and NIC work.
Change-Id: I605df26b61bdffabd74846206ad0b7bf677ebed1
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11225
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Trap handling code was bugged in that it loaded in the wrong stack
pointer, overwriting the space the processor uses to talk to its host
for doing device requests. Fix this issue, as well as add support for
handling misaligned loads the same way we handle misaligned stores.
Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11620
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Recently qemu stopped doing a basic lapic setup and expects the
firmware to handle this properly (like on real hardware). So
let's do that so coreboot works properly on qemu 2.4+.
Here is the qemu commit message for the change:
<quote>
commit b8eb5512fd8a115f164edbbe897cdf8884920ccb
Author: Nadav Amit <namit@cs.technion.ac.il>
Date: Mon Apr 13 02:32:08 2015 +0300
target-i386: disable LINT0 after reset
Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone
and therefore this hack is no longer needed. Since it violates the
specifications, it is removed.
Signed-off-by: Nadav Amit <namit@cs.technion.ac.il>
Message-Id: <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
</quote>
Change-Id: I022f3742475d3f3477fc838b1e2bce69287b6b8e
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/11611
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We had two mappings of filetype IDs to strings. We shouldn't.
Change-Id: I08e478b92f3316139f14294e50ede657c7d5fb01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11626
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change was sitting in my git index, and I
failed to push it in the original patch.
Change-Id: If6f49c3c2b7908f93a99c23a80536ad5937959c7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11622
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Revive ffs() in a more fancy way (that is more likely to be accepted).
We dropped it in
7a8a4ab lib: Unify log2() and related functions
but there is at least one user: flashrom.
Change-Id: I4e3fc15816b778e640bceea0d89cd9624d271c2e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11591
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current endian API support in coreboot doesn't follow
any known API that can be shared in userland as well as coreboot
proper. To that end provide big and little endian helper functions
that can be used in code that can be shared within coreboot proper
and userland tools.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi
Change-Id: I737facab0c849cb4b95756eefbf3ffd69e558b32
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11618
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
FSP has some unique attributes which makes integration
cumbersome:
1. FSP header files do not include the types they need. Like
EDKII development it's expected types are provided by the
build system. Therefore, one needs to include the proper
files to avoid compilation issues.
2. An implementation of FSP for a chipset may use different
versions of the UEFI PI spec implementation. EDKII is a
proxy for all of UEFI specifications. In order to provide
flexibility one needs to binding a set of types and
structures from an UEFI PI implementation.
3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h
file which defines it's own types. Commonality between
FSP chipset implementations are only named typedef
structs. The fields within are not consistent. And
because of FSP's insistence on typedefs it makes it
near impossible to forward declare structs.
The above 3 means one needs to include the correct UEFI
type bindings when working with FSP. The current
implementation had the SoC picking include paths in the
edk2 directory and using a bare <uefi_types.h> include.
Also, with the prior fsp_util.h implementation the SoC's
FSP FspUpdVpd.h header file was required since for providing
all the types at once (Generic FSP 1.1 and SoC types).
The binding has been changed in the following manner:
1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1
selects. No other bindings are currently available,
but this provides the policy.
2. Based on CONFIG_UEFI_2_4_BINDING the proper include
paths are added to the CPPFLAGS_common.
3. SoC Makefile.inc does not bind UEFI types nor does
it adjust CPPFLAGS_common in any way.
4. Provide a include/fsp directory under fsp1_1 and
expose src/drivers/intel/fsp1_1/include in the
include path. This split can allow a version 2,
for example, FSP to provide its own include files.
Yes, that means there needs to be consistency in
APIs, however that's not this patch.
5. Provide a way for code to differentiate the FSP spec
types (fsp/api.h) from the chipset FSP types
(fsp/soc_binding.h). This allows for code re-use that
doesn't need the chipset types to be defined such as
the FSP relocation code.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted on glados.
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Change-Id: I894165942cfe36936e186af5221efa810be8bb29
Reviewed-on: http://review.coreboot.org/11606
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
RISCV requires the bios/bootloader to set up an interface by which it
can get information about memory, talk to host devices, etc. Put
implementation for spike in
src/mainboard/emulation/spike-riscv/spike_util.c, and
src/arch/riscv/trap_handler.c
Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11368
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Execution in supervisor level code in RISCV requires early setup of
virtual memory. Add initialization calls in
src/arch/riscv/virtual_memory.c to implement the required page table
setup, and helper functions to use when jumping to the payload correctly
in riscv.
Change-Id: I46e080e0ee8dc13277d567dcd4bf0f61a4507b76
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11369
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
... the configuration is handled further below in the file by virtue of
select DRIVERS_UART_8250MEM
Change-Id: Ie5481d23cd3ac3561958fd100bd05c0e4b03ce00
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Move some remaining ACPI init code to the SOC instead of being
done in each mainboard:
- acpi_create_gnvs is now a local function
- add a weak acpi_mainboard_gnvs() that can be used for mainboards
to override or set additional NVS
- add acpi_fill_madt() function for skylake
- remove acpi_create_serialio_ssdt() function as it is unused
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c717bb418a0cb6002582572632e42b44b473f718
Original-Change-Id: I0910ac8ef25de265ae1fde16b68f6cbacedb4462
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297800
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11581
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the acpi_tables.c functions so these functions can move to
SOC init code. The file itself is included by x86/arch code and
must exist for the build to succeed.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93ae87f2429af5cb9d497f8b5ef8b8dffe370df4
Original-Change-Id: Ifc2f64dc1693e7bd3f5a43144d84ff033b2cfe8b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297759
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11580
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the acpi_tables.c functions so these functions can move to
SOC init code. The file itself is included by x86/arch code and
must exist for the build to succeed.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I18e6a0be5eac053598b613b30b622c4963417919
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: af04eb112adf58578c8d2c9d3d182d4c2024abb2
Original-Change-Id: Ibe026d493c25d771357ea39e4b956629fbb799ac
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297758
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11579
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove thermal.h as it is not used by this board.
Remove functions from acpi_tables.c so they can move to SOC.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-sklrvp coreboot (does not compile due to GPIO changes)
Change-Id: I934fcc451a722f853034c0970074ee3259cc704f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e3b5c0ed8295091d3d5761b8456f3c13c6bd8bc
Original-Change-Id: If855f598e895e38c58657af17130158b2f73de81
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297757
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11578
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Read and print the board ID if it is enabled in the mainboard.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I9d50089242b3a2f461dff2b1039adc8f0347179e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f245854b30c40eda38453c1b0ae5d3b8b18c010f
Original-Change-Id: Ifbd7c2666820ea146dc44fbc42bfe201cb227ff6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297756
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11577
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clean up the intel/kunimitsu mainboard code to match the code
and cleanups in glados. Many of these are trivial changes that
do not impact things in a meaningful way but will make it easier
to diff the code and keep the mainboards in sync.
- use relative path for mainboard includes to make porting easier
- fix trivial style issues to match glados so diffs are clean
- pull GPIO configuration into gpio.h and use from there
- remove thermal.h as it is not used on this board
- make info message BIOS_INFO instead of BIOS_ERR
- add support for SPD manufacturer and part number in SMBIOS
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be
Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297752
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11576
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Select the EC PD and software sync kconfig options so they are
supported by the mainboard and call the EC early init function
to reboot into RO in recovery mode.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I48316df99b796c568c2481c72588b41f7147bec0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7507470f82848062bc98da809d3c5fe1ca31998
Original-Change-Id: I822aac9c24718f226819e5d3fcc82a4024b7c5a7
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297751
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Select the BOARD_ID_AUTO kconfig option to have the coreboot
tables populated with the board ID and print it early in
romstage as well. Also clean up the code for it.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I90bd85ef14543717287cbeaaab77e6c54b94df97
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1fed7de4a0650a497a240b091fd2eb99d59e1433
Original-Change-Id: I82e9d17ab618b1aae1fd874d9247b7d52b42334d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297750
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11574
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for reading board id and populating it in the
coreboot tables so it is exposed to payloads.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=boot on glados and look for reported board ID
Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004
Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297746
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Add ACPI code for DPTF support with placeholder thresholds
- Do not have custom PDL for mainboard
- Do not have enable charger control for DPTF as there is
already a complicated charge profile in the EC. We may still
want to enable this but it would need to be tuned to work
well with the EC profile.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a
Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297745
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11569
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- romstage.c is using gpio_configure_pads so it should really
include soc/gpio.h instead of relying on it to come from "gpio.h"
- consistent formatting of array initializers in pei_data.c
- remove pei_data->ec_present flag as this is unused in skylake
- fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR
- clean up acpi_slp_type usage in ec.c, remove unnecessary post
codes, and cleaner console output message.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b
Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297744
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11568
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The constants defined in thermal.h are never used since there
is no defined thermal zone. Remove it to result in less code
to worry about in board ports.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10
Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11567
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To make it easier to port glados to a new board name change
the include headers to use relative path name instead of
including the mainboard name.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90
Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297742
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11566
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This will help development activity. Default GPIO print settings is
disable, need to set gpio_debug = 1 to get GPIO MMIO dump.
BUG=None
BRANCH=None
TEST=build coreboot and boot on Kunimitsu.
Change-Id: I70c0a7bee1593cbc8e9fe1599f45bb50e3fc0f42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19102612ea40184307ecb0ce8b165b5b989f6911
Original-Change-Id: I4ea6349866c108382de9787bb9ed09fc78d9c770
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/296280
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11552
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a parameter to find_fsp which is the image base address. Adjust the
fake stack in cache_as_ram.inc to pass in the read-only FSP image base
address. In fsp_notify, pass in the read-only FSP image base address
when the FSP header pointer is NULL. In find_fsp, validate the FSP
binary image starting from the specified image base address.
BRANCH=none
BUG=None
TEST=Build and run on Skylake
Change-Id: Iac43c8aac8491390479af551765b514ca919928a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95
Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295593
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11545
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Wished I hadn't seen that. Git saw the conflict (file was gone), both
committer and reviewer thought it would be a good idea to re-add it as
dead code (see 558e9b5: libpayload: Add minimal support for PL011 UART).
Change-Id: Ifea8113fbc59e0463eaedb86b976f54ec11113a9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Duncan Laurie