Commit graph

7 commits

Author SHA1 Message Date
Arthur Heymans
aaced4a932 cpu/intel/common: Use a common acpi/cpu.asl file
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
2018-11-30 22:02:35 +00:00
Elyes HAOUAS
6d19a20f5f mb: Set coreboot as DSDT's manufacturer model ID
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".

Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
2018-11-23 11:00:40 +00:00
Elyes HAOUAS
0cca6e24b7 ACPI: Fix DSDT's revision field
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.

Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21 12:12:04 +00:00
David Wu
aceaa71531 mb/google/fizz: Provide baseboard and variant concepts
In order to be able to share code across different fizz variants,
provide the concept of baseboard and variants. New directory layout:

variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/fizz - code
variants/fizz/include/variant - headers

New boards would then add themselves under their board name within
"variants" directory.

This is purely an organizational change.

BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
CQ-DEPEND=CL:1273514

Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19 09:23:23 +00:00
Furquan Shaikh
d7b88dcbcd mb/google/x86-boards: Get rid of power button device in coreboot
As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button

Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.

On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.

Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.

This change gets rid of the generic hardware power button from all
google mainboards and relies completely on the fixed hardware power
button.

BUG=b:110913245
TEST=Verified that fixed hardware power button still works correctly
on nautilus.

Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-25 18:52:40 +00:00
Emil Lundmark
2ad7ea07b8 mb/google/fizz: Add USB port info
This adds all USB ports to the device tree. Additionally, it adds _PS0
and _PS3 ACPI methods for the visible USB A ports, which makes it
possible to control the port power (VBUS) of each port individually.

Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://review.coreboot.org/26472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-06-01 08:16:00 +00:00
Shelley Chen
243dc3913d google/fizz: Add new board
Creating google/fizz directory based on poppy (using kabylake and FSP
2.0).  Only making name changes and Copyright year changes.  Many
poppy-specific configs left in and will be updated in follup CLs.

BUG=b:35775024
BRANCH=None
TEST=Compile fizz board

Change-Id: Icab3639a53fef65e904e797028916fda879fff7c
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/18796
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-23 19:58:24 +01:00