Commit Graph

37698 Commits

Author SHA1 Message Date
Josie Nordrum 65d0ef7cbd mb/google/zork: Revert temp acpi backlight fix
Remove code to turn on backlight during ACPI mode because backlight has
been properly enabled in ACPI.

BUG=b:158087989
BRANCH=Zork
TEST=tested backlight during reboot and suspend

Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I3bf06042aa19e4559127d611d401f0ba0516b3a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28 17:18:15 +00:00
Josie Nordrum 0310fe7bdc mb/google/zork: Generate acpi methods in mainboard.c
Generate acpi methods which enable and disable backlight during _INI,
_WAK, and _PTS.

BUG=b:158087989
BRANCH=Zork
TEST=check backlight during reboot and suspend

Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I2f3434dc92de1f697693ff69ca15bd76647b89a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46671
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28 17:18:00 +00:00
Josie Nordrum da4d9da51a soc/amd/picasso/acpi: Include platform.asl
Include platform.asl to link acpi methods for _INI, _WAK, and _PTS to
correctly enable backlight in OS for zork.

BUG=b:158087989
BRANCH=Zork
TEST=check backlight during reboot and suspend

Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I702f807a5907d85d083295cf339ba9d31b246627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28 17:17:38 +00:00
Josie Nordrum 77f4b7fe0c soc/amd/common/acpi: Create platform.asl to define acpi transitions
Define device _WAK, _PTS, and _INI acpi methods with callbacks into
mainboard methods if provided.

BUG=b:158087989
BRANCH=Zork
TEST=tested backlight during reboot and suspend

Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I8020173a15db1d310459d5c1de3600949b173b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46669
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28 17:17:22 +00:00
Arthur Heymans 3603960d4d sec/intel/txt/Kconfig: Remove the menu for including ACMs
This is consistent with how other binaries (e.g. FSP) are added via
Kconfig. This also makes it more visible that things need to be
configured.

Change-Id: I399de6270cc4c0ab3b8c8a9543aec0d68d3cfc03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28 12:55:43 +00:00
Arthur Heymans ccb1119738 sec/intel/txt/Makefile.inc: Include ACMs using Kconfig variables
The Kconfig variables are used in the C code for cbfs file names but
not in the Makefiles adding them.

Change-Id: Ie35508d54ae91292f06de9827f0fb543ad81734d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28 12:55:29 +00:00
Tim Wawrzynczak 6ad856825a drivers/mrc_cache: Fix size comparison in mrc_cache update
`mrc_cache_needs_update` is comparing the "new size" of the MRC data
(minus metadata size) to the size including the metadata, which causes
the driver to think the data has changed, and so it will rewrite the
MRC cache on every boot. This patch removes the metadata size from
the comparison.

BUG=b:171513942
BRANCH=volteer
TEST=1) Memory training data gets written the on a boot where the data
was wiped out.
2) Memory training data does not get written back on every subsequent
boot.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7280276f71fdaa492c327b2b7ade8e53e7c59f51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-28 10:43:41 +00:00
Seunghwan Kim 71b546773d mb/google/nightfury: Set internal pull-down for GPP_D19
Add internal pull-down for GPP_D19 to improve DMIC noise issue on
nightfury.

BUG=b:171669255
BRANCH=firmware-hatch-12672.B
TEST=Built and checked GPP_D19 voltage after booting

Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-28 10:43:25 +00:00
Maxim Polyakov e828554ee0 mb/ocp/tiogapass/acpi: Exclude uncore.asl from _SB scope
The corresponding devices and objects are already included in the
System Bus ACPI scope inside uncore.asl. There is no need to do this
again in the DSDT of the motherboard.

Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28 10:10:14 +00:00
Morgan Jang bdd863689d src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7
TEST=Execute "dmidecode -t 7" to check if cache error correction type
and cache sram type is correct for each cache level

Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28 10:09:32 +00:00
Morgan Jang 160cb331fc soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADT
Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button
is present on Cooperlake platform.

Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28 10:09:14 +00:00
Jingle Hsu 83a2a007c7 mb/ocp/deltalake: Rename motherboard_fill_fadt()
Rename motherboard_fill_fadt() to the common override
mainboard_fill_fadt() function to override FADT.

Tested=On OCP Delta Lake, verify FADT PM Profile is set to
Enterprise Server.

Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: Ie9ea7cc6e712d0aca57bbeac1a4154921d123be4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28 02:33:38 +00:00
CK Hu bd0a222ab4 mb/google/asurada: Pass reset gpio parameter to BL31
To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I2ae7684a61af76693605cc0bcf8d20c8992c7bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46388
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28 02:01:10 +00:00
Wenbin Mei fc38e88341 mb/google/asurada: Configure pinctrl for SD and MMC
The pins for SD and MMC must be configured properly
so we can access them in payloads.

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: Ie6bdffb987d5acf286645550f1c53f294f71c38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-28 02:00:52 +00:00
Andrey Pronin 441c63d5f0 security/vboot: fix policy digest for nvmem spaces
This CL fixes the policy digest that restricts deleting the nvmem spaces
to specific PCR0 states.

BRANCH=none
BUG=b:140958855
TEST=verified that nvmem spaces created with this digest can be deleted
     in the intended states, and cannot be deleted in other states
     (test details for ChromeOS - in BUG comments).

Change-Id: I3cb7d644fdebda71cec3ae36de1dc76387e61ea7
Signed-off-by: Andrey Pronin <apronin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46772
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28 01:29:37 +00:00
Kevin Chiu 5b511f98b5 mb/google/octopus/var/garg: Disable XHCI LFPS power management by sku
LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.

If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.

BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46701
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27 16:35:24 +00:00
Kevin Chiu fd3dde3e33 mb/google/octopus/var/garg: fix LTE power sequence in reboot state
invoke LTE power off function to meet LTE power sequence while DUT is
in reboot state.

BUG=b:167565015
BRANCH=octopus
TEST=build and verify on the DUT with LTE

Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46022
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27 16:35:22 +00:00
Felix Singer 05b883ed24 device: Rephrase bus master Kconfig option
Change-Id: I902915133035fb2adff7edd9c931d4b1d3e7dc40
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-27 15:35:42 +00:00
Martin Roth 93122a7e77 util/testing: Allow what-jenkins-does to skip lint testing
The linters touch every file under src and probably util.  This makes
it difficult to see what files have been accessed by the builder.

The JENKINS_SKIP_LINT_TESTS variable will only be set on the jenkins
build that looks for unused files.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I12fa31641c2a72c5e07be1c4958467f7165f21bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:10:56 +00:00
Martin Roth b043277866 util/testing: Update test-abuild output directories
This matches the what-jenkins-does target.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I20b455e0161dcebf2eb9022bd142bbec99937a19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:10:14 +00:00
Martin Roth 2aba15fce1 util/docker: Update atime mount point options for jenkins
- The ccache files don't need atime.
- Enable strict atime for the git repos.  This will help find unused
files.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I94bcc55ea5c5a74f3ad0292ca50b74874a0d920d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:09:50 +00:00
Martin Roth a266299490 util/docker: Update agent-root to node-root for jenkins
Jenkins has changed the name of the build directory, so it's not
currently building out of memory, it's writing to the SSD. This
changes the build back to tmpfs.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iefcf53757862feb2025aa5696f9f5dbce9dd70dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:09:06 +00:00
Martin Roth 7d520ff98f util/docker: Add tests to coreboot-sdk build process
This tests some of the basic targets that coreboot-sdk needs to be
able to run.

I was running most of these tests manually after creating the sdk
image, but adding it into the Dockerfile makes sure they get run.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d4a2ad82042733a7966edb8ccf927676618977c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:08:45 +00:00
Martin Roth ebeec5aed3 util/docker: Update coreboot-sdk consolidate coreboot build
Because docker saves a container for every run command, by breaking
the coreboot build into 3 commands, it greatly increased the size of
the docker containers needed.  When combined as one run command, the
coreboot repo that is downloaded, along with the coreboot test build
are deleted before the container is created.  Since those directories
are deleted in a later run command, they don't even make it into the
final container, and just force coreboot-sdk users to download extra
data for no reason.

While splitting the build may help with debugging failures when
creating the docker container, that debugging can be done locally by
splitting up a working copy.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia28ee4e22c0a76dc45343755c45678795308adca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:07:20 +00:00
Martin Roth b86d2b0935 util/docker: Update coreboot-sdk to set python2 as default
Even though both python2 and python3 are now installed to the SDK, the
default python program is not.  This sets the default to python2.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4220c316df86cb2481143a79fadb70fc734e6879
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:06:17 +00:00
Martin Roth bd8e6dd2ca util/docker: Update coreboot-sdk with additional tools
- cscope: Run cscope targets
- ctags: Run ctags targets
- pbzip2: Allow compression on all cpu cores

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I31ca45fcc5880f2b0346ca3f7d36a71ae18da979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:06:00 +00:00
Angel Pons 99af210456 mb/google/auron: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical.

Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27 10:05:35 +00:00
Martin Roth ce19f4f8ad util/testing: Remove test for util/broadcom/secimage
util/broadcom/secimage was removed in commit aea00f496b, so don't
try to test it anymore.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibcc018a6b8ed4ecd407f2dc374cec62900920a92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:05:15 +00:00
Ren Kuo 12b376c87f mb/google/dedede/var/magolor: Configure I2C high and low time
Configure the I2C bus high and low time for all enabled I2C buses.

BUG=b:168783630
TEST=Measured the I2C bus frequency reduce to 387 KHz.

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46613
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27 06:13:43 +00:00
Jonathan Zhang 8f594b7319 cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN
Integer handling issues:
Potentially overflowing expression "1 << size_msb" with type "int"
(32 bits, signed) is evaluated using 32-bit arithmetic, and then
used in a context that expects an expression of type "uint64_t"
(64 bits, unsigned).

Fixes: CID 1435825 and 1435826

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46711
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27 06:13:32 +00:00
Kevin Chiu bd21476f99 mb/google/kukui: change Jacuzzi followers LCMID to fixed value
The LCM ID is not really used on Jacuzzi followers and the reference
design expects ADC to return 0. However, there were hardware design
issues so the returned value became unexpected numbers.

 - Juniper and Kappa returns 1.
 - Burnet and Esche returns 1 on normal boot, and 0 on recovery boot.
 - Cerise and Stern usually returns 0, and sometimes 1.

To fix that, we are changing LCM ID to fixed value for Jacuzzi followers.

BUG=b:170916885,b:171365301
BRANCH=kukui
TEST=1. emerge-jacuzzi coreboot
     2. check burnet/esche skuid correctly

Change-Id: I3b43b9153315ec65e9168c4e84ea844dff14d446
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-27 04:15:46 +00:00
Nick Chen 955ce24afc mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb
2. Update tcc offset to 5
3. Follow thermal validation and update PL2 max_power to 51

BUG=b:167931578, b:170357248

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26 15:24:04 +00:00
Jakub Czapiga 43439f6d49 lib/edid: Add missing name descriptor presence flag
EDID parser internal flag c->has_name_descriptor
was never set. It was causing decode_edid() function
to return NON_CONFORMANT instead of CONFORMANT even when
EDID frame was correct.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ifdc723b892a0885cfca08dab1a5ef961463da289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 13:28:41 +00:00
Julius Werner 11298542cd cbfstool: Don't build unneeded commonlib sources
These sources are built but not used by cbfstool. The only .c file in
commonlib/ it really needs is fsp_relocate.c. Get rid of the others.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6ebbb4161874f6279b6dbaffe7c3144226a6f9b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46253
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:59:53 +00:00
Julius Werner 4a30d42c4a vboot: Disable vboot functions in SMM
SMM does not have access to CBMEM and therefore cannot access any
persistent state like the vboot context. This makes it impossible to
query vboot state like the developer mode switch or the currently active
RW CBFS. However some code (namely the PC80 option table) does CBFS
accesses in SMM. This is currently worked around by directly using
cbfs_locate_file_in_region() with the COREBOOT region. By disabling
vboot functions explicitly in SMM, we can get rid of that and use normal
CBFS APIs in this code.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4b1baa73681fc138771ad8384d12c0a04b605377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-10-26 06:58:54 +00:00
Nico Huber d9e543a5f9 libpayload/keyboard: Use `bool` as return type
Use `bool` whenever `0` was used to indicate an error. The mixing of
different types for return values was mildly confusing and potentially
dangerous with the i8042 API close by that uses `0` for success.

Change-Id: I876bb5076c4921f36e3438f359be8ac4c09248cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:47 +00:00
Nico Huber f56d65266c libpayload/curses: Use <stdbool.h>
Change-Id: I35ef7c55fc6bcfb9c51a711a8e238f0970fd4ad4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:21 +00:00
Nico Huber bfa46e25e0 libpayload: Add <stdbool.h>
Change-Id: I972c78c5da4136bc61e78fcbb52d7d162cc1b698
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:06 +00:00
Stefan Reinauer 3a7825983c ectool: Don't ignore fgets return code
Change-Id: I12dc449e06dee31b4b0811ab23c6e8635cf31512
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:56 +00:00
Stefan Reinauer 9d50efe19d ectool: Add newline to warning message
Cosmetic fix:

$ sudo ./ectool -p
Cannot get EC ports from /proc/ioports, fallback to default.EC RAM:

Change-Id: Icc2b5bbbbfe7685e4fe512af029ce00b33a26daa
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:49 +00:00
Stefan Reinauer f3b1a53858 inteltool: Only use real graphics devices
Right now IGD is hard coded to 0:2.0 and if that
device is there, it is blindly used, even if it is
not a graphics device. Look at the PCI class to make
sure we're not using the wrong device.

Change-Id: Ia7f52071bd202e2960faba0f46e4fa5e14ad65f8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:36 +00:00
Stefan Reinauer 91893ee785 inteltool: initial Hewitt Lake support
Change-Id: Ifed43d058c70f75d88e9f4b2b07527782ebcbac5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:26 +00:00
Elyes HAOUAS 28b68ae4fe soc/amd/picasso/acpi: Convert to ASL 2.0 syntax
Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26 06:56:00 +00:00
Jakub Czapiga 466a378b9a tests: Add lib/imd-test test case
Implement unit tests for src/lib/imd.c module.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Signed-off-by: Anna Karas <aka@semihalf.com>
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I3902f8638669440144064ce0e3756918338f4068
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46457
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:55:46 +00:00
Jakub Czapiga 05fa5b2450 tests: Add test region and symbol macros to <tests/test.h>
Some modules require and operate on memory regions and symbols.
This macros systematize how they are defined in testing code.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I314028c201732416bb3d5446a4c8585e055073e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-26 06:55:40 +00:00
Karthikeyan Ramasubramanian 468c46df25 Revert "soc/intel/jasperlake: Allow mainboard to override chip configuration"
This reverts commit 5acea15d63. This
change got accidentally merged. There is no need for mainboard to
override chip configuration.

BUG=None
TEST=Build and boot Drawlat to OS.

Change-Id: I166ba7e5ee50a6329032eae8e17b9a554b094e2e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:55:18 +00:00
Karthikeyan Ramasubramanian b11b731e80 Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration"
This reverts commit 214c719eed.
CB:45857 overrides the GPIO PM configuration if Cr50 does not support
long interrupt pulse width. More recent Cr50 Firmware versions support
long pulse width and hence the GPIO PM can take the default
configuration.

BUG=None
TEST=Build and boot Drawlat to OS. Ensured that 200 iterations of
suspend/resume sequence, warm and cold reboot cycles each are
successful.

Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
2020-10-26 06:55:09 +00:00
Tim Wawrzynczak 7c80de6328 ec/google/chromeec: Update ec_commands.h
This change copies ec_commands.h directly from the Chromium OS EC repo
at SHA edd8b73e8, with the exception of changing the copyright header
to SPDX format.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I97bdb12dd561bd95746cc2761397aa7406326e12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45937
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:54:54 +00:00
Tim Wawrzynczak ba4a4909a8 sconfig: Split up sconfig-generated static.h
Currently sconfig generates a `static.h` to accompany
`static.c`. However, some payloads may decide they would like to consume
the FW_CONFIG macros as well. The current state of `static.h` makes this
impossible (relying on `device/device.h`).

This patch splits up `static.h` into 3 files: `static.h,
`static_devices.h`, and `static_fw_config.h`. `static.h` simply includes
the other two `.h` files to ensure no changes are needed to other
code. `static_devices.h` contains the extern'd definitions of the device
names recently introduced to sconfig.  `static_fw_config.h` contains the
FW_CONFIG_FIELD_* macros only, which makes it easily consumable by a
payload which wishes to use FW_CONFIG.

Also refactor the generation of all these output files, as the code was
getting messy.

Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-26 06:54:16 +00:00
Morgan Jang 8ae391d199 arch/x86/smbios: Populate SMBIOS type 7 with cache information
SMBIOS has a field to display the cache size, which is currently
set to UNKNOWN unconditionally, multiply the cache size of L1 and L2
by the number of cores.

TEST=Execute "dmidecode -t 7" to check if the cache information
is correct for Deltalake platform

Change-Id: Ieeb5d3346454ffb2291613dc2aa24b31d10c2e04
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:54:04 +00:00