For nissa, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.
BUG=b:234776154
TEST=Boot to OS on nirwen and yaviks UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.
Cq-Depend: chrome-internal:5102230
Change-Id: I68f963e17bc0dbf9db9adaaa3f96f06b8737523b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
BUG=b:253387689
Test:Boot to OS on craask and check SAR Proximity Sensor GPIO pin
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I2b2a2516890b68036e96d1a542e6a10a098cb6a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69790
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Move smbios_ec_revision to ocp folder so that all ocp boards
share the same function without implementing again.
TESTED=Execute "dmidecode -t 0" to check corresponding field.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Jonzhang Zhang <jonzhang@meta.com>
Change-Id: I898662b78d3dbab1861cee6f1b6e148297a5d11b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Following warnings occur when compiling with
`i386-elf-gcc (coreboot toolchain v2022-09-18_c8870b1334) 11.2.0`
drivers/serial/8250.c:75: [-Werror=unused-variable]
Move variable declaration inside the
`#if !CONFIG(LP_PL011_SERIAL_CONSOLE)` block
drivers/udc/dwc2.c:505: [-Werror=format=]
use `%zd` to match type `size_t`
Change-Id: Id285c24cba790f181fa203f3117e5df35bed27c4
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69764
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
With the addition of the clang tests, the jenkins builds are taking a
really long time to run the tests. This change allows the
"what-jenkins-does" build to be split into separate builds on jenkins.
Additionally, some jenkins builds like coverity don't need (or want)
to build clang or even the linters.
Update help with the variables.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0f8ac68c1bc8f8ff9be62d80db850355e742ee74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This tests building a single target with scanbuild so to make sure that
option hasn't been broken. Since it's a different type of build, it
hasn't previously been tested with what-jenkins-does.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8a74dac203f4d38c0cb30a0b64724e6f9095b9dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This gets rid of the duplicated directory and xml filename and uses the
--name argument to abuild instead, which also updates the test name in
the junit xml file.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ibe538da42280696190b0a7a0c63fd86a63e40214
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Previously, the testclass variable was only updated with the chromeos
or Kconfig option values, and the output directory and xml file names
were updated independently.
With the --name option, all of these can be set simultaneously. This
also prevents jenkins from seeing clang and gcc tests as the same
because the testclass variable wasn't updated.
If --name is not set, all behavior is as it was previously.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8f52779b92d213386a3eb371d1f30ee32ed48b85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69859
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having duplicate lines in the what-jenkins-does target and
the test-tools target, make test-tools from what-jenkins-does.
Now there's only one place to update when changing the call.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id62d6bb1e729892ec123ea970ca8a31e03a812d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It's hard to tell what is what with the short option names, so use the
long options here.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1371e098bba1077dedfaffa56287a28656197b40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69837
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having duplicate lines in the what-jenkins-does target and
the test-abuild target, make test-abuild from what-jenkins-does.
The test-abuild target had not been updated to use the ABUILD_OPTIONS
variable, so update it with the commands from what-jenkins-does.
Now there's only one place to update when changing the call.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4552193894c16301defb851eb3db4bdfbfa49803
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having duplicate lines in the what-jenkins-does target and
the test-lint target, make test-lint with the --junit argument from
what-jenkins-does.
Now there's only one place to update when changing the call.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f90df76126f453fbcd91f4c4af5d784ac2dbe88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having the what-jenkins-does target clean up before building,
have it call the test_cleanup target.
Clean the tegra targets.
Remove distclean from test_cleanup target - I don't think that's
expected, and people might be upset by having their .config deleted.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia9d585df05343365c89e49b1c01dba9ba865003f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
CBFS_MCACHE is currently experiencing overflow with CBFS verification
enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB.
This reduction along with the available free space in PSP shared buffer
(32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required
14 KiB.
BUG=b:259342909
TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS
mcache overflows.
FMAP: area COREBOOT found @ 80a000 (8347648 bytes)
VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported
CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes
CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640
VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled
Ensure that firmware_CbfsMcache FAFT test is successful.
Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If no boards are tested by abuild, an error is currently shown because
no boards failed, but no boards passed either. Account for this
possibility.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I097d3c728ca1acc652d5a1b7b49e57d01b0e513b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE is nowadays defined in
vboot/firmware/2lib/include/2constants.h, so update the comment.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7c9a5476ae06d4bac762da1729aff878b7d0965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.
For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
One register configuring multi-pin functions was outside of the Global
Configuration Registers space and skipped in the initial port patches.
Replicate the vendor configuration and set the Super I/O pin for PECI
functionality.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add pcie_find_dsn() to detect and match PCIe device serial
number. In addition, vendor ID is matched when provided.
Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add initial CEDT (CXL Early Discovery Table) support based on
CXL spec 2.0 section 9.14.1.
Add functions to create CEDT table (revision 1), and create CEDT
CXL Host Bridge Structure (CHBS) and CXL Fixed Memory Windows
Structure (CFMWS).
TESTED=Create CEDT table on Intel Archer City CRB, dumped the
CEDT table and examined the content.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The change being reverted [1] caused all the Kconfig dependency files
to be generated at the top level of coreboot's build directory.
This reverts that behavior and puts the dependencies back where we're
used to them being.
[1] 1b9e740a81
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic4b48831705c3206e7c2e09f01d072d1cde9c9c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69535
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a note about the default I2C speed of this being 400 kHz
despite the logic in rx6110sa.c sets the fallback (correctly) to
100 kHz.
This information originally comes from the fact the dw_i2c bus
controller default speed is 400 kHz. This is irrelevant to
the default speed of this device as it can be used with any
bus controller.
BUG=none
TEST=coreboot builds correctly (no functional changes).
Change-Id: Ic0ffe5667574c59e1c1df952b84b8a3680b53341
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69545
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit doesn't add any new format options, just makes selecting
existing format explicit.
Ticket: https://ticket.coreboot.org/issues/422
Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change enables the DisplayPort detection at preboot for Rex board.
BUG=b:247670186
TEST=Built image and validated DisplayPort feature at preboot on Rex.
Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67742
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
After DisplayPort is plugged into type-C port, its hpd signal
instantly presents and EC has mux_info for dp and hpd. This change
fixes the DP detection flow to avoid the 1 second delay while no DP
is connected. If DP is present, there will be requests towards PMC
through the sequence of connect, safe mode, dp and hpd mode.
BUG=b:247670186
TEST=Built image and validated the DisplayPort preboot feature on Rex.
Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Update definitions on glinda used by birman.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I03065011581489b5345c16e225edc341e1d7811c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update definitions to match morgana FSP.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic893526789c05a298965702114d4a814466a5742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all
references.
BUG=b:216485035,b:258126464
BRANCH=none
TEST=none
Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
BUG=b:235919755
Test=Check error message "Exposing GPIOs in Power Resource and _CRS"
not show in firmware log.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I21a47adde48555098d041b94d483cad308bdb717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Set `EnableTcoTimer=1` in order to keep FSP from
1) enabling ACPI Timer emulation in uCode.
2) disabling the PM ACPI Timer.
Both actions are now done in coreboot.
`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.
Port of commit 0e905801f8 ("soc/intel: transition full control over PM
Timer from FSP to coreboot").
NOTE: This will have a huge power impact when it's enabled. If TCO timer
is disabled, uCode ACPI timer emulation must be enabled, and WDAT table
must not be exposed to the OS.
BUG=none
TEST=Boot to OS on google/rex.
Excerpt from google/rex coreboot log:
[SPEW ] EnableTcoTimer = 1
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch deselects `USE_PM_ACPI_TIMER` kconfig to ensure that
ACPI PM timer remains disabled.
The PM timer (by PMC IP) consumes more power and blocks S0ix so the
timer is emulated by ucode to save power and unblock S0ix.
TEST=Able to boot Google, Rex and ensure PMC MMIO register 0x18fc
BIT 1 is set.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2a23b417ff7fb6328323380a7df46b4b397fc8eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69685
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The coreboot build system automatically adds a `config` file to CBFS
that lists the exact Kconfig configuration that this image was built
with. This is useful to reproduce a build after the fact or to check
whether support for a specific feature is enabled in the image.
However, the file is currently generated using the `savedefconfig`
command to Kconfig, which generates the minimal .config file that is
needed to produce the required config in a coreboot build. This is fine
for reproduction, but bad when you want to check if a certain config was
enabled, since many configs get enabled by default or pulled in through
another config's `select` statement and thus don't show up in the
defconfig.
This patch tries to fix that second use case by instead including the
full .config instead. In order to save some space, we can remove all
comments (e.g. `# CONFIG_XXX is not set`) from the file, which still
makes it easy to test for a specific config (if it's in the file you can
extract the right value, if not you can assume it was set to `n`). We
can also LZMA compress it since this file is never read by firmware
itself and only intended for later re-extraction via cbfstool, which
always has LZMA support included.
On a sample Trogdor device the existing (uncompressed) `config` file
takes up 519 bytes in CBFS, whereas the new (compressed) file after this
patch will take up 1832 bytes -- still a small amount that should
hopefully not break the bank for anyone.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Elyes Haouas