In the LOG_FAST macro, the comparison was incorrectly made with 'level'
value. Correct is the comparison with 'speed'.
With the wrong comparison you cannot set a lower level for console log,
the highest level is always output.
TEST:
- Boot mc_ehl2 with console log level 5 and check output
Change-Id: Ib5b4537ae2cbf01c51c3568d312b5242c4bee7bb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Clang does not seem to work with 'fall through' in comments.
Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
I think this doesn't do anything on most architectures, but it should
still be there just in case. Found by Coverity.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I845a784d90f65610fd1e0d751ea13e9af5b970fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Post codes don't signify an emergency error, so they shouldn't be
classified as BIOS_EMERG. Now that loglevels are more visible, this
misclassification looks pretty glaring. This patch changes them to
BIOS_INFO which seems more appropriate for an informational code that is
expected to occur in the normal boot flow.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I85c8768232ae0cbf65669a7ee6abd538a3b2d5e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
A common use case when running coreboot on production systems is that
only the CBMEM console (the one with the least impact on boot speed) is
enabled. In this case, some of the code in the console subsystem has no
effect. Due to the way it's all genericized over multiple consoles and
tied together with function pointers, not all of this can be
compile-time eliminated automatically, so this patch adds a little
helper to facilitate that. This results in roughly 200 (compressed)
bytes of savings per stage on an arm64 system.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1d5b8bda80d02a13ee0b7835e0805c4319fd21d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In order to provide the same loglevel prefixes and highlighting that
were recently introduced for "interactive" consoles (e.g. UART) to
"stored" consoles (e.g. CBMEM) but minimize the amont of extra storage
space wasted on this info, this patch will write a 1-byte control
character marker indicating the loglevel to the start of every line
logged in those consoles. The `cbmem` utility will then interpret those
markers and translate them back into loglevel prefixes and escape
sequences as needed.
Since coreboot and userspace log readers aren't always in sync,
occasionally an older reader may come across these markers and not know
how to interpret them... but that should usually be fine, as the range
chosen contains non-printable ASCII characters that normally have no
effect on the terminal. At worst the outdated reader would display one
garbled character at the start of every line which isn't that bad.
(Older versions of the `cbmem` utility will translate non-printable
characters into `?` question marks.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I86073f48aaf1e0a58e97676fb80e2475ec418ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This patch adds ANSI escape sequences to highlight a log line based on
its loglevel to the output of "interactive" consoles that are meant to
be displayed on a terminal (e.g. UART). This should help make errors and
warnings stand out better among the usual spew of debug messages. For
users whose terminal or use case doesn't support these sequences for
some reason (or who simply don't like them), they can be disabled with a
Kconfig.
While ANSI escape sequences can be used to add color, minicom (the
presumably most common terminal emulator for UART endpoints?) doesn't
support color output unless explicitly enabled (via -c command line
flag), and other terminal emulators may have similar restrictions, so in
an effort to make this as widely useful by default as possible I have
chosen not to use color codes and implement this highlighting via
bolding, underlining and inverting alone (which seem to go through in
all cases). If desired, support for separate color highlighting could be
added via Kconfig later.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I868f4026918bc0e967c32e14bcf3ac05816415e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In an attempt to make loglevels more visible (and therefore useful,
hopefully), this patch adds a prefix indicating the log level to every
line sent to an "interactive" console (such as a UART). If the code
contains a `printk(BIOS_DEBUG, "This is a debug message!\n"), it will
now show up as
[DEBUG] This is a debug message!
on the UART output.
"Stored" consoles (such as in CBMEM) will get a similar but more
space-efficient feature in a later CL.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic83413475400821f8097ef1819a293ee8926bb0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This patch makes a slight change in the way CONSOLE_LOG_FAST and
CONSOLE_LOG_ALL are differentiated, by no longer passing a different
tx_byte() function pointer and instead using the `data` argument to
vtxprintf() to encode the difference. It also passes the message log
level through to the tx_byte() function this way, which will be needed
in the next patch.
Change-Id: I0bba134cd3e70c2032689abac83ff53d7cdf2d7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Chromebooks normally run with non-serial enabled firmware because
writing to the UART console is very slow. This unfortunately makes
debugging boot errors more difficult. We tend to rely on port 80s and/or
the vboot recovery code.
When CONSOLE_CBMEM_DUMP_TO_UART is selected it will dump the entire
cbmem console to the UART whenever `vboot_reboot()` is called. We don't
incur any boot time penalty in the happy path, but still retain the
ability to access the logs when an error occurs.
The previous implementation was using a hard coded UART index and
`get_uart_baudrate` was always returning 0 since `CONFIG_TTYS0_BAUD`
wasn't defined. This change makes it so the UART console properties are
available when CONSOLE_CBMEM_DUMP_TO_UART is set. This results in the
following .config diff:
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_TTYS0_BASE=0x3f8
+CONFIG_TTYS0_LCS=3
+CONFIG_CONSOLE_SERIAL_115200=y
+CONFIG_TTYS0_BAUD=115200
This functionality is especially helpful on Guybrush. PSP Verstage is
run on S0i3 resume. Today, if there is an error, the cbmem console is
lost since it lives in the PSP SRAM.
BUG=b:213828947, b:215599230
TEST=Build non-serial guybrush FW and verify no serial output happens in
happy path. Inject a vboot error and perform an S0i3 suspend/resume.
Verify CBMEM console gets dumped to the correct UART.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I997942204603362e51876a9ae25e493fe527437b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not
have the ability to log to the UART, so their console messages are
inaccessible until the boot processes gets into the payload or OS.
This makes it difficult to debug verstage.
This feature will dump the pre-bootblock CBMEM console immediately
after the bootblock console is initialized. I chose to do this in
console_init instead of bootblock_soc_init because I wanted to have the
pre-bootblock contents dumped before the coreboot bootblock starting
message is printed.
BUG=b:213828947
TEST=Boot guybrush with PSP verstage and verify verstage logs are dumped
to the UART.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I363c93ef3ee6c5c303a6a68f88a622e2aa62594c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61012
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Other drivers may need to know the coreboot log level hence,
export this function rather than marking it static.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I56349f22c71c9db757b2be8eeb2dbfe959f80397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We never call console_init from asm, so we don't need the asmlinkage.
This allows us to remove the arch/cpu.h include since we only needed it
for the asmlinkage #define.
BUG=b:179699789
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9a7895d4f5cba59f6b05915fa4d6c6fd6ab85773
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57568
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expand NO_EARLY_BOOTBLOCK_POSTCODES to all of the early assembly code in
bootblock.
BUG=b:191370340
TEST: Build with & without the option enabled
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idb4a96820d5c391fc17a0f0dcccd519d4881b78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
CB:55356 removed static inline declarations from get_log_level(). This
commit puts them back. It also changes the method of accessing static
symbols in tests/console/routing-test to source file inclusion like
in CB:46458 to avoid changing tested source file.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iaa5dcbccb327f819374967be51ef642b1fb25e7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55473
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
With this change, the type-unsafe {get,set}_option() API functions are
no longer used directly. The old API gets dropped in a follow-up.
Change-Id: Id3f3e172c850d50a7d2f348b1c3736969c73837d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52512
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like the option is generally not compatible with
garbage collections.
Nothing gets inlined, for example is_smp_boot() no longer
evaluates to constant false and thus the symbols from
secondary.S would need to be present for the build to pass
even if we set SMP=n.
Also the addresses of relocatable ramstage are currently
not normalised on the logs, so util/genprof would be unable
dress those.
Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a new CONFIG_OVERRIDE_UART_FOR_CONSOLE token to override the index
of uart port, platform use a get_uart_for_console routine to decide what
index value should be used for console.
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
We limited the configurability of the debug level to stages that have
a `.data` section. This is not really a requirement, because a `.bss`
section should suffice and we always have that now.
We want to make the debug level configurable early but also want to
avoid calling get_option() early, as an error therein could result
in no console output at all. Hence, we compromise and start using
get_option() from the second console init on.
TEST=Booted QEMU once with `debug_level=Debug` and once with
`debug_level=Notice`. On the second boot, most messages
vanished for all stages but the bootblock.
Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this
option with `EM100Pro`. Looks like it is not build-tested, however.
Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This adds support for line-buffered console output to System76 EC firmware.
Once the print command is received, the EC firmware multiplexes the output
to any enabled console on the EC. This can be a memory ringbuffer, a
parallel port (using the keyboard connector), or i2c (using the battery
connector). Once the entire buffer is sent, it sets the command register
to 0, indicating completion. For more information, please see:
https://github.com/system76/ec/blob/master/doc/debugging.md
Tested on system76/lemp9 with CONSOLE_SYSTEM76_EC enabled.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I861bf3e22f40dd6c3ec7ba1d73711b399358e332
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Exclude pieces of console code from the vboot if running before
bootlock. The PSP verstage code will re-implement some of
these in its own code.
BUG=b:123887623
TEST=Build with following patches
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41815
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The purpose of pci_early_bridge_init() is to temporarily configure
PCIe rootport (or PCI bridge) on bus 0 to configure PCI device BARs
on the secondary bus. Currently used and tested only with UART_OXPCIE.
Since those BARs do not reset on stage changes, it is not necessary
to redo those steps for verstage or postcar. Note that the option
does not really work with many of the later platforms where PCIe
pins/links/lanes are configured late in FSP-M or similar blob.
Change-Id: I148f44c76c61edcfd8ab1c8c531cd2e6ca343130
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Ib8a40e5633faf840e19a35bcdc8edc7e7cdd0ad9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Both IO port and cmos are currently arch/x86 only features.
Change-Id: I010af3f645c0be38dd856657874c36103aebbdc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38187
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make it consistent with the more used cmos_write().
Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38178
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For each boot_state, report the times spent interleaved
with other console output and remove the samples arrays.
The time spent to report the times to console is not
accounted for.
Change-Id: I0c847da98901c56b356b4a933d9ae865dada98b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Now that romcc is gone, move cmos_post_init() into post.c, and remove
some preprocessor workarounds.
Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
According to the POSIX standard, %p is supposed to print a pointer "as
if by %#x", meaning the "0x" prefix should automatically be prepended.
All other implementations out there (glibc, Linux, even libpayload) do
this, so we should make coreboot match. This patch changes vtxprintf()
accordingly and removes any explicit instances of "0x%p" from existing
format strings.
How to handle zero padding is less clear: the official POSIX definition
above technically says there should be no automatic zero padding, but in
practice most other implementations seem to do it and I assume most
programmers would prefer it. The way chosen here is to always zero-pad
to 32 bits, even on a 64-bit system. The rationale for this is that even
on 64-bit systems, coreboot always avoids using any memory above 4GB for
itself, so in practice all pointers should fit in that range and padding
everything to 64 bits would just hurt readability. Padding it this way
also helps pointers that do exceed 4GB (e.g. prints from MMU config on
some arm64 systems) stand out better from the others.
Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.
This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The code in cpu/x86/lapic/apic_timer.c for timer_monotonic_get()
is not SMP safe as LAPIC timers do not run as synchronised as TSCs.
The times reported for console for boot_states does not accumulate
from APs now. Also remove console time tracking from ENV_SMM.
Change-Id: I1ea2c1e7172f8ab3692b42dee3f669c5942d864a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37398
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The romcc bootblock will be deprecated soon and most platforms use
C_ENVIRONMENT_BOOTBLOCK already. This patch drops the
CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK
where needed.
Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Mario Scheithauer