Commit Graph

32090 Commits

Author SHA1 Message Date
Matt DeVillier 92b0e8dcae drivers/generic/cbfs-serial: Add driver to read serial from CBFS
Add a new driver to support reading a board serial number from
a text file in CBFS and injecting into the SMBIOS tables.
Allow driver to be selected at the .config level and not require
inclusion at the board level.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Ieae39f39ab36e5b1f240383b7cf47681d9a311af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26 10:49:03 +00:00
Marshall Dawson f9ad22d9f7 src/x86|cpu/intel: Hardcode FIT and ID
Revert two of the changes made in
  "arch|cpu/x86: Add Kconfig option for x86 reset vector"
  I6a814f7179ee4251aeeccb2555221616e944e03d

The Intel FIT pointer and the ID section should be offsets from the
top of flash, and aren't inherently tied to the reset vector or to
bootblock.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I2c9d5e2b2c4248c999d493a72d90cfddd92197cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26 10:48:17 +00:00
Marshall Dawson cca7486120 soc/amd/picasso: Configure APOB NV only with ACPI resume
The APOB NV region holds the save data for resuming.  Omit it if the
mainboard doesn't use HAVE_ACPI_RESUME.

The APOB information will also be board-specific so remove the
default values.

Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26 10:48:06 +00:00
Peichao Wang da6170a223 mb/google/hatch/akemi: Set touchpad data hold time more than
300ns

According to SI team and vendor request, need to tune I2C bus
0 data hold time more than 300ns

BUG=b:146163044
TEST=build firmware and measure I2C bus 0 data hold time

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I75e33419cbaef746487de6ee8628d07cf08adaa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37322
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26 10:47:29 +00:00
Angel Pons 58ececfb28 Doc/releases/checklist.md: Correct some inconsistencies
Use periods on every element of a list, and make `IRC` uppercase.
Also, correct a grammar mistake that slipped through.

Change-Id: Id05865719c7c845265416e89bfd9b02b6d22ca6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-12-26 10:47:13 +00:00
Matt DeVillier 66406d4754 mb/google/eve: select SYSTEM_TYPE_CONVERTIBLE
select SYSTEM_TYPE_CONVERTIBLE, which properly sets the
SMBIOS chassis type, and allows the OS driver to
recognize tablet mode capability

Change-Id: Ic61659e9fa6f7428afd1f018fb8cb25fe49e8747
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26 10:47:00 +00:00
Matt DeVillier 34f52dd0ad mb/google/kefka: Add missing SPD
Adapted from Chromium commit 9522225e
[Kefka: Add memory SPD info for Hynix H9CCNNN8GTALAR-NUD]

Add current available ram_id to support Hynix H9CCNNN8GTALAR-NUD spd info.
RAM_ID: 0110 4GiB Hynix H9CCNNN8GTALAR-NUD
RAM_ID: 0111 2GiB Hynix H9CCNNN8GTALAR-NUD

Original-Change-Id: I48386ff3e5f80de94ea87359a09a5ec2577043b5
Original-Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/664517
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I0ae76c4d8313246927bbc3f71b21f3611c89a6e3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26 10:46:56 +00:00
Matt DeVillier 0405109eed mb/google/eve: Update and fix VBT
Update Eve's VBT from v211 to v221, and change the backlight
control type from PWM to VESA eDP/AUX. This allows the OS to
select the proper backlight control type for the panel.

Test: Eve backlight control now functional under Windows 10
(Linux requires some pending patches to fix)

Change-Id: I8be2a719765891b3f2702c1869981009fa73ca05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26 10:46:42 +00:00
Elyes HAOUAS 4200a52263 src: Remove unused include <string.h>
Change-Id: Ic6b66dd8fa387e67bb0ce609fb7e2553eeb66b3c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-26 10:45:37 +00:00
Wisley Chen a8a7374e84 hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon
In https://review.coreboot.org/c/coreboot/+/37459
(commit fcd8c9e99e) which moves power/reset
pin control of FPMCU to var/board/ramstage, but does not implement it for
dratini/jinlon. So, add it in dratini/jinlon.

BUG=b:146366921
TEST=emerge-hatch coreboot

Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26 10:45:26 +00:00
Usha P e150876910 soc/intel/cannonlake: Clean up report_cpu_info() function
This patch makes below clean-up for report_cpu_info() function.
1. Remove unused variables.
3. Reuse fill_processor_name.

TEST = Successfully able to boot hatch and verify the
cpu_name "CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz"

Change-Id: I41c76eb93f0c5229c4a49ab041339b6ad51ad24a
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26 10:44:43 +00:00
Usha P 33ff4cc137 soc/intel/cannonlake: Refactor pch_early_init() code
This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like TCO
configuration and SMBus init into romstage/pch.c in order to maintain only
required chipset programming for bootblock and verstage.

Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.

TEST=Able to build and boot hatch successfully.

Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26 10:44:17 +00:00
Usha P 5395123b84 soc/intel/skylake: Rename pch_init() code
This patch renames pch_init function to bootblock_pch_init and
romstage_pch_init according to the stage it is defined in.

TEST=Able to build and boot soraka successfully.

Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26 10:44:00 +00:00
Subrata Banik f96c638a60 vendorcode/intel/fsp/fsp2_0/tgl: Add FSP header files for Tiger Lake
Add header files for FSP for Tiger Lake platform version 2457.

Change-Id: I52bb2e164cc89d3535fe67493686d1e8e064e31e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-12-26 10:43:42 +00:00
Wisley Chen f814ff15f9 mb/google/hatch/var/jinlon: Update DPTF parameters
The change applies the DPTF parameters received from the thermal team.

BUG=b:146540028
TEST=build and verified by thermal team.

Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-26 10:41:41 +00:00
Kevin Chiu 1f7a11699a mb/google/octopus/variants/garg: update new SKU
add new SKU ID below:
19 - Garg PVT (HDMI DB, Touch)
20 - Garg PVT (2A2C DB, Touch)
38 - Garg360 EVT (2A2C DB, touch, no stylues, rear camera)

BUG=b:146260545
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage

Change-Id: Ic74ce14db7060f3124c1a277eb3625ce0ff0b9f0
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-26 10:40:48 +00:00
Bill XIE 5dd4bf3644 mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants
Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions
to wire SuperSpeed-capable ports to XHCI in its devicetree, causing
these ports being wired to the second EHCI, and only working as USB
2.0 ports. The missing register definitions are added to fix that.

Tested on my ga-b75-d3v board.

Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26 10:39:42 +00:00
Patrick Rudolph e69798b5ae util/pgtblgen: Fix qemu on KVM
Running the x86_64 qemu mainboard target with '-accel kvm' results in hang,
as the 'D' and 'A' bits needs to be set in read only page tables.

Tested on QEMU Q35: Boots into payload with '-accel kvm'.

Change-Id: I4beae8deec6bf34f9762e7b54c5da4e5b63f6d24
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36778
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26 10:39:26 +00:00
Kyösti Mälkki b73111cfa7 soc/amd/common/car: Remove unneeded header
Change-Id: I9c65d3c54efcdec1ebb2648d078acdd9e7c11c49
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-26 08:25:20 +00:00
Kyösti Mälkki e6b313da36 cpu/intel/car/p4-netburst: Add assert for SIPI_VECTOR_IN_ROM
Location of _start16bit in entry16.inc is about to see some changes,
lets make sure they don't break the alignment requirement here.

Change-Id: Id8a0964982387e5321e8c89254922e1242cf85ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-26 08:11:30 +00:00
Mike Banon 2bdc05d89b asus/am1i-a: Switch away from ROMCC_BOOTBLOCK
Switching was done by moving a SIO configuration and
the clocks setup from 'romstage.c' to 'bootblock.c',
following the example of change CB:37719 (fc749b2).

TEST=Boots into Artix Linux 2019 without a problem.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-26 08:08:51 +00:00
Patrick Rudolph 7a70a46ecc mb/supermicro/x11-lga1151-series: Remove default devicetree values
The same default values are used if the values are not present in devicetree.

Change-Id: Ic910cdc8077e1b3e98eadc77a2d1fa0f9cb38e5b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Michael Niewöhner
2019-12-25 09:40:24 +00:00
Patrick Rudolph b824f7dbae soc/intel/skylake/vr_config: Use lookup table by default
If the board doesn't provide VRconfig in devicetree make sure to use
the lookup table for IccMax instead of defaults for some mobile SoC.

Also use decimal values instead of hex.

Change-Id: If31063f9b483a3bbd6cc90df1c1b76b4efc66445
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37598
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-25 09:40:00 +00:00
Edward O'Callaghan d33b02e7f3 mainboard/google/puff: Add GPIO configuration
BUG=b:144809606,142094759
BRANCH=none
TEST=none

Change-Id: Iae20d2262c910044dde84f10d795f4aee3318532
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Signed-off-by: Kangheui Won <khwon@chromium.org>
Co-Author: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37925
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-25 07:25:33 +00:00
Edward O'Callaghan 7899cd9088 mb/google/hatch/variant/kohaku: Fix Kohaku baseboard/gpio.c mux comments
Follow MEM_STRAP_* comment style to be consistent with other boards.

BUG=b:144809606
BRANCH=hatch
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I4945f676f307af9b8c0baa1fbcaf33113de647c3
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37592
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-25 07:24:50 +00:00
Edward O'Callaghan c735a31861 mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.

This patch handles the GPP_H3 gpio config for easier review. This
toggles the MAX amp which not all boards have. Move the pin
configuration to boards with the respective devicetree configuration
following on from the theme of commit b417786525.

BUG=b:142094759
BRANCH=none
TEST=builds

Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25 07:24:17 +00:00
Edward O'Callaghan 3dbe593906 mainboard/google/hatch: Move gpio GPP_C* NC down into baseboard
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.

This patch handles the GPP_C15 group for easier review.

BUG=b:142094759
BRANCH=none
TEST=builds

Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25 07:16:23 +00:00
Edward O'Callaghan c4a3f51618 mainboard/google/hatch: Move gpio GPP_A* NC down into baseboard
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.

This patch handles the GPP_A* group for easier review.

BUG=b:142094759
BRANCH=none
TEST=builds

Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25 07:04:02 +00:00
Kangheui Won 60889e55ea mainboard/variant/puff: set PL values for puff
To be safe for now, don't differentiate between SKUs and use lower
values to ensure board won't be browned out.

BUG=b:143246320
TEST=none
BRANCH=none

Change-Id: I041ebaa33bf2582386198290e625099ba8e2f3c9
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37651
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-24 23:37:20 +00:00
Raul E Rangel 028570b445 vendorcode/amd/pi/Kconfig: Add prompt to pre/post pi files
This allows the values to be set in a .config

BUG=none
TEST=Was able to set the value from a .config and built careena firmware

Change-Id: I757e4b9a0b80ff42c1f49143a44f15550366fd0b
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37879
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-24 16:33:29 +00:00
Edward O'Callaghan b417786525 mainboard/google/hatch: Remove MAX98357A assumption from baseboard
Generally work towards a more loose baseboard definition by moving out
some original assumptions to be board specifics. Specifically Puff does
not have the MAX98357A speaker amp and enabling the driver winds up
generating incorrect SSDT tables that confuse the kernel. Since
devicetree inherits the chip from device node in base and an override
will also inherit the chip and thus dispatch the unwanted fill_ssdt fn
call.

V.2: lean on linker to drop max98357a driver when not in dt.

BRANCH=none
BUG=b:146519004
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I8e7fed69a4c6d9610ac100da6bae147828ebfa81
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37909
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-24 00:08:42 +00:00
Edward O'Callaghan 295fdbef39 mainboard/google/puff: Configure HDA registers
Enable PCH HDA and configure dmic+ssp registers.

BRANCH=none
BUG=b:146519004
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: If9495261201ca256cdb35352338c0b3a82a50196
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2019-12-23 22:09:48 +00:00
Edward O'Callaghan e8b7ff1ab5 mainboard/google/puff: Enable func0 of 1c for nic
Two things here:

 i. ) FSP requires that function 0 be enabled whenever any non-zero
      functions hang under the same bus:device.

 ii.) FSP reorders function 6 RP to be function 0 if function 0 is
      indeed unused.

BUG=b:146437819
BRANCH=none
TEST=none

Change-Id: I0f499a23495e18cfcc712c7c96024433a6181a4c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-23 22:09:08 +00:00
Patrick Rudolph 95bff2e17e superio/common: Add more ACPI methods
* Make use of introduced SSDT config mode access
* Make use of introduced SSDT mutex
* Provide ACPI functions to safely access SIO config space
* Implement method to query LDN enable state
* Implement method to set LDN enable state
* Use introduced functions to implement _DIS and _STA in the device
* Update documentation

Tested on Aspeed AST2500 and Linux 5.2.
Manually verified ACPI code that generates no errors in Linux.

Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-22 13:47:55 +00:00
Patrick Rudolph 7db16ddc88 superio/common/conf_mode: Add op to write SSDT
Add functions to write ACPI SSDT code for entering and leaving
the config mode.
To be used by ACPI generators.

Tested on Linux 5.2 using the Aspeed SSDT generator.

Change-Id: I14b55b885f1c384536bafafed39ad399639868e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-22 13:47:39 +00:00
Angel Pons 0142d441c6 mb/**/dsdt.asl: Remove "Some generic macros" comment
It provides no useful information, so it might as well vanish.

Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-21 11:38:16 +00:00
Kyösti Mälkki 282717e5cc sb/amd/{agesa,pi,cimx}/bootblock: Use simple PCI config accessor
Change-Id: I5e1f2ceda37927d7a75660affee8504f9f8aff15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-21 11:37:15 +00:00
Kyösti Mälkki b915faedd5 sb/amd/{agesa,pi}/hudson: Use simple PCI config accessor
Change-Id: I3d8e21e17a0f870d854694e326b10f7d2d04e5ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37596
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-21 11:37:07 +00:00
Kyösti Mälkki 520717dff1 AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20 18:14:34 +00:00
Elyes HAOUAS b9bd69e70e src/mainboard: Remove unused '#include <device/pci.h>'
Change-Id: I5791fddec8b2387df5979adbb1a0fa64c5dd23ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-20 17:59:59 +00:00
Elyes HAOUAS ed69de318f mainboard: Add missing include <device/pci_def.h>
Change-Id: I8a7c989540e8b62de7fd291f695adac849f4680c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-12-20 17:59:42 +00:00
Bill XIE cdf6f3a4ba security/vboot: Add a dedicated flag for building of vboot library
As discussed in CB:35077, since both measured boot and verified boot
depends on vboot library, it had better to introduce a dedicated flag
CONFIG_VBOOT_LIB to control the building and linking of the vboot
library, and make other flags needing vboot library select it. Only
the actual verification stuff should be conditional on CONFIG_VBOOT.

Change-Id: Ia1907a11c851ee45a70582e02bdbe08fb18cc6a4
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-12-20 17:58:44 +00:00
Maulik V Vaghela e9b1e0fe88 soc/intel/tigerlake: Update FSP stack and heap size
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB
and heap size to be minimum 128 KiB.
Updating both Kconfig to meet size requirements.
Also updated required CAR region size during boot block due to increment
in stack & heap requirement by fsp

Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20 17:57:17 +00:00
Huayang Duan 6ee5559d6a soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell
The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps to improve DRAM stability.

BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-20 17:57:03 +00:00
David Wu 6de7ecb585 mb/google/hatch/var/kindred: Decrease i2c frequency below 400 KHz
Before tuning i2c frequency,
I2C0: 479.4 KHz
I2C1: 491.4 KHz
I2C4: 476.4 KHz

After tuning i2c frequency,
I2C0: 391.8 KHz
I2C1: 396.4 KHz
I2C4: 388.8 KHz

BUG=b:146535585
BRANCH=hatch
TEST=emerge-hatch coreboot chromeos-bootimage

Change-Id: I55d095efb60eba4e860b54bb90e8e0df62d88419
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37831
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20 17:56:06 +00:00
Wisley Chen 9ac409c7e5 mb/google/hatch/var/jinlon: Config WWAN_RESET
jinlon supports LTE, so remove WWAN_RESET NC configuration

BUG=none
TEST=emerge-hatch coreboot

Change-Id: Ibc5d21f0a33952f519265a5ce2df559a79346d9e
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37837
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20 17:55:36 +00:00
Michał Żygowski 727ac0d263 AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID
PCI devices starting from 18 are processor configuration devices for each
node and are not a bus itself.

According to ACPI specification 6.3 section 6.1.5:

"... _HID object must be used to describe any device that will be
enumerated by OSPM. OSPM only enumerates a device when no bus enumerator
can detect the device ID. ... Use the _ADR object to describe devices
enumerated by bus enumerators other than OSPM."

PCI device 18 with its functions has a standard enumerator, which is PCI
enumerator so it needs a _ADR. Create a separate ACPI device for the
processor configuration space. This fixes the ACPI compliance problem
from CB:36318.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20 17:54:42 +00:00
Elyes HAOUAS a87a741b41 crossgcc: Upgrade Python to version 3.8.1
Change-Id: I2867d62d2e6f5ca1e97ce52ecc45a794b4831686
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-20 17:51:49 +00:00
Kyösti Mälkki bba4ec4ca1 superio/smsc/lpc47m10x: Expose pnp_enter/exit_conf_state
Change-Id: I55915b63dbb097634a228193f62395e45a1f42fe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-12-20 17:51:10 +00:00
Wim Vervoorn f863176423 mb/facebook/fbg1701: Correct typo in hda verbs
The MIC1 NID is configured incorrectly because of a typo. The value is 7
digits instead of 8. This is corrected by this patch.

No issues are known because of this (the MIC is not connected).

BUG=N/A
TEST=build

Change-Id: Ia12f3be7d7262829cce3400a8535a33ea1c54b78
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-20 17:50:54 +00:00