Commit Graph

44076 Commits

Author SHA1 Message Date
Furquan Shaikh e1ba1c03ab drivers/gfx/generic: Drop unused find_gfx_dev
This change drops the function `find_gfx_dev()` as it is unused now.

Change-Id: Ie42707bd45348dc7485ca0ca12ebff2994897e6b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21 01:10:23 +00:00
Furquan Shaikh ebf1482627 mb/google/hatch/var/jinlon: Switch to using device pointers
This change replaces the device tree walks with device pointers by
adding alias for igpu (integrated graphics) device in the tree.

Change-Id: I6d159f6dc674f4a0b38ebb553c5141105405a883
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21 01:10:14 +00:00
Furquan Shaikh 56fd6419c3 mb/google/guybrush: Switch to using device pointers
This change replaces the device tree walks with device pointers by
adding alias for following devices:
1. FPMCU
2. WWAN

Additionally, this change drops the __weak attribute for variant_has_*
functions as there is no need for different implementations for the
variants.

Change-Id: I8af5e27f226270e6b40a50640c87de99a5a703f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21 01:10:06 +00:00
Furquan Shaikh e7821e8de0 mb/google/dedede: Clean up LTE device enabling
On some dedede variants, USB port 2.3/3.3 might be connected to either
LTE device or Type-A external port depending upon FW_CONFIG. Commit
856b579 ("mb/google/dedede/var/kracko: Update LTE USB port
configuration") enabled Type-A external port by default in override
tree and updated the config dynamically for LTE USB device if
FW_CONFIG indicated support for it. This was required because sconfig
lacked the support for multiple override devices. Commit
b9c22e0 ("util/sconfig: Compare probe conditions for override device
match") fixed this behavior in sconfig and now we can add multiple
override devices using different FW_CONFIG probe statements in
override tree. Hence, this change moves the LTE USB device to override
tree for metaknight, kracko and drawcia variants.

In addition to that, drawcia needs to be update reset_gpio depending
upon board_id. Thus, alias `lte_usb2` is used in drawcia override tree
to fix the reset_gpio for older boards i.e. board_id <= 9.

Change-Id: Ie5b205594680d9c2b8543c5c99325d95620cafd2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21 01:09:59 +00:00
Furquan Shaikh 2cf88c185a mb/google/dedede/var/sasukette: Drop special codec device handling
On sasukette, codec device might be either 10EC5682 or RTL5682
depending upon the provisioned FW_CONFIG value for
AUDIO_CODEC_SOURCE. The HID for the device was updated in ramstage.c
because sconfig lacked the support for multiple override
devices. Commit b9c22e0 ("util/sconfig: Compare probe conditions for
override device match") fixed this behavior in sconfig and now we can
add multiple override devices using different FW_CONFIG probe
statements in override tree. Hence, this change moves the codec device
to override tree and drops the special handling in ramstage.c

This change also probes for UNPROVISIONED value of FW_CONFIG for
"10EC5682" device since some devices might have shipped with
UNPROVISIONED value and using "10EC5682" device.

Change-Id: I909a29c3df0cbb7ac3c07ca7663a49ad47007232
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21 01:09:52 +00:00
Ricardo Quesada e48043b095 elogtool: compile in 32-bit platforms
This CL fixes a compilation error that happens in 32-bit platforms.
This error happens because printf() was using %ld instead of %zu to
print size_t variables.

This CL fixes it.

BUG=b:200608182
TEST=emerge-kevin (ARM 32-bit)
TEST=emerge-eve (Intel 64-bit)

Change-Id: I340e108361c052601f2b126db45caf2e35ee7ace
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-09-21 01:02:56 +00:00
Reka Norman b05edb1fea util/spd_tools: Implement a unified version of the part_id_gen tool
Currently there are two versions of gen_part_id.go, one for LP4x and one
DDR4. This change implements a unified version of this tool.

The new part_id_gen.go is almost identical to the existing
ddr4/gen_part_id.go. The new version was based on the ddr4 version and
not the lp4x version, since the ddr4 version contains extra logic to
support fixed IDs in the mem_parts_used files.

The only non-trivial change from ddr4/gen_part_id.go is to include the
full paths of SPD files in the generated Makefile.inc. E.g. instead of

  SPD_SOURCES += lp4x-spd-1.hex

the full path relative to the coreboot root directory is included:

  SPD_SOURCES += spd/lp4x/set-0/spd-1.hex

BUG=b:191776301
TEST=For each variant of brya/volteer/dedede/guybrush/zork, run
part_id_gen and verify that the generated Makefile.inc and
dram_id.generated.txt are identical to those currently in the src tree,
except for the modified SPD file paths in Makefile.inc.
Example:
util/spd_tools/bin/part_id_gen \
  spd/lp4x/set-0 \
  src/mainboard/google/brya/variants/kano/memory \
  src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt

Change-Id: Ib33d09076f340f688519dae7956a2b27af090c0b
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20 23:51:07 +00:00
Reka Norman cf0014b145 spd: Add a placeholder SPD file to spd/
When a new variant is created, its SPD_SOURCES contains a placeholder
file, to avoid a build failure due to SPD_SOURCES being empty. Currently
these placeholder files live with the rest of the SPD files in soc and
mainboard directories, e.g.
src/soc/intel/alderlake/spd/placeholder.spd.hex

Add a similar placeholder SPD file to the new spd/ directory.

BUG=b:191776301
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ia6d76ed512a7e44221fc93ad960790be575c44c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-20 23:50:49 +00:00
Reka Norman c65fba87b3 spd: Generate SPDs under spd/ using unified spd_gen tool
Use the new unified version of the spd_gen tool to generate all LP4x and
DDR4 SPDs, storing them in a new spd/ directory. Storing them in a
common location allows platforms with the same SPD requirements to share
SPD files, reducing duplication compared to storing SPDs in soc/ and
mainboard/ directories.

For each memory technology there are multiple sets of SPDs. Each set
corresponds to a set of platforms with different SPD requirements, e.g.
due to different memory training code expectations. A manifest file
(platforms_manifest.generated.txt) lists the platform -> set mappings.

Commands used to generate SPDs:
cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \
    spd/lp4x/memory_parts.json
cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \
    spd/ddr4/memory_parts.json
util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4

BUG=b:191776301
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20 23:20:50 +00:00
Furquan Shaikh 522174ba38 mb/google/volteer: Switch to using device pointers using alias names
This change replaces the device tree walks with device pointers by
using alias names for the following devices:

1. PMC MUX connector
2. SPI TPM
3. I2C TPM

Change-Id: I38f87d3a90a7253f2a29aba7db9a9f9744985494
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20 23:08:42 +00:00
Furquan Shaikh 4aba7395b7 mb/google/brya: Switch to using device pointers using alias names
This change replaces the device tree walks with device pointers by
adding alias for dptf_policy generic device in the tree.

Change-Id: I8fd5476a9cea84ab8b2678167b3e0504eecacf6c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20 23:08:34 +00:00
Wisley Chen 364aa76b9d mb/google/brya/var/redrix: Enable EC keyboard backlight
Enable EC keyboard backlight for redrix.

BUG=b:192052098
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage

Change-Id: I175d8b91b37c6645ab1a7f05fc6915b3b016e3ff
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20 18:54:20 +00:00
Shelley Chen 212f48daf2 herobrine: Add Hoglin variant
Create a variant for the QC CRD device.

BUG=b:197366666
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HOGLIN -x -a -B

Change-Id: I883d17b3ad3c7e44a00f0d0e7007c119417c5028
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-20 17:36:53 +00:00
Tim Wawrzynczak 56791b2841 soc/intel/elkhartlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.

Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).

BUG=b:181678769

Change-Id: I95753fa536fae8ca4bb95007419875815c1bcb06
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20 15:44:16 +00:00
Tim Wawrzynczak 38d38479fa soc/intel/icelake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.

Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).

BUG=b:181678769

Change-Id: I1a55df754c711b2afb8939b442019831c25cce29
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20 15:44:12 +00:00
Tim Wawrzynczak ff8d0e64a7 soc/intel/jasperlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.

Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).

BUG=b:181678769

Change-Id: Idfaa9a24f7b7fefa4f63ab8e3bc4ee6a0f1faedf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20 15:44:09 +00:00
Tim Wawrzynczak e186821952 soc/intel/tigerlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.

Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).

BUG=b:181678769

Change-Id: Ie86822f22aa5899a7e446398370424ca5a4ca43d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20 15:44:07 +00:00
Paul Menzel 1a7640dc62 vc/amd/sb800: Fix out of bounds shift
Fix the two issues below.

    SB800: sb_Before_Pci_Init
    shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:49:18
    ubsan: unrecoverable error.

    SB800: sb_Before_Pci_Init
    shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:66:18
    ubsan: unrecoverable error.

Found by: UBSAN
Change-Id: Id42e62d35f59793bad10998f14422ab7fb4fc029
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-09-20 15:43:26 +00:00
Julian Schroeder f9080ce6d9 soc/amd/cezanna/acpi/mmio.asl: enable ACPI AOAC for I2C
This enables runtime power management for the I2C controllers.

BUG=b:182556027, b:183983959
TEST=enable dynamic debug in kernel and check i2c D3/D0 transitions
during suspend_stress_test.

Change-Id: Ia6b9ca95d751f32b7cd701494377f15091c22d2f
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56462
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20 12:56:21 +00:00
Felix Held d453208623 soc/amd/cezanne/acpi/mmio: uncomment AOAC_DEVICE macro for UARTs
This enables runtime power management for the UART controllers.

BUG=b:183983959

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e57d6312feda459cec65f330c6d2072774d4eb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-20 12:50:01 +00:00
Wisley Chen 9cc550eb8e driver/i2c/max98390: Add vmon_slot_no/imon_slot_no property
Add two properties (maxim, vmon-slot-no/maxim, imon-slot-no) in maxim9839 driver.
This is  I/V source destination definition that from below properties .
maxim,vmon-slot-no => PCM_IVADC_V_DEST
maxim,imon-slot-no => PCM_IVADC_I_DEST

BUG=b:197076844
TEST=build and check SSDT

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Idb24d19c7cfea559bf6d53f401d66cadb8b3acc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20 12:40:51 +00:00
Reka Norman a2c009bd94 util/abuild: Regenerate xcompile on every abuild run
Currently, running abuild in a fresh checkout without having built the
toolchain results in the following confusing behaviour:
1. Run abuild. It fails due to the missing coreboot toolchain, and the
   error message suggests running `make crossgcc`.
2. Run `make crossgcc`. It succeeds.
3. Re-run abuild. It still fails due to a missing coreboot toolchain.

This happens because the first abuild run generates an xcompile file
which uses the system toolchain. The second abuild run doesn't
regenerate the xcompile, so it still fails due to the non-coreboot
toolchain.

To avoid this confusing behaviour, regenerate the xcompile file every
time abuild is run.

BUG=None
TEST=Perform the steps above in a clean checkout. The second abuild run
now succeeds.

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I78a7702c45cecbfe8460ec55df03741e5ced94b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-20 12:21:05 +00:00
Michael Niewöhner 5307f12e9c soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC support
Currently, Intel TME (Total Memory Encryption) can be enabled regardless
of SoC support. Add a Kconfig to guard the option depending on actual
support.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia20152bb0fc56b0aec3019c592dd6d484829aefe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-20 12:19:39 +00:00
Furquan Shaikh 26e2afdd77 device: Add helper macros for device pointers using alias names
This change provides helper macros for generating pointer name and
weak pointer definition for devices using alias names. This will be
helpful for developers to reference the device pointer with alias
names used in the device tree.

Change-Id: I3a5a3c7fdc2c521bac9ab3336f5a6ebecd621e04
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20 12:17:50 +00:00
Furquan Shaikh 0df32c85ad sconfig: Emit device structure pointers if alias names are provided
This change uses _dev_${ALIAS_NAME} as the name for `struct device` if
the device has an alias. In addition to that, it emits
_dev_${ALIAS_NAME}_ptr which points to the device structure. This
allows developers to directly reference a particular device in the tree
using alias name without having to walk the entire path. In later CLs,
mainboards are transitioned to use this newly emitted device structure
pointers.

Change-Id: I8306d9efba8e5ca5c0bda41baac9c90ad8b73ece
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20 12:17:13 +00:00
Wisley Chen f0227ee2a8 mb/google/brya/var/redrix: Get wifi sar name
Add get_wifi_sar_cbfs_file_name() to return the wifi SAR file name

BUG=None
TEST=FW_NAME=redrix emerge-brya coreboot

Change-Id: I87e7a30619fd93d0eae692c4c540c29850ff6721
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20 12:16:04 +00:00
Wisley Chen 99204bbda6 mb/google/brya: Add CHROMEOS_WIFI_SAR
Add CHROMEOS_WIFI_SAR to include the SAR configs.

BUG=None
TEST=FW_NAME=redrix emerge-brya coreboot

Change-Id: I50a413f3425d0b0e0b5ce71dabf6b9477800795e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20 12:15:52 +00:00
JingleHsuWiwynn 5f08ef9639 device/dram/spd.c: Add more manufacturer ID codes
Add manufacturer ID codes for Hynix, Samsung and Micron.

Tested=On OCP Crater Lake, dmidecode -t 17 shows expected info.

Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I0b4bbc46d3bfd9e9534cdd59f90cbdc150f29542
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daocheng Bu <daocheng.bu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20 12:12:46 +00:00
Tim Crawford 800754fea3 mb/system76/cml-u: Add Darter Pro 6 as a variant
Change-Id: I9ba7d2af3c9c298fda2b2997d52546cc2f702a82
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-20 12:11:50 +00:00
Tim Crawford f8ba8980fd mb/system76/cml-u: Add System76 Galago Pro 4
Change-Id: I3dfa2ab430439d8dc71531b92aa7800db94d603b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-20 12:11:28 +00:00
Angel Pons ccbbb1bbd4 vc/amd/agesa/Kconfig: Move SPD options out of choice
The Kconfig options for custom SPD values aren't supposed to be part of
the choice block.

Change-Id: I12eb1012f94000b14e5d7f1e5123dddf69ac1a94
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57717
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20 12:09:47 +00:00
Eric Lai 1897a3abd9 mb/google/brya/var/felwinter: Configurate AUX pin for USB3 MB
USB3 MB doesn't have re-timer. Thus we have to configurate the AUX pin.
For now, we use USB3 DB to determine the USB3 MB.

BUG=b:197907500
TEST=NA

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ide45c77e0a6f736a02d5dc9ad05aa1ef9e754fa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20 12:09:30 +00:00
Rex-BC Chen 50eff1c083 mb/google/cherry: Fix unusable USB3 HUB
To save the S3 power, USB3_HUB_RST_L is externally pulled up to a
weak resistor so we have to reset the hub via GPIO84 as early
as possible. Otherwise the USB3 hub may be not usable.

BUG=b:199822702
TEST=measure voltage of USB3_HUB_RST_L as 1.8V

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie87d631e83ede819ee9f9951dfc6517beae50247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57663
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20 12:08:56 +00:00
Wisley Chen 58d2943c3a mb/google/brya/var/redrix: Update thermal table.
Update thermal setting from thermal team.

BUG=b:200134784
TEST=build and verified by thermal team.

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: If74c3bc19cf4abd64d646b842cbb6a61b910e933
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20 12:08:24 +00:00
Julius Werner ea03d0047b device/mmio: Make buffer_to_fifo32() take a const buffer
The input buffer to the buffer_to_fifo family of functions is only read,
so it can be a const pointer. (Also, remove the MIPS check in libpayload
for these functions... the MIPS architecture has been removed a while
ago.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-20 12:07:51 +00:00
Patrick Georgi 1c8e8b259d arch/riscv: Avoid gcc11 replacing memset implementation with memset call
SBI comes with its own memset implementation (under a slightly
different name) that gcc11 "helpfully" tries to replace with a call
to memset(). Since we don't provide a memset, the linker isn't happy,
so prevent gcc from doing that.

Change-Id: I3459a519d46a123f873306000b8b2261bd64e0c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-19 18:52:22 +00:00
Patrick Georgi f28e368d58 util/crossgcc: Update binutils to 2.37
Change-Id: Ia68d4d9f836ad23fb8f6a7203a78b4ea40c7c43b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-19 18:51:52 +00:00
Raul E Rangel e74b0b6a5e console: Remove asmlinkage from console_init
We never call console_init from asm, so we don't need the asmlinkage.
This allows us to remove the arch/cpu.h include since we only needed it
for the asmlinkage #define.

BUG=b:179699789
TEST=build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9a7895d4f5cba59f6b05915fa4d6c6fd6ab85773
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57568
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-17 23:52:02 +00:00
Felix Held 6397e0ee41 drivers/ipmi/ocp: add missing commonlib/bsd/cb_err.h include
This include provides the definition of enum cb_err.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idfee720de920377796e3fd64cb47514b8cb08c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 22:32:51 +00:00
Felix Held 4ceef0ecce sb/intel/ibexpeak/early_cir: add missing arch/cpu.h include
Including arch/cpu.h is needed to have the declaration for cpuid_eax,
get_fms and struct cpuinfo_x86.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18b60f8cf33f71c7215a97ea209b8f8cf66cf42f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 22:32:29 +00:00
Felix Held ae546ecc27 drivers/gic/gic: add missing arch/cpu.h include
smp_processor_id is defined in src/arch/arm64/include/armv8/arch/cpu.h.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0b610189bf439774cb900f74559dee314cbc5854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 22:31:58 +00:00
Felix Held 6266c417a2 sb/intel/bd82x6x,ibexpeak,lynxpoint/me.h: add missing includes
Include device/device.h to have struct device defined and types.h to
have bool, u8, u16 and u32 defined.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3c5d5a78c2e2dab21432ced5f84665eb78a49d52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 22:31:48 +00:00
Michael Niewöhner 0e25580fe1 soc/intel/{ehl,jsl}: make use of Kconfig options for PRMRR size
Migrate the last two platforms to using Kconfig through
`get_valid_prmrr_size()` instead of hardcoded values in the devicetree.

Change-Id: I93aa177f741ca8b2a2d50fae2515606b96784e83
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17 22:22:20 +00:00
Malik_Hsu 1ad9ff8156 mb/google/brya/primus: add NVMe power and reset pin to early_gpio_table
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that primus can successfully
boot into OS with non-serial coreboot.

BUG=b:199967106
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I9c66efe96515347502d059556052c764c1be5d09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17 22:20:05 +00:00
Sunwei Li 8d46db20a3 mb/google/dedede/var/cappy2: Update DPTF parameters
Update DPTF parameters from internal thermal team.

BUG=b:197546694
BRANCH=dedede
TEST=emerge-keeby coreboot

Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I71a76a4d94a704aef7b3cefa2fca3009eb765bb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57693
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-17 22:19:53 +00:00
Felix Held b0e11503e7 security/intel/txt/romstage: add missing arch/cpu.h include
Including arch/cpu.h is needed to have the declaration for
cpu_get_feature_flags_ecx.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I091c82f5a55ee9aa84a255c75c7721eff989344d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 20:28:19 +00:00
Felix Held 1fb2e1eb42 cpu: add missing arch/cpu.h includes
Including arch/cpu.h is needed to have the declaration for cpuid_eax.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic22aba062117e3afa818fa2fc39cb0738e6a1612
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 20:28:09 +00:00
Felix Held 5f12b7b214 mb/scaleway/tagada/bmcinfo: replace stdbool.h include with types.h
Apart from the u8, u16 and u32 types, the bool type is used in this file
so include types.h instead of stdint.h to have bool defined too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95f037deb0fe11b717586df655065bfbb33b0d23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 20:27:58 +00:00
Felix Held 5340abcd2f soc/amd/common/block/pi/image: replace stdbool.h include with types.h
Apart from the bool type, uint8_t, uint32_t and uint64_t are used in
this file, so include types.h instead of stdbool.h.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 20:27:42 +00:00
Felix Held dd9edefa15 arch/riscv/trap_handler: add missing types.h include
Both bool and uintptr_t types are used in this file, so include types.h
to have the definitions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I647d9f50cd6edaf08bebf5d713cd05731fadfc1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 20:27:34 +00:00