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11 commits

Author SHA1 Message Date
Patrick Georgi
22579596ff soc/intel/*lake: Load vbt when it's needed 
That removes the need for another global variable.

Change-Id: I25e12ba724836de4c8afb25cd347cafe6df8cea9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21907
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-10-09 07:10:54 +00:00
Patrick Georgi
9d3de2649f soc/intel/common: refactor locate_vbt and vbt_get 
Instead of having all callers provide a region_device just for the
purpose of reading vbt.bin, let locate_vbt handle its entire life cycle,
simplifying the VBT access API.

Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-10-06 16:59:31 +00:00
Abhay kumar
fcf8820505 soc/intel/cannonlake: Add FSP GOP support 
1. Add FSP GOP config.
2. Pass VBT to FSP.

Change-Id: Icf836d683ae00cd034c853bc9ce965d4de5f7413
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-09-27 04:01:45 +00:00
Aaron Durbin
aa090cb6ea device: acpi_name() should take a const struct device 
There's no reason to mutate the struct device when determining
the ACPI name for a device. Adjust the function pointer
signature and the respective implementations to use const
struct device.

Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2017-09-14 14:34:27 +00:00
Lijian Zhao
0823183323 soc/intel/cannonlake: Add serialio device config 
Add SerialIO device mode configuration, device mode definition mirrored
from FSP.

Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-09-13 22:56:09 +00:00
Lijian Zhao
2b074d90ae soc/intel/cannonlake: Add common ACPI support for CNL 
Basic ACPI support for CNL on top of common ACPI, which will establish
a root of FADT table, fill MADT entry, create gnvs field, record wake
status and convert device names into DSDT dev definitions.

Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-09-13 03:09:15 +00:00
Pratik Prajapati
9027e1ba2f soc/intel/cannonlake: Init UPD params based on config 
Initialize UPD params based upon config

Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21175
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-25 18:24:33 +00:00
Pratik Prajapati
201fa8ffe5 intel/cannonlake/chip: Add initial PCI enum support 
Add callbacks for initial PCI devices enumeration.

Change-Id: Ia8a51973aa2b805d62590114bfc49968244b1668
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2017-08-17 19:23:48 +00:00
Lijian Zhao
2f764f7dfe soc/intel/cannonlake: Call into FSP siliconinit 
The following changes can make system call into FSP siliconinit and exit
from that until payloads.

1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.

This patch was merged too early, and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20581

Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20687
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-15 20:21:31 +00:00
Martin Roth
70de396958 Revert "soc/intel/cannonlake: Call into FSP siliconinit" 
This reverts commit dbe7f893c0.

This was merged too early.  I'll repost it.

Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-07-21 17:32:07 +00:00
Lijian Zhao
dbe7f893c0 soc/intel/cannonlake: Call into FSP siliconinit 
The following changes can make system call into FSP siliconinit and exit
from that until payloads.

1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.

Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-21 15:56:16 +00:00