The following original authors agreed to the license:
- Ronald G. Minnich <rminnich@gmail.com>
- Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- Stefan Reinauer <stepan@coresystems.de>
- Andrei Birjukov <andrei.birjukov@artecdesign.ee>
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to set the right GPIO pins, so write protection is disabled.
Signed-off-by: Mondrian Nuessle <nuessle@uni-mannheim.de>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
as that is not RAM but used for other stuff.
First try at PCI init added to src/mainboard/tyan/s1846/Config.lb.
Use a real payload (FILO) per default now.
Note: this cannot boot a payload, yet, but it gets a lot further now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
it fixes. It seems many of the other boards run out of space for the
payload.
Thus, this patch only increases the image size for the three boards
- tyan/s2912
- nvidia/l1_2pvv
- gigabyte/m57sli
by adding a custom Config-abuild.lb file for each of them.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
For files derived from the Linux kernel we merely add a small header
which states the origin of the file and the copyright owners of the
modifications to the file.
We know all files from Linux are licensed under the GPLv2.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Comment out code which currently doesn't compile. Needs fixing later.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
instead of stdout (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Drop AMD prototype mainboards that were for internal testing &
validation use only.
Note: These boards could never be purchased. No reasons to worry.
Questions welcome via private mail.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
abuild with a payload. Trivial
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
artecgroup/dbe61
Add CONFIG_COMPRESSED_PAYLOAD_NRV2B to Options.lb since it's used in
Config.lb.
Change default for CONFIG_PCI_ROM_RUN to 1 so VGA ROM can run.
technologic/ts5300
Removed CONFIG_CONSOLE_VGA, the embedded board has no VGA without the
development addon card anyways.
Changes to target Config.lb so it actually builds.
Signed-off-by: Peter Stuge <peter@stuge.se>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* going back to old board specific dsdt for agami aruma.
This is hopefully dropped again some day, but until then
here's a working solution.
* Some minor Agami specific changes.
* drop obsolete bringup workaround hyperclocking.diff
* increase image size again, x86emu wants it.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It shows the remaining space in an image now.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
all.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I'm guessing nobody has tried compiling it with 64bit userspace?
Patch makes it compile cleanly and stops a "SEGV instead of working"
issue.
I also added a few checks for errors on system calls.
Signed-off-by: Jeremy Jackson <jerj@coplanar.net>
Reworked and
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
when CONFIG_CONSOLE_VGA==0 and CONFIG_PCI_ROM_RUN==1
Signed-off-by: Roman Kononov <kononov@dls.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Drop a lot of debugging code from northbridge.c
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
dead code and adding a few fixmes.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
changes are correct. If someone could look into this, thank you.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
likely break the build, since it is only a small part, but it needs to
go in at some point and doing it directory by directory makes things
easier.
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
this fix, LinuxBIOS crashes if the CONSOLE_LOG_LEVEL is high enough.
Additionally, The VGA option rom will be executed if either
CONFIG_PCI_ROM_RUN=1 or CONFIG_CONSOLE_VGA=1.
Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Drop empty file (0 bytes) northbridge/amd/amdk8/cpu_rev.c
and references to it.
* move config option decision to preprocessor instead of code
since config options can not change during runtime
* slightly more verbose output in built_opt_tbl.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Only open /dev/mem once and do it early.
* Drop extern for function prototypes.
* Minimize ts5300 impact in probe_flash()
This cleanup will making ICH7 SPI support quite some easier.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This splits up the ROM Write enable code into chipset specific and
board specific parts. This of course means that a lot of code is
plainly moved about.
* Allows for linuxbios name matching and pci-subsystem id matching.
The latter uses a double set to properly distuinguish boards despite
of some known vendors being lax about it.
* Fixes GPIO15 being raised on every VT8235 southbridge, regardless of what
that line actually controls; rom on EPIA-M, backlight on mitac 8999 laptop.
* Adds flashrom support for Asus A7V400-MX (KM400 + VT8235)
* Island aruma was renamed agami aruma, the board specific code now got
adjusted. A set of pci-ids was retrieved from source code.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's not fully working, among other things because the Intel
440BX northbridge isn't working, yet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
port(s), and nothing else. The code in superio.c will initialize the
rest when RAM is available...
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This does _not_ fully work, yet. You will _not_ be able to boot any
payload with this code, yet.
Add missing license headers.
Base the northbridge.c file on the Intel 855PM version, that comes
closer to what we want.
The raminit.c file is written from scratch and hardcodes several
values for now. This needs to be fixed later by reading the
correct values via SPD.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Jordan Crouse