Wacom I2C driver can be used by devices other than
touchscreen. e.g. digitizer. So there is no need to name the driver
with touchscreen specific attributes. Only a separate descriptor name
is required that needs to be set by mainboard correctly.
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Compiles successfully.
Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17341
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Program I/O expander connected on I2C bus 4
Change-Id: I1a431f50e7b06446399a7d7cb9490615818147e7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/thomson/ip1000.
Change-Id: Id7b979d2539d4a80609a60464527939c4d449822
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17308
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/supermicro/h8qme_fam10.
Change-Id: Ia03c205ce498eadf8a34749a6a21fb2d0b29c840
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17306
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/supermicro/h8qgi.
Change-Id: I6cf123272283edbf89e854e4aa1a15a2d566133e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/roda/rk9.
Change-Id: I56fec2a2814ee4b91b11f71dbdca1271792cd0e5
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17302
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/roda/rk886ex.
Change-Id: I2e88adc444dbbde7a4344829d7bd5a6c9e1f7531
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17301
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/rcs/rm4100.
Change-Id: I8b242eefe796cd93337177fc694ea42c57c53f08
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17300
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Pyro is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.
BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17335
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Maxim98357a speaker amp requires BCLK & SFRM to be active
and stable before it is unmuted. If there is a BLCK and no
SFRM, it results in a pop sound.
sdmode_delay property already exists which facilitates this
configuration. This patch updates "sdmode_delay" to avoid
pop sound.
BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I5aee41957c9de7a05f962d3ede74efc6998a78fc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17336
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
1. Add RECOVERY_MRC_CACHE region to reef FMAP.
2. Implement helper function for getting event for recovery mode with
memory retraining.
3. Select HAS_RECOVERY_MRC_CACHE.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified recovery mode behavior with and without memory training
request on reef.
Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17243
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the use of the old device_t definition inside
mainboard/kontron/986lcd-m.
Change-Id: Ib47a4bb3580cb72ee51fb06c6faa6d2d1bd3a80c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/jetway/j7f2.
Change-Id: I37f59f74ac22fbf6e036cdb0515301e8dec400fb
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17296
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/iei/pm-lx2-800-r10.
Change-Id: I60e5b84141aa4998427c3ecaadf8fce1654b8210
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17295
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/ibase/mb899.
Change-Id: Id5b460090db58e91b2c210d8633a69114a9c7f6b
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17294
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/getac/p470.
Change-Id: Ifb81976ed7068f9d51edb0d297cd4a12265c51ec
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17293
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
WACOM request to add a new identifier `WCOMNTN2`,
and use that for the board Pyro with all LCD combinations.
BRANCH=master
BUG=chrome-os-partner:58093
TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage
Signed-off-by: Janice Li <janice.li@quantatw.com>
Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307
Reviewed-on: https://review.coreboot.org/17257
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The T400 features a socket P (mPGA478MN) and could potentially support
model_6fx CPUs.
Change-Id: I24f3356aa213c29011953daed31f46404e7a4d9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17155
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Startpoint was Intel d945gclf, which has same chipset and
Gigabyte ga-g41m-es2l which has same Superio.
What works and is tested:
* PCI slot;
* PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card;
* onboard VGA output (only textmode implemented) with native graphic init;
* 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset);
* serial output during and after boot.
What does not work:
* resume from suspend (does not work for d945gclf either).
Quirks:
* The Realtek ethernet card requires a reset which currently also
hardcodes a MAC adress.
This board was only tested with the SeaBIOS payload due to flash size
constraints (512KB) and with GNU/Linux.
Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17033
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Configure overcurrent pins for various usb ports.
Configure CdClock to 3.
Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17251
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
After tuning the temperature values for optimal performance,
this patch updates few DPTF settings for Kunimitsu board.
BUG=None
BRANCH=None
TEST=Built and booted on Kunimitsu boards. Verified these
updated DPTF settings with different workloads.
Change-Id: Ic1c319262d80cc5cb29a8630af213822308f8bed
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/350223
Reviewed-on: https://review.coreboot.org/17069
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
After tuning the temperature values for optimal performance,
this patch updates few DPTF settings for lars boards.
BUG=chrome-os-partner:51025
BRANCH=firmware-glados-7820.B
TEST=Built and booted on lars DVT boards. Verified these
updated DPTF settings with different workloads.
Change-Id: I4c040526c31c3263ed3a9b4cccff3b7a021cfcdb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/338877
Reviewed-on: https://review.coreboot.org/17068
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be
configured as native mode to use them for DMIC record
on other potential DMIC's.
DMIC blobs configure the clocks. For stereo & quad channel
record, both CLK_A1 and CLK_B1 are enabled.
For mono channel record, only CLK_A1 is enabled.
BUG=chrome-os-partner:56918
BRANCH=None
TEST=During DMIC record, check CLK_B1 and DATA_2 lines
Change-Id: I838009b85190de5360d593238e48c9593c1dc43a
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17199
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Note that currently, traps are only handled by the trap handler
installed in the bootblock. The romstage and ramstage don't override it.
TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux
payload. It worked as much as before (Linux didn't boot, but it
made some successful SBI calls)
Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Ron's code calculated the DLL and DLM registers of the 8250 UART, but
that's the job of the UART driver. uart_input_clock_divider isn't needed
anymore because the default value of 16 works.
As a bonus, the baud rate can now be selected in Kconfig, instead of
being hardcoded at 115200.
TEST=Booted the board at 9600 and 115200 baud.
Change-Id: I3d5e49568b798a6a6d944db1161def7d0a2d3b48
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17188
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This brings the frequency down to 400kHz which is spec for
fast i2c.
BUG=chrome-os-partner:58889
Change-Id: Ibc5f152e55ed618f18ac6425264f086b1f2d1ffa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17215
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This brings the frequency down to 400kHz which is spec for
fast i2c.
BUG=chrome-os-partner:58889
Change-Id: I8689a062b5457aa431eaa7fb688a7170dad83fcf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17214
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
1. Update gpio.h to set proper pad config for Kaby Lake RVP3.
2. Set spd index to zero.
3. Remove nhlt specific init.
Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
There are two configs, sdram-lpddr3-hynix-2GB.inc and
sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14.
Changing .ddrconfig from 14 to 3 improves performance
especially on contiguous memory accesses. Comparing the .ddrconfig:
- if .ddrconfig = 3,
C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C---
- if .ddrconfig = 14,
C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C---
where
- R: indicates Row bits
- B: indicates Bank bits
- C: indicates Column bits
- D: indicates Chip selects bits
.ddrconfig = 3 has multiple banks switching which improves DDR timing.
BUG=chrome-os-partner:57321
TEST=Boot from fievel and play video
BRANCH=veyron
Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e
Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/404691
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
framebuffer address is dynamically chosen by libpayload now, so there's
no need to configure it in coreboot.
CQ-DEPEND=CL:401402
BUG=chrome-os-partner:58675
BRANCH=none
TEST=Boot from kevin, dev screen is visible
Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c
Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/401401
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17109
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to
train alternative configurations first, so do the training and store the
values.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: I944a4b297a4ed6966893aa09553da88171307a42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2
Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/386596
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17104
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add the eve board files using kabylake and FSP 2.0.
BUG=chrome-os-partner:58666
TEST=build and boot on eve board
Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
This was tested at the coreboot meeting in Berlin.
The uart programming may still not be right but when used with
the lowrisc bitstream for the board we were able to load
and start linux, although it does not yet get far due to
PTE version issues with lowrisc.
Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17132
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This patch updates the _ART table with other external sensor
TSR0 for Fan speed control on Skylake-U based Kunimitsu and
Lars boards.
Also, updates the temperature values in DPTF policy for
better performance.
BUG=chrome-os-partner:51025
BRANCH=firmware-glados-7820.B
TEST=Built and booted on kunimitsu and lars EVT boards.
Verified this updated _ART table on these boards with
different workloads.
Change-Id: Ib195910c5eb00e004e8b9bd50e266ade3c175be2
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332349
Reviewed-on: https://review.coreboot.org/17066
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
In certain cases a board variant may need to override the NHLT
OEM strings in the main NHLT table. Therefore, provide that path.
BUG=chrome-os-partner:56918
Change-Id: I57cc4fd3665698e41ceebb1949180f86bb60b61f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17167
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Going forward GPIO_17 is used to determine the configuration of
the board w.r.t. the number of DMICs on the board.
BUG=chrome-os-partner:56918
Change-Id: I03edb880e0649977030c1b87219ebebac631a519
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17163
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In RS485 mode RTS line acts as a transceiver direction control.
The datasheet is not very clear about the polarity but register setting
here is tested to drive nRTS line high when transmitting.
Also note revision of B of the super-IO has errata and 8N1 setting does
not work properly, you would need revision C of the chip assembled to
fix this.
Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14998
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In anticipation of getting fixed material remove the disabling of
periodic training for MT53B512M32D2NP and MT53B256M32D1NP.
BUG=chrome-os-partner:59003
Change-Id: Iaadaa979d85cab78dda527db7480420af02fd832
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17130
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Explain the reasoning for the part_num strings used in the
memory SKU table explaining the necessity of keeping mosys
in sync with the strings used. It's possible that actual part
numbers could change as the higher speed material gets cheaper,
for example.
BUG=chrome-os-partner:58966
Change-Id: If895e52791dc56e283261b3438106116b8b2ea05
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17129
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
