As part of GPIO driver cleanup across qcom chipsets,
GPIO_OUTPUT_ENABLE has been renamed to GPIO_OUTPUT.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I51eedc722a91c5ea8e009fb8468a60667d374b49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Defining a macro for the gpio offset instead of a constant value.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Iefdde8f8331cf1df2e88a2c8915aefb4fa091d65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
For new MT8195 devices we will control mt6360 via EC,
so we have to add ec function of controlling MT6360 and
add CONFIG to separate them.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic2228f5b45173f0905ea66a3a1f00ec820e0f855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch sets the optimized FIVR configs for ehlcrb customized
based on the performance measurements to achieve the better power
savings in sleep states.
- Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5
states.
- Update the supported voltage states.
- Update max supported current, voltage transition time and RFI
spread spectrum.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the new definition of mt6360_regulator_id,
merge the MT6360 LDO and PMIC interfaces into one.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7ccc32cb0a9481d5f55349c152267a44fe09d20a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On MT8195 platforms with BC1.2, we have to use EC to control
MT6360 so the mt6360_regulator_id is redefined to match the
numbers defined in EC driver.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I9437edb9776442759ce04c31d315c3760078ffb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56434
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No reason to use the preprocessor for this.
BUG=none
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I920dfa2d27c2eb27e8bc50c615ccd13601610fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
These methods are oprom specific. Move them out of CBFS. I also deleted
the tohex methods and replaced them with snprintf.
BUG=b:179699789
TEST=Boot guybrush and see oprom still loads
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I03791f19c93fabfe62d9ecd4f9b4fad0e6a6146e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
New version of kconfig requires trailing slash at the end of
KCONFIG_SPLITCONFIG to indicate that it is a directory path.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I1a11eca21c4aa5a6260006c4ba2cb419eca8a802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As per the EDS revision 1.3 add support for I2C6 and I2C7.
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id918d55e48b91993af9de8381995917aef55edc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the variants can have different memory move the SPD related
content to the variant directory.
Change-Id: I38aa5e7514437bfcc61c38d64f0ba6f19350810d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56036
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we don't escape the $ then the actual $(obj) path will be written
into the .config file. With this change `$(obj)` is written into the
.config file. The Makefile then does:
PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
Since this is a recursive assignment the $(obj) will be expanded at that
point.
This change makes it easier to compare full .config files.
BUG=none
TEST=Build ezkinil
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic961df148d3f22585f3441d75c3f2454329c678a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This change allows preloading the payload.
BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We
now spend 7ms decompression from RAM. By switching to LZ4 we drop that
to 500us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
FILO allows to configure a line to autoboot. Hook this up into
coreboot’s build system.
TEST=Configure coreboot for QEMU i440fx with FILO as payload and
configure:
CONFIG_FILO_MASTER=y
CONFIG_FILO_USE_AUTOBOOT=y
CONFIG_FILO_AUTOBOOT_FILE="hda1:/vmlinuz root=/dev/sda1 console=tty0 console=ttyS0,115200 initrd=hda1:/initrd.img"
CONFIG_FILO_AUTOBOOT_DELAY=5
Boot Debian image with:
qemu-system-x86_64 -bios /dev/shm/coreboot/build/coreboot.rom -L /dev/shm -enable-kvm -smp cpus=2 -m 1G -hda /dev/shm/debian-32.img -serial stdio -net nic -net user,hostfwd=tcp::22222-:22
Change-Id: Id167e9a144bf466da87469108002672b299b702a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This method will allow the SoC code to start loading the payload before
it is required.
BUG=b:177909625
TEST=Boot guybrush and see read/decompress drop by 23 ms.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifa8f30a0f4f931ece803c2e8e022e4d33d3fe581
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This CL adds a method that can start the processes of reading the APOB
from SPI. It does require more RAM in ramstage since we no longer mmap
the buffer in the happy path. This will allow us to reduce our
boot time by ~10ms. The SoC code will need to be updated to call
start_apob_cache_read at a point where it makes sense.
BUG=b:179699789
TEST=With this and the patches above I can see a 10 ms reduction in
boot time on guybrush.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will cause a linker error if these methods are used outside
ramstage.
BUG=b:179699789
TEST=compile guybrush w/ and w/o COOP_MULTITASKING
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9983fca939c8a15fa570481bfe016a388458830
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56352
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If a thread wants to block a state transition it can use
thread_run_until. Otherwise just let the thread run. `thread_join` can
be used to block on the thread. Boot states are also a ramstage concept.
If we want to use this API in any other stage, we need a way of starting
a thread without talking about stages.
BUG=b:179699789
TEST=verify thread_run no longer blocks the current state
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3e5b0aed70385ddcd23ffcf7b063f8ccb547fc05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56351
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The thread_handle can be used to wait for a thread to exit. I also added
a return value to the thread function that will be stored on the handle
after it completes. This makes it easy for the callers to check if the
thread completed successfully or had an error. The thread_join
method uses the handle to block until the thread completes.
BUG=b:179699789
TEST=See thread_handle state update and see error code set correctly.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56229
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no telling when the next udelay will be, so explicitly call
`thread_yield()` after completing a transaction. This will allow any
pending transactions to immediately start.
BUG=b:179699789
TEST=Verify new transaction is enqueued right after another.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56321
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Once we enable COOP_MULTITASKING, we need to guarantee that we don't
have multiple threads trying to access the DMA hardware.
BUG=b:179699789
TEST=Boot guybrush with APOB patches.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56231
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need a way to protect shared resources. Since we are using
cooperative multitasking the mutex implementation is pretty trivial.
BUG=b:179699789
TEST=Verify thread lock and unlock.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56230
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switching threads while holding a spinlock can lead to a deadlock. This
happens if you have two thread trying to print to the serial console
because the uart code uses udelay.
BUG=b:179699789
TEST=Boot guybrush and no longer see a deadlock when printing to
console from a second thread.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1b929070b7f175965d4f37be693462fef26be052
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Renaming them to thread_coop_disable()/thread_coop_enable() makes them
sound like a pair.
BUG=b:179699789
TEST=Boot guybrush to OS
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d70c18965f53e733e871ca03107270612efa4fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56357
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows nesting critical sections, and frees the caller from
having to keep track of whether the thread has coop enabled.
BUG=b:179699789
TEST=Boot guybrush with SPI DMA
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I325ab6181b17c5c084ca1e2c181b4df235020557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56350
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
idle_thread_init was actually configuring the BSP thread at the end.
We can instead do this in threads_initialize. This now lets us set
initialized after the idle thread has been set up.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f1d6afac3b0622612565b37c61fbd2cd2481552
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56356
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This helper method is just a shorthand for
`thread_yield_microseconds(0)`. I think it makes it clear that we want
to yield a thread without delaying.
BUG=b:179699789
TEST=build test
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id8b60c35b183cff6871d7ba70b36eb33b136c735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56349
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.
There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.
BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU
definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify
that that is the one for Cezanne.
BUG=b:193888172
Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI
ID, so we need to implement map_oprom_vendev for the SoC.
BUG=b:193888172
Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Define new configs for Opregion versions.
2. Assign RVDA to relative address of the Opregion buffer
in case of opregion 2.1+.
BUG=b:190019970
BRANCH=None
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Elkhart Lake provides option to configure FIVR (Fully Integrated
Voltage Regulators) via parameters in FSP-S.
This CL removes fixed FIVR config values and expose these parameters
to the devicetree so that they can be configured on mainboard level
as needed.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add new ram_id:1000 for memory part MT40A1G16RC-062E:B.
BUG=b:193732051
TEST=Generate new spd file and build coreboot.
Then boot from the DUT with new memory MT40A1G16RC-062E:B
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56328
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is
enableda on the system.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon
if not updated.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a1f60fda7575212bb694fc423bd229452515903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Ravi Kumar Bokka