The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.
BRANCH=none
BUG=chrome-os-partner:48292
TEST=Build and boot on lars
Change-Id: I28fbbd690ca6efb539422e9ba02f10e07cd35346
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d229ba9d8934dcb5f22b27ce0ad27601ec87d6ff
Original-Change-Id: I64f2497a6bb3a50b0f58c67e2ab6751c4836fd89
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317130
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0
(default) disables Heci1 and hides the device from OS. It internally uses
the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb
device in the devicetree which is necessary for hiding and unhiding the
device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu.
CQ-DEPEND=CL:*238451
Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05
Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311913
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12977
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
- Split the script up to make it easier to update and read.
- Check for multiple different license strings. Not all files are GPL
licensed.
- Don't validate 0 length files
- Update list of files to exclude from the license header check.
- Add command line option to set directories to check
- Add stable version to check a few directories that are fixed. This
just calls the non-stable version with the directories to check.
Change-Id: I90d4e93a20b4e1638ce4f43f8acbee72dc588625
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12909
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.
Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This fixes some nits that were pointed out in a previous review, and
adds a couple additional comments to explain what is happening.
Change-Id: I1ca4bf59ba79744f79fbe73f4e226feeea1cc2ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13019
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These were copied from the linux kernel, so get the standard corboot GPL
v2 header.
Change-Id: I27ef3326cc42b7e005f94c8b4fd355012a89561d
Signed-off-by: Damien Roth <yves.r.roth@gmail.com>
Reviewed-on: https://review.coreboot.org/13023
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These files are original to coreboot and get the standard
coreboot GPL header.
Change-Id: I19565b0d2424a6f37a95ab4d7b16742d23122d1e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12919
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Most of these files are original to coreboot and get the standard
coreboot GPL header.
encoding.h and atomic.h are from the riscv codebase and have their
license.
Change-Id: I32506b0ecf88be2f5794dc1e312a6cd9b2a271ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12906
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Check that selected symbols are type bool
- Check that selected symbols aren't created inside a choice
- Check that symbols created inside a choice aren't created
outside of a choice as well.
Change-Id: I08963d637f8bdfb2413cfe831eafdc974d7674ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12969
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This was breaking the build on OS X, but also wasn't working correctly
under linux anymore either. It wouldn't print the illegal symbols
when it failed.
- Split the generation of the offenders file from the actual check for
offending symbols and just send all output to /dev/null.
- Rewrite the check for offending symbols in a way that works with OS X.
Tested by adding a global variable to romstage and verifying the
failure is shown correctly. Verified that it works correctly with no
illegal variables.
Change-Id: I5b3ac32448851884d78c3b3449508ffe014119ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13018
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch power gates the Kepler module
on skylake kunimitsu board. This is required
to save power since this is consuming over 500mw
of power in all active use cases.
The device can be powered on later by using the
kernel driver as required by setting the
kepler enable gpio high.
BRANCH=None
BUG=chrome-os-partner:45962
TEST=Build and Boot Kunimitsu and check lspci.
The Kepler device should not be listed.
Also power measurement of board should give
approximately 300mW of reduction in power.
Change-Id: I244a23385e20ef1431dc895536c8a47e1f5770d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8d4fb7d01f32ac307a351c307b8461628c0e5414
Original-Change-Id: Idafa74d7ff14d67a5b1e635f783efd84b5a7399c
Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302277
Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12964
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.
BUG=chrome-os-partner:46335
BRANCH=none
TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0)
Change-Id: I311cc7d2e70cc52a7e90f3c3c60d422b7b998789
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad9450c342c752f87e3385a2acd5dd79b65cc75f
Original-Change-Id: Ib7b1b40c296fce80d5366bd19e7ff20d7161db95
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316287
Original-Commit-Ready: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12963
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
kunimitsu mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
Kunimitsu does support two audio codec, ADI and MAXIM,
hence use AUDIO_DB_ID to read correct codec and craete
NHLT table, this will also help to load only one amplifier ASL
for machine driver consumption.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted kunimitsu board. Audio worked
with both ADI and MAXIM audio card.
CQ-DEPEND=CL:316352
Change-Id: Ic9b9af83a0229fdf5f1cb019245ae65ad9d2f06c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2db85062d65c5e831da297588aa4abb18d6ed1bb
Original-Change-Id: I3b08f3f23b334799a81cde81a30d6f231cc8583f
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315450
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12959
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds support for disabling the heci1 device
at the end of boot sequence. Prior to this, FSP would have
sent the end of post message to ME and initiated the d0i3 bit.
This uses the Psf unlock policy and the p2sb device to disable
the heci1 device, then lock the configuration and hide the device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu or glados board. set the hecienabled policy
to 0 and check for heci 1 device status in kernel lspci.
CQ-DEPEND=CL:*238451
Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358
Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311912
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12976
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
CB used to clear recovery status towards romstage end after FSP
memory init. Later inside FSP silicon init due to HSIO CRC mismatch
it will request for an additional reset.On next boot system resume
in dev mode rather than recovery because lost its original state
due to FSP silicon init reset.
Hence an additional 1 reset require to identify original state.
With this patch, we will get future platform reset info during romstage
and restore back recovery request flag so, in next boot CB can maintain
its original status and avoid 1 extra reboot.
BUG=chrome-os-partner:43517
BRANCH=none
TEST= build and booted Kunimitsu and tested RO mode
Change-Id: Ibf86ff2b140cd9ad259eb39987d78177535cd975
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 40ddc21a97b318510116b7d5c4314380778a40f7
Original-Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302257
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12975
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.
BUG=none
BRANCH=none
TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0)
Change-Id: I761d623d1064b8030f2703500d174259bb20ca79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f7bdb1091b7dd62a3c0b4a2272ab9f56fd7acc9
Original-Change-Id: Id1a867980d2e28a1f328aa36bed3c846b2137bec
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317471
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12974
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
At S0, S0ix and S3 LPC LAD signals are
floated at 400~500mV.
BRANCH=none
BUG=chrome-os-partner:48331
TEST=Build and boot on lars
Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38
Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317071
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12965
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Count DIMMs on current memory channel instead of all memory channels.
The current code is only able to correctly handle the following memory
configurations:
One DIMM installed in either channel.
Four DIMMs installed, two in each channel.
Two DIMMs installed, both in the same channel.
For systems that have any other configuration the DRAM On-Die-Termination
setting is wrong.
For example:
Two DIMMs installed, one in each channel.
Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
Change-Id: I0e8e1a47a2c33a326926c6aac1ec4d8ffaf57bb6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register
BRANCH=none
BUG=none
TEST=Build and boot on lars
Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9
Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317080
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12962
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
lars mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted lars board.
Audio worked with MAXIM audio card.
Change-Id: I1b7836c685ebbe1498f3dbaa2eb64d5e0d4faabb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 401f1a7b23dca19712517ed1588e1390769d1271
Original-Change-Id: I6a937872a9e10d2c5ea15d5952d23e98416df092
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316092
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12961
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This corresponds with the changes that have already gone into the
soc/intel/skylake chip.h file and is needed to get skylake platforms
building again.
Change-Id: I15bfee4eff50d6632659953ec8f97a39d8810db3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13022
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I don't think the warning is valid, because we already verify
that num_channels is 2 or 4 as soon as we enter the function.
Adding the default case makes the compiler happy.
Fixes warning:
src/soc/intel/skylake/nhlt/dmic.c: In function 'nhlt_soc_add_dmic_array':
src/soc/intel/skylake/nhlt/dmic.c💯2: error: 'formats' may be used
uninitialized in this function [-Werror=maybe-uninitialized]
return nhlt_endpoint_add_formats(endp, formats, num_formats);
^
Change-Id: Idc22c8478ff666af8915d780d7553909c3163690
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Make sure the latest & greatest Intel targets actually
build in our build system.
intel/sklrvp is still failing for reasons unrelated to the rest
of the skylake boards. Leaving that disabled for now.
Change-Id: Ie784628a57257cea30e5e47074648198b884f6db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12857
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu
Change-Id: Ia523e7956c06c9f4a60e0a2296f771cc3c70bc25
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12a07eebfb8fa4ee8013fbbb12283a0b429cacfd
Original-Change-Id: I2be6c5b0114e4c7d8a7b9ceb59ee32f28f61769f
Original-Reviewed-on: https://chromium-review.googlesource.com/316717
Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12958
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Skylake Core boot should have configurable option to skip
PCH based SD 3.0 Controller from customer/reference design.
Addition to that no unused or unnecessary should list under
device view.
BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot Kunimitsu and LARs.
Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb
Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315420
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12946
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Even though the data32 variable was getting written by
pch_pcr_read(), GCC still flagged it as being used while
uninitialized and failed the build.
Note that pch_pcr_read() may only set 1 or 2 bytes of data32 in the
successful path, depending on the size of the read.
Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12860
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
I think these four methods should cover most operating systems,
with many supporting several of the methods.
If we don't find anything, we're not any worse off than we were before.
The big issue would be if we get an incorrect value.
Change-Id: I4a612d39e93173e9d6e0de892f5bebf716912b1a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12937
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested on Intel D510MO
Before this patch, I was unable to get the SATA controller into AHCI
mode. That is, I could never see PCI ID 8086:27c1 appearing on the bus.
With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1
Tested on X60 with AHCI enabled 8086:27c5 (AHCI mode for mobile ich7)
No regressions detected.
Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12923
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some more PCH Policy UPD Parameters are added in FSP.
Lockdown config moved from FSP to coreboot.
Removing settings in devicetree.cb which are zero.
BRANCH=none
BUG=none
TEST=Build and booted on kunimitsu, verified that CB is doing
the Lockdowns which were previously done by FSP.
CQ-DEPEND=CL:*237842, CL:310191
Change-Id: I3dcf3a5340f3c5ef2fece2de5390cde48db4d327
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8bdb35897b640d271adcaed266030367f060553
Original-Change-Id: Ia201672565c07b2e03d972b2718512cd4fcbb95c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310869
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12941
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Some MemoryInit UPD parameters have been moved to
SiliconInit in FSP 1.8.0. This patch has the respective
changes in coreboot for this.
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu
CQ-DEPEND=CL:*237423, CL:*237424
Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118
Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310191
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
GPIO ASL APIs to get GPIO Value.
Need such APIs to read GPIO config settings.
Example: Kunimitsu need to read AUDIO_DB GPIO
to identify codec select.
BUG=chrome-os-partner:44481
BRANCH=none
TEST=build and boot on Kunimitsu.
Change-Id: If56bb7b3eae08e1949d372850a6426dfde5aadd0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4983ba835a8da2baf578b035ae482755983c1ecb
Original-Change-Id: Ia40d86c8d4b14857fa8822677b3f7d393a35b677
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316352
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12956
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
DPTF may power off the system when it starts if the CPU temp is >90C.
Since TJmax is 100C set the critical threshold to just below that value.
BRANCH=none
BUG=none
TEST=Build and boot on lars.
Change-Id: I3abf946ae09c3c691480e468d0c1d74730dc6c06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c2230009edb840e88a20c2d8a87f942c09b6bf3
Original-Change-Id: Iee1a3596dbbe934f68637f012c02c078c3751eeb
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316102
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12955
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Disable kepler device, it is removed and was not used on proto anyway.
BUG=none
BRANCH=none
TEST=build and boot on lars proto
Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1
Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315950
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12950
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.
BUG=chrome-os-partner:48292
BRANCH=None
TEST=Boot with the write protect screw in place. Issue
crossystem wpsw_boot. It should show 1.
Change-Id: I3a333a4dcce31be9afe28cf11b127090cc7b9421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 462dd0229c2d3b81cd34bdd2e36bea844f58586c
Original-Change-Id: Ib7e0539845575b32322e243e89b81ffee077eb81
Original-Signed-off-by: Arindam Roy <arindam.roy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316009
Original-Commit-Ready: Arindam Roy <rarindam@gmail.com>
Original-Tested-by: Arindam Roy <rarindam@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12952
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.
BRANCH=none
BUG=none
TEST=Build and booted on lars.
Change-Id: Ic1313385e0aa1760b473a34c853a95c76257eecf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a47faee53e08da81602b485937621fd49eb2ddbf
Original-Change-Id: I7c91dcdc82525a6d2b706f8f504ba48601097ef7
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316370
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12953
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
modify the P/N in samsung K4E6E304EE-EGCF SPD from K4E6E304ED-EGCE to
K4E6E304EE-EGCF
BRANCH=none
BUG=chrome-os-partner:48299
TEST=build chell and use gooftool to probe and P/N match
Change-Id: Ie560e5c0d4b9a3cfb34c3856911930fb8159764e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dabe5eaa8abf54f4e4a5492062adca6ef9b4634d
Original-Change-Id: Ie8d44ac6032e5213928bfae2a2ac5877d4193d62
Original-Signed-off-by: Wisley <wisley.chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316100
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12951
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: Iaf910041453695b7125b254ca5d71e8ccbd0b02f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea77d326ba1c33b100c34066ed361a55dfa14ce3
Original-Change-Id: I5d93c3a7fa4cf68ba91f1398b4bd04504a28fef2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315520
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12948
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: I6e36c0a99a73cdcb2bf6ccfbfc886a594f989a39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b0383a93f054011dd7c18519ece4e6f1944366d
Original-Change-Id: I6f8bd15c72fa89756382af99bddb6cb6abe89905
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313794
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12939
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The use of a NHLT table is required to make audio work
on the skylake SoCs employing the internal DSP. The table
describes the audo endpoints (render vs capture) along with
their supported formats. These formats are not only dependent
on the audio peripheral but also hardware interfaces. As such
each format has an associated blob of DSP settings to make
the peripheral work. Lastly, each of these settings are provided
by Intel and need to be generated for each device's hardware
connection plus mode/format it supports. This patch does not
include the dsp setting blobs.
The current supported connections:
- digital mic array 2 channel
- digital mic array 4 channel
- Maxim 98357 amplifier
- ADI ssm4567
- NAU88L25 headset codec
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built glados. Speakers, headphones, and mic on camera decently
worked.
CQ-DEPEND=CL:*239598
Change-Id: If1a9be97573b9b160893944661790cac7df26fca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f5514e27811c500732de97e1cc7edeced2607e7
Original-Change-Id: Ib42e895f00e7605cb30ce24d9b8dd00bf68a7477
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313998
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12938
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Intel's SST (Smart Sound Technology) employs audio support
which may not consist of HDA. In order to define the topology
of the audio devices (mics, amps, codecs) connected to the
platform a NHLT specification was created to pass this
information from the firmware to the OS/userland.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Tested on glados. Audio does get emitted and some mic recording
works.
Change-Id: I8a9c2f4f76a0d129be44070f09d938c28a73fd27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2472af5793dcffd2607a7b95521ddd25b4be0e8c
Original-Change-Id: If469f99ed1a958364101078263afb27761236421
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312264
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12935
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
david