Commit Graph

1379 Commits

Author SHA1 Message Date
Marcello Sylvester Bauer a4266691e3 Linux/Linuxboot: share cmdline and initrd parser
Merge the command-line and initramfs parser from 'a linux payload'
and 'LinuxBoot'.

GOAL: merge 'a Linux payload' and 'LinuxBoot'

Change-Id: I2d2aef5d07453b98e115af6ee06318c690def785
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29510
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:01:20 +00:00
Richard Spiegel 509d99ca6b payloads/libpayload/drivers/storage: Get rid of void pointer math
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. In this particular
situation, dev->buf is already pointer to u8, and there's no need to convert
to void *.

BUG=b:118484178
TEST=Build libpayload.

Change-Id: Ib70b8ce11abc88c35be4092f097cfff385921f46
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16 09:42:34 +00:00
Richard Spiegel b93796d624 payloads/coreinfo/cbfs_module.c: Get rid of void pointer math
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.

BUG=b:118484178
TEST=Build coreinfo with original code, run objdump and saved output. Added
modifications, build coreinfo again, run objdump again, compared objdump
outputs.

Change-Id: I1bbdc9499d257c5051fd7a86ca8b5c68bbf2e81d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29344
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-06 01:46:47 +00:00
Marcello Sylvester Bauer 9d3b1b206c Linuxboot: remove initramfs path entry
Remove Linuxboot initramfs path entry in Kconfig.
Custom initramfs can and should be used with 'Linux payload'.

Change-Id: I648fb2e0383d20b0e4d50e416af637ea07d1efb4
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-05 20:57:38 +00:00
Marcello Sylvester Bauer 28e0cb4b23 Linuxboot: check go version
Check if the installed Golang version is >= 1.9.

Change-Id: I9fd74fa8dc5e906e8b54ff5afaf69609fe957960
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29445
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 20:56:50 +00:00
Marcello Sylvester Bauer 51f2f2eba1 LinuxBoot: use curl
Download the linux kernel tarball with curl.
Curl is already a dependency for coreboot.

Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-02 14:58:56 +00:00
Marcello Sylvester Bauer 78d29bff72 LinuxBoot/X86_64: Enable 8250 uart drivers
Enable 8250 uart drivers on default defconfig.

- makes it easier to debug. (qemu -nographic)
- Kernel size increases only by 20kB.

Change-Id: I8309ecf7afd74b3c4021effedcac47350b442173
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-02 14:58:05 +00:00
Marcello Sylvester Bauer 159656b661 LinuxBoot: fix custom defconfig override
The default ARCH defconfig should not override a custom defconfig.

Change-Id: I9de24497ef6296029c66a94124bc11a0bb4d0107
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-02 14:57:50 +00:00
Patrick Rudolph fa5c69ff85 libpayload: Fill reg_base for debugging purposes
Fill reg_base with physical register base address.

Tested on Lenovo T500.

Change-Id: If42135c8e10b70d5ac9626521abd9cca3cf40053
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18600
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23 06:24:47 +00:00
Elyes HAOUAS 0b5b44e004 libpayload/curses/PDCurses/doc/intro.txt: Remove unneeded whitespace
Change-Id: Ib5a0f193d54d1b6f2431f7b801678f2a983c7941
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28432
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18 17:17:35 +00:00
Wonkyu Kim af89f49b83 tianocore : Enable Serial Debug for UEFI payload Debug build
Change-Id: I29953250ca278d5b1977be3763359df5110f67c7
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/29004
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15 22:51:34 +00:00
Patrick Rudolph ac4819de70 libpayload: Always set pciaddr
For debugging purposes always set the pciaddr attribute.
Tested on Lenovo T500.

Change-Id: I83a0e7f7196ed251fa0becc4e56bef3ca68f20f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18599
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15 15:42:18 +00:00
Julius Werner f3aa6e9319 libpayload: arm64: Add GDB support
This patch adds remote GDB support for the arm64 architecture.

Change-Id: I2fa4dbca6c39f822f489a5e81bd052f53fda98a5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-12 20:17:48 +00:00
Julius Werner 1bfda7293a libpayload: gdb: Factor out gdb_handle_reentrant_exception() from arm32
The arm32 GDB architecture code contains a little hack that allows it to
(sort of) correctly deal with a reentrant exception triggered from
within the GDB stub. The main logic for this isn't really arm32 specific
and could be useful for other architectures as well, so factor it out
into a separate function.

Change-Id: I3c6db8cecf1e86bba23de6fd2ac9fdf0cf69d3c6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-12 20:17:40 +00:00
Julius Werner 5c0e72ff99 libpayload: arm64: Make exception handling closer to arm32
This patch reworks the arm64 exception handling to be more similar to
how it works on arm32. This includes a bunch of features like actually
saving and restoring more exception state in the exception_state
structure and supporting the same sort of partial reentrancy that is
useful for GDB. Since there's no instruction to directly load into or
store out of SP on arm64, we can't do quite the same thing where we use
that to read an exception_state_ptr variable right after exception entry
when no other register is available. But we can do something very
similar by (ab-)using the "high" stack pointer (SP_EL2) as a pointer to
the exception_state struct and providing a function to change it.

Change-Id: Ia16a1124be1824392a309ae1f4cb031547d184c1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-12 20:17:28 +00:00
Julius Werner ca52a25882 libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2
This patch adds the new, faster architectural register accessors to
libpayload that were already added to coreboot in CB:27881. It also
hardcodes the assumption that coreboot payloads run at EL2, which has
already been hardcoded in coreboot with CB:27880 (see rationale there).
This means we can drop all the read_current/write_current stuff which
added a lot of unnecessary helpers to check the current exception level.

This patch breaks payloads that used read_current/write_current
accessors, but it seems unlikely that many payloads deal with this stuff
anyway, and it should be a trivial fix (just replace them with the
respective _el2 versions).

Also add accessors for a couple of more registers that are required to
enable debug mode while I'm here.

Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2018-10-12 20:14:54 +00:00
Piotr Król 3c60375c57 payloads/tianocore: Fix not applying patch 06_CorebootPayloadPkg_keep_cb_table
Mentioned patch could not be applied in coreboot-sdk:1.52. With this fix
patch apply correctly.

Change-Id: I130856520f91bcfbd9a62741b1d5abb6495a6eac
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-11 01:20:06 +00:00
Philipp Hug 56dceb2e1a payloads: Only show supported payloads in menuconfig
Some payloads don't depend on their supported platforms, which makes
them visible in menuconfig even if they are not supported (yet).

Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-09 11:29:52 +00:00
Patrick Rudolph eec0d9b8dc LinuxBoot/arm64: Remove firmware from defconfig
The extra firmware is not part of upstream kernel.
Fixes build error if the firmware is not present.

Change-Id: Ifbcb0bb0e2edf3aa260b40dfa339812019f9f0b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-05 03:27:39 +00:00
Raul E Rangel 59e923d757 libpayload/x86/exception: Add ability to ignore unknown interrupts
This will make enabling the APIC safer by ignoring unknown interrupts
and not halting the system. Once all interrupt sources have been found
and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired.

BUG=b:116777191
TEST=Booted grunt, halted the kernel, and pushed the power button while
in S5. Verified that depthcharge logged the unknown exception.

APIC Init Started
APIC Configured
Ignoring interrupt vector 39

Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:25:17 +00:00
Raul E Rangel 44d89f526d libpayload/x86/exception.c: Remove exception_install_hook
Not used by x86 code anymore.

BUG=b:116777191
TEST=Validated that depthcharge can be built.

Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:24:54 +00:00
Raul E Rangel ad37763a5f libpayload/apic: Register a spurious interrupt vector
We should have a spurious interrupt vector just incase we get one. The
handler doesn't need to do anything.

BUG=b:116777191
TEST=Booted depthcharge on grunt and inspected the register. I can't
generate a spurious interrupt, so I can't validate that the handler gets
called.

Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:24:44 +00:00
Raul E Rangel b025de0ddb libpayload/apic: Only ACK interrupts triggered by the APIC
Only set end of interrupt (EOI) when the APIC In-Service vector matches
the interrupt vector. This makes it so we don't EOI a non APIC
interrupt.

BUG=b:116777191
TEST=Booted grunt with APIC enabled and verified depthcharge still
works.

Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:24:20 +00:00
Patrick Rudolph 1fea734e54 libpayload/drivers/usb: Fix leaks
Don't leak buffers on device detach.

Tested on qemu using:
qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \
 -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \
 -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd

Change-Id: Ib2d80dd4590aa0dacdf2da3b614c6505c931d0be
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/23689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-01 16:58:29 +00:00
Patrick Rudolph d5a70bdfd5 libpayload/drivers/usb: Fix broken retry counter
Exit on first sucessful CONTROL transfer instead of doing
GET_DESCRIPTOR_TRIES iterations.

Tested on qemu using:
qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \
 -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \
 -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd

Change-Id: I7c881c08d94636a43223338e46c876b5f3e27d47
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/23688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-01 16:54:55 +00:00
Piotr Król 80346d0490 payloads/tianocore: ignore whitespace change when applying patches
This change is required to apply patch
06_CorebootPayloadPkg_keep_cb_table since conflict in white space
between patch and target file in edk2 makes patch rejected while
building under coreboot-sdk:1.52.

Change-Id: I38f7d46925cc00a2b5c5400e3fbf3579990f3fa5
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-28 09:52:27 +00:00
Patrick Georgi 5b2a2d008f src/*: normalize Google copyright headers
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."

While at it, also ensure consistency in the LLC variants (exactly one
trailing period).

"Google Inc" does not need to be touched, so leave them alone.

Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-28 07:13:00 +00:00
Andrea Barberio 256dd1198c payloads/Kconfig: do not show compression menu for FIT
FIT payloads do not support compression. Currently this would thrown an error
like the following:

E: FIT images don't support whole-image compression, compress the kernel component instead!

With this patch, menuconfig will correctly *not* show payload compression for
FIT payloads, and this will correctly set compression to NONE.

Change-Id: If564e2f5c0d499bc30411d7bd41611790453d4ef
Signed-off-by: Andrea Barberio <insomniac@slackware.it>
Reviewed-on: https://review.coreboot.org/28732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-26 15:38:58 +00:00
Martin Roth f2c3d8076e payloads/external: Add yabits payload
Yabits (Yet another UEFI bootloader) is designed to be a slim and quick
alternative to Tianocore.  It is still under heavy development.

https://web.archive.org/web/https://yabits.github.io/

Change-Id: I132970e952c605c73cfe33dc47f20170ae8aa899
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/28590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-16 13:10:17 +00:00
Ronald G. Minnich 95c331b94b rampayload: Add the linuxcheck payload
The i386.c file uses standard 3f8 UART for some simple diagnostic
prints, and the libpayload console otherwise.

This payload was used to debug Linux as a rampayload and was very helpful
for that work.

Change-Id: I1cce5528780cd825fd91a88137fa70abd9f218e7
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28600
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14 09:59:17 +00:00
Lijian Zhao cf9ea55473 payloads/tianocore: Add option to use 8254 timer
Change TianoCore payload default to use HPET timer. Add an option to use
8254 timer for legacy platform support.

BUG=N/A.
TEST=Build and boot up into UEFI shell on Whiskey Lake rvp platform.

Change-Id: I857704b0ca128fc9da193ae26a33c7cf89ad7320
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-09-13 16:43:36 +00:00
Raul E Rangel 9fc7b8e973 libpayload/x86/delay: Make arch_ndelay call apic_delay if delay is long
This reduces power consumption on grunt by over 3W when sitting at the
depthcharge recovery screen.

BUG=b:109749762
TEST=Booted grunt in the recovery screen and made sure it continued to
work.

Change-Id: Id079c099ee4cf6a07724241af4400063f4551668
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28245
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Julius Werner <jwerner@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 14:15:48 +00:00
Raul E Rangel 370c116ca5 libpayload/x86/delay: Add an x86 arch_ndelay
This method has a pause instruction to help the CPU relax a little bit.
Measuring grunt it saves about 80mW.

BUG=b:109749762
TEST=Made sure that grunt boots.

Change-Id: I045a941ed42fcc4f2dbdd65b5cbb42d84813f50c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 14:15:25 +00:00
Raul E Rangel d63627fb84 libpayload/libc/time: Add an arch_ndelay()
Replace _delay with an arch_ndelay(). This way each arch can setup their
own delay mechanism.

BUG=b:109749762
TEST=Verified delay's still work on grunt.

Change-Id: I552eb30984f9c21e92dffc9d7b36873e9e2e4ac5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28243
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 14:15:18 +00:00
Raul E Rangel 24ae85c3ff libpayload/x86/apic: Add an apic_delay method and calibrate the timer
The apic_delay method will halt the CPU and wait for a timer interrupt
to fire. I went with usec because nsec is too granular to guarantee.

This method will be called from an arch_ndelay() method when the delay
is large enough to justify a sleep.

BUG=b:109749762
TEST=Tested it on grunt by changing the _delay method to call
apic_delay().

Change-Id: I80363f06bdb22d0907f895885e607fde1c4c468d
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12 14:15:11 +00:00
Raul E Rangel ac8ebd0e73 libpayload/arch/x86: Add support for initializing the APIC
This is just the bare minimum required to initialize the APIC. I only
support xAPIC and chose not to support x2APIC. We can add that
functionality later when it's required.

I also made the exception dispatcher call apic_eoi so that the callbacks
won't forget to call it.

BUG=b:109749762
TEST=Booted grunt and verified that depthcharge continued to function
and that linux booted correctly. Also verified GDB still works.

Change-Id: I420a4eadae84df088525e727b481089ef615183f
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12 14:14:46 +00:00
Raul E Rangel f47ccbdd47 libpayload/x86/gdb: Migrate to use set_interrupt_handler
BUG=b:109749762
TEST=Verified GDB still functions by hitting Ctrl+G on the developer
screen and stepping through some code.

Change-Id: I723a8a95f681c500d9d8e35e49fd1d893cb1f133
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10 15:01:19 +00:00
Raul E Rangel 80d5c19590 libpayload/x86/exception: Add ability to handle user defined interrupts
I need to setup the APIC timer to fire interrupts. I would like to reuse
the existing interrupt table. So I extended it to support user defined
interrupts. I just added all 255 vectors so there wouldn't need to be
any additional build time configuration.

I'm going to deprecate exception_install_hook and remove it in a follow
up. It will be replaced with set_interrupt_handler. This way the
exception lookup does not have to manage a list of callbacks, or have to
worry about the order they are processed.

BUG=b:109749762
TEST=Wrote an interrupt handler and fired an APIC timer interrupt and
verified that vector 32 was returned.

Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10 15:01:04 +00:00
Martin Roth 87282737a8 payloads: Remove/fix trailing whitespace
Change-Id: Idfc54ca0ed53f52ddad61114ec6b05d94dd746c1
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-04 12:38:40 +00:00
Philipp Deppenwiese 9569ebeab8 payloads/LinuxBoot: Fix remaining issues
* Update kernel versions
* Fix initrd path handling

Change-Id: Ia0641fd0c0db1e47ee4829b73871af662d4a6370
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-09-04 12:36:43 +00:00
Raul E Rangel cf79c8344d libpayload/x86/exception: Add methods to enable/disable interrupts
Will be used by the APIC.

BUG=b:109749762
TEST=Verified by the other cls in the stack.

Change-Id: Id86f2719d98a90318ac625e09601e5dbb06e3765
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-23 16:24:44 +00:00
Raul E Rangel 052b5317da libpayload/x86/cpuid: Add a cpuid macro
Since libpayload doesn't link against libgcc we need to define our own
cpuid macro. I didn't add any error checking since anything in the last
decade should support cpuid.

BUG=b:109749762
TEST=called it and made sure the correct flags were returned.

Change-Id: Id09878ac80c74416d0abca83e217516a9c1afeff
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-23 16:24:38 +00:00
Stefan Tauner a07366c9f9 payloads/external/Memtest86Plus: allow for selecting a specific revision
Because the Kconfig configuration files for primary payloads are
already sourced via a wildcard pattern this change requires to
use another file name pattern.

Change-Id: I83b89f5e14618e8a487ebb044fcdd3c175662591
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22 15:34:35 +00:00
Joel Kitching 44cff7a897 cbtable: remove chromeos_acpi from cbtable
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.

BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725

Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-22 15:33:50 +00:00
Joel Kitching 75b1f768d8 cbmem: rename vdat to chromeos_acpi
There is a confusingly named section in cbmem called vdat.
This section holds a data structure called chromeos_acpi_t,
which exposes some system information to the Chrome OS
userland utility crossystem.

Within the chromeos_acpi_t structure, there is a member
called vdat.  This (currently) holds a VbSharedDataHeader.

Rename the outer vdat to chromeos_acpi to make its purpose
clear, and prevent the bizarreness of being able to access
vdat->vdat.

Additionally, disallow external references to the
chromeos_acpi data structure in gnvs.c.

BUG=b:112288216
TEST=emerge-eve coreboot, run on eve
CQ-DEPEND=CL:1164722

Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/27888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-14 14:48:44 +00:00
David Hendricks fb03dd6043 linuxboot: remove curley brace expansion from u-root commands
Curley brace expansion is a bash-ism, so we can't use it for the
u-root command list.

This unfortunately also breaks the current Kconfig option since the
list needs to be separated by space instead of commas.

Change-Id: I429a52c1673e29b7180ee6f53deaa7a551a1a9b3
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-10 09:05:04 +00:00
Raul E Rangel 8346a44dd1 libpayload/drivers/usb/xhci: Replace raw values with constants
BUG=none
TEST=compiled on grunt and made sure USB still works in depthcharge

Change-Id: I972f4604bb5ff3838cb15f323c5a579ad890ecf5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08 21:57:22 +00:00
Piotr Król bb95731dad payloads/external/SeaBIOS: add support for sercon port
Change-Id: Id2d2ed0fa97f2cef5818a8508bb8ee3ddba73647
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/26060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-06 14:16:17 +00:00
Raul E Rangel a8b4b75d24 exception: Fix segment error code mask
The segment error descriptor is actually 13 bits long.

BUG=b:109749762
TEST=Verified by causing a segment error

Change-Id: I3439f9ce1e8cf0c472c4eb82d74a787718c9609f
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06 07:56:00 +00:00
Philipp Deppenwiese 781693f211 payload/LinuxBoot: Fix compilation and clean target
* Update kernel version
* Add kernel directory removal during clean target
* Add x86 and x86_64 default configs

Change-Id: I6793bffd2c537a0e9fe7c07abbea99b28defb52e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27745
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31 12:46:21 +00:00