Commit Graph

26780 Commits

Author SHA1 Message Date
Angel Pons 7ec15c82f4 util: Fix shebang for python2 scripts
Python 3 is the default Python interpreter on most modern systems.
Python 2 scripts must specify they should be run with Python 2 in their
shebang. Solves issue raised in CB:28953.

Change-Id: I9ace4afd668539c05e7ace30e255af50c7a069c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-18 09:12:22 +00:00
Patrick Rudolph 5a61cc5d22 cpu/qemu-x86: Fix CPU driver
There's a typo in the cpu driver causing it to always use the weak
implementation defined in the devicetree instead of the real
implementation.

Tested on qemu-q35, the CPU driver contains valid values.

Change-Id: I4a6bb447bfdb3df6053c0df8be9d7c6aa8f689be
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/29675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-18 09:12:15 +00:00
Arthur Heymans 0115606286 mb/intel/dg43gt: Add documentation
Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-17 16:51:43 +00:00
Angel Pons e0e98eb11d src/mb/asus/p5qc/gpio.c: Allow specifying a gpio.c in Kconfig
Even though these two mainboards use the same gpio.c file, other boards
such as the p5ql_pro do not.

Change-Id: I2f7c8c12cb1bdcf47f3b4d4cef0b11e44a5b8863
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-17 15:28:36 +00:00
Patrick Georgi 68aed91eb9 intel/i945: Fix booting on a dual channel configuration
The register values in dram width programming changed in
commit a4fc7bef7f which broke booting on getac/p470.

TEST=getac/p470 with 2 X8DDS DRAM boots again

Change-Id: I8b3eedc8c5234e8a28948d4dc58bf565024f62ce
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
2018-11-17 13:27:43 +00:00
Subrata Banik 8ad5a62de9 soc/intel/icelake: Make static IRQ mapping for PIC mode
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.

Change-Id: I9693f2a52529961e6b611b69e389f01f77f77d63
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-17 09:37:19 +00:00
Subrata Banik 990db2213f soc/intel/icelake: Make static IRQ mapping for ICP PCH pci devices
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl

Also remove unused irqlinks.asl from soc/intel/icelake/acpi/

Change-Id: Idec00c3b8a97cb5aa7b4000840aba914aea478c9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-17 09:37:09 +00:00
Yegor Timoshenko c2e4941367 treewide: use /usr/bin/env where appropriate
Some Unix systems (GuixSD, NixOS) do not install programs like
Bash and Python to /usr/bin, and /usr/bin/env has to be used to
locate these instead.

Change-Id: I7546bcb881c532adc984577ecb0ee2ec4f2efe00
Signed-off-by: Yegor Timoshenko <yegortimoshenko@riseup.net>
Reviewed-on: https://review.coreboot.org/28953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-17 07:32:03 +00:00
Shelley Chen 15316e2321 mb/google/poppy/variants/nami: Invert FP MCU wake signal
GPP_D6 needs to be inverted to enter S0ix because FPMCU_INT_L is
active low.  Keeps device awake otherwise.

BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into
     S0ix in the EC console.

Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-17 07:30:15 +00:00
Duncan Laurie bf2710e849 mb/google/sarien: Set SMBIOS mainboard SKU
Setting sku_id() is not enough to get a value to show up in the SMBIOS
tables, it also needs to be returned as a string for the table creation
to consume.  This change defines the smbios_mainboard_sku() function
and returns a string constant of "sku#" as expected.

Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Trent Begin <tbegin@google.com>
2018-11-17 07:26:49 +00:00
Lijian Zhao 79152f3c81 soc/intel/cannonlake: Add options for pcie ltr
FSP can support enable/disable Pci express LTR (Latency Tolerance
Reporting) mechanism through upd interface. Include that into coreboot
side.

BUG=N/A
TEST=N/A

Change-Id: I69b423afa4f81a2d58375734bba07792e08931d5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29642
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-17 07:25:54 +00:00
Elyes HAOUAS 28114ae71b SMBIOS: Remove duplicated smbios_memory_type enum
Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-11-16 15:48:04 +00:00
Elyes HAOUAS 0acb28a9c0 {soc,sb}/amd: Remove unused SOUTHBRIDGE_AMD_*_SKIP_ISA_DMA_INIT
Change-Id: Ic9bca9a56663926a153b93c298f69ba7d26f6e5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16 14:25:10 +00:00
Vadim Bendebury 98485de881 util/cbsftool: allow enabling verbose make output
Sometimes it is necessary to be able to see exact command lines used
when compiling and linking. Use the same scheme as some other
Makefile's - enable verbose output when variable V is set to 1.

TEST=tried building cbfstool with V=1, observed verbose output.

Change-Id: Iff25439aabff79e69d1d94a2c51c60bb0e0d7b80
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/29431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 12:59:09 +00:00
Sumeet Pawnikar 36c1719143 mb/google/octopus/variants/bobba: Set tcc offset for bobba
Change tcc offset from 0 to 10 degree celsius for bobba.

BUG=b:118099582
TEST=Cross verified the value using TAT UI.

Change-Id: I68527c27635844f4edb0dda5f6018589d7bae297
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/29636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-16 12:56:50 +00:00
Nick Vaccaro 40b41826e1 mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST.

BUG=none
TEST=none

Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29540
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 12:32:20 +00:00
Elyes HAOUAS a5f5790c93 mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VAR
Change-Id: I6e911556abc7b7ac3573c5807b6453eecaff7e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-11-16 11:55:04 +00:00
Elyes HAOUAS 8a5283ab1b src: Remove unneeded include <cbmem.h>
Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29302
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:56:47 +00:00
Elyes HAOUAS 55d6238fa6 src: Remove unneeded include <cbfs.h>
Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29303
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:26:32 +00:00
Alex Thiessen 52fdc05013 util/gitconfig/test: Add commit-msg hook test
Add a test that, after cloning the repository to a temporary directory,
installs git hooks and attempts to do a good and a bad commit, expecting
the former to succeed and the latter to fail, thus testing the
`commit-msg` hook.

Change-Id: Icdaf0109c60cb5b6952b1a2468ab050a742e4201
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23281
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:08:48 +00:00
Nico Huber 9b1cbe040b util/docker: Rename _CONTAINER_VERSION => _IMAGE_TAG
This is so confusing, let's name it what it is ;)

Change-Id: I6f87e2f6912d886e241e03998fb4136fb28bc7b1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 10:06:09 +00:00
Nico Huber 9b731b5c08 util/docker: Use common .ccache for local builds
Bind a volume for .ccache to the `docker-run-local` targets. By default
the current user's $(HOME)/.ccache will be used, it can be overridden
via the DOCKER_CCACHE variable.

Also rearrange some docker parameters to keep the target readable.

Change-Id: I7d0bdb3861ac56361cacfa74aaf8b45c4f135e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 10:06:02 +00:00
Tristan Corrick 3693294112 mainboard: Add ASRock H81M-HDS
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9.

This board works quite well under coreboot. A list of what works and
what doesn't can be found in the documentation part of this commit.

The file `data.vbt` matches the VBT in the latest stable version of the
vendor firmware (version 2.20).

Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-16 10:05:26 +00:00
Tristan Corrick b2632cec0e sb/intel/lynxpoint: Generate the ACPI FADT with a common function
The function `acpi_fill_fadt()` is based on that of sb/intel/bd82x6x.

Tested on an ASRock H81M-HDS and a Google Peppy board, both using Linux
4.9 with `acpi=strict`. No ACPI errors or warnings appear in the kernel
log. System reset, poweroff, and S3 suspend/resume continue to work.

General improvements
--------------------

- `fadt->preferred_pm_profile` is set based on the value of
  `CONFIG_SYSTEM_TYPE_LAPTOP` instead of being hardcoded.

- Constants are used instead of magic values in more locations.

- `fadt->gpe0_blk`, `fadt->gpe0_blk_len`, and `fadt->x_gpe0_blk` are set
  appropriately depending on whether the system uses Lynx Point LP or
  not.

- Boards can indicate docking support in the FADT via the devicetree.

Changes to existing Lynx Point boards
-------------------------------------

- `header->asl_compiler_revision` changes from 1 to 0.

- `fadt->model` is left at 0 instead of being set to 1. This field is
  only needed for ACPI 1.0 compatibility.

- `fadt->flush_size` and `fadt->flush_stride` are set to 0. This is
  because their values are ignored, since `ACPI_FADT_WBINVD` is set in
  `fadt->flags`.

- `fadt->duty_offset` is set to 0 instead of 1. None of the existing
  boards indicate support for changing the processor duty cycle (as
  `fadt->duty_width` is set to 0), so `fadt->duty_offset` does not
  currently need to be set.

- Access sizes of registers are set.

- On mb/intel/baskingridge, the pmbase is now read using the common
  function `get_pmbase()` instead of `pci_read_config16(...)`.

- On mb/intel/baskingridge, the value of `fadt->x_gpe0_blk.bit_width`
  changes from 64 to 128. The correct value should be 128 (bits), to
  match `fadt->gpe0_blk_len`, which is set to 16 (bytes).

- On Lynx Point LP systems, the unused extended address
  `fadt->x_gpe0_blk` sets its address space ID to be consistent with
  other unused extended addresses. Such a change should not alter the
  interpretation of the registers as being unused. Why not set them all
  to zero? Simply because the existing practice, in both coreboot and
  some other vendors' firmware, has them set in such a case.

A diff of the FADT from a Google Peppy board is below:

--- pre/facp.dsl	2018-10-30 20:14:52.676570798 +1300
+++ post/facp.dsl	2018-10-30 20:15:06.904381436 +1300
@@ -1,179 +1,179 @@
 /*
  * Intel ACPI Component Architecture
  * AML/ASL+ Disassembler version 20180810 (64-bit version)
  * Copyright (c) 2000 - 2018 Intel Corporation
  *
- * Disassembly of facp.dat, Tue Oct 30 20:14:52 2018
+ * Disassembly of facp.dat, Tue Oct 30 20:15:06 2018
  *
  * ACPI Data Table [FACP]
  *
  * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
  */

 [000h 0000   4]                    Signature : "FACP"    [Fixed ACPI Description Table (FADT)]
 [004h 0004   4]                 Table Length : 000000F4
 [008h 0008   1]                     Revision : 04
-[009h 0009   1]                     Checksum : 61
+[009h 0009   1]                     Checksum : 6E
 [00Ah 0010   6]                       Oem ID : "CORE  "
 [010h 0016   8]                 Oem Table ID : "COREBOOT"
 [018h 0024   4]                 Oem Revision : 00000000
 [01Ch 0028   4]              Asl Compiler ID : "CORE"
-[020h 0032   4]        Asl Compiler Revision : 00000001
+[020h 0032   4]        Asl Compiler Revision : 00000000

 [024h 0036   4]                 FACS Address : 7BF46240
 [028h 0040   4]                 DSDT Address : 7BF46280
-[02Ch 0044   1]                        Model : 01
+[02Ch 0044   1]                        Model : 00
 [02Dh 0045   1]                   PM Profile : 02 [Mobile]
 [02Eh 0046   2]                SCI Interrupt : 0009
 [030h 0048   4]             SMI Command Port : 000000B2
 [034h 0052   1]            ACPI Enable Value : E1
 [035h 0053   1]           ACPI Disable Value : 1E
 [036h 0054   1]               S4BIOS Command : 00
 [037h 0055   1]              P-State Control : 00
 [038h 0056   4]     PM1A Event Block Address : 00001000
 [03Ch 0060   4]     PM1B Event Block Address : 00000000
 [040h 0064   4]   PM1A Control Block Address : 00001004
 [044h 0068   4]   PM1B Control Block Address : 00000000
 [048h 0072   4]    PM2 Control Block Address : 00001050
 [04Ch 0076   4]       PM Timer Block Address : 00001008
 [050h 0080   4]           GPE0 Block Address : 00001080
 [054h 0084   4]           GPE1 Block Address : 00000000
 [058h 0088   1]       PM1 Event Block Length : 04
 [059h 0089   1]     PM1 Control Block Length : 02
 [05Ah 0090   1]     PM2 Control Block Length : 01
 [05Bh 0091   1]        PM Timer Block Length : 04
 [05Ch 0092   1]            GPE0 Block Length : 20
 [05Dh 0093   1]            GPE1 Block Length : 00
 [05Eh 0094   1]             GPE1 Base Offset : 00
 [05Fh 0095   1]                 _CST Support : 00
 [060h 0096   2]                   C2 Latency : 0001
 [062h 0098   2]                   C3 Latency : 0057
-[064h 0100   2]               CPU Cache Size : 0400
-[066h 0102   2]           Cache Flush Stride : 0010
-[068h 0104   1]            Duty Cycle Offset : 01
+[064h 0100   2]               CPU Cache Size : 0000
+[066h 0102   2]           Cache Flush Stride : 0000
+[068h 0104   1]            Duty Cycle Offset : 00
 [069h 0105   1]             Duty Cycle Width : 00
 [06Ah 0106   1]          RTC Day Alarm Index : 0D
 [06Bh 0107   1]        RTC Month Alarm Index : 00
 [06Ch 0108   1]            RTC Century Index : 00
 [06Dh 0109   2]   Boot Flags (decoded below) : 0003
                Legacy Devices Supported (V2) : 1
             8042 Present on ports 60/64 (V2) : 1
                         VGA Not Present (V4) : 0
                       MSI Not Supported (V4) : 0
                 PCIe ASPM Not Supported (V4) : 0
                    CMOS RTC Not Present (V5) : 0
 [06Fh 0111   1]                     Reserved : 00
 [070h 0112   4]        Flags (decoded below) : 00008CAD
       WBINVD instruction is operational (V1) : 1
               WBINVD flushes all caches (V1) : 0
                     All CPUs support C1 (V1) : 1
                   C2 works on MP system (V1) : 1
             Control Method Power Button (V1) : 0
             Control Method Sleep Button (V1) : 1
         RTC wake not in fixed reg space (V1) : 0
             RTC can wake system from S4 (V1) : 1
                         32-bit PM Timer (V1) : 0
                       Docking Supported (V1) : 0
                Reset Register Supported (V2) : 1
                             Sealed Case (V3) : 1
                     Headless - No Video (V3) : 0
         Use native instr after SLP_TYPx (V3) : 0
               PCIEXP_WAK Bits Supported (V4) : 0
                      Use Platform Timer (V4) : 1
                RTC_STS valid on S4 wake (V4) : 0
                 Remote Power-on capable (V4) : 0
                  Use APIC Cluster Model (V4) : 0
      Use APIC Physical Destination Mode (V4) : 0
                        Hardware Reduced (V5) : 0
                       Low Power S0 Idle (V5) : 0

 [074h 0116  12]               Reset Register : [Generic Address Structure]
 [074h 0116   1]                     Space ID : 01 [SystemIO]
 [075h 0117   1]                    Bit Width : 08
 [076h 0118   1]                   Bit Offset : 00
-[077h 0119   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[077h 0119   1]         Encoded Access Width : 01 [Byte Access:8]
 [078h 0120   8]                      Address : 0000000000000CF9

 [080h 0128   1]         Value to cause reset : 06
 [081h 0129   2]    ARM Flags (decoded below) : 0000
                               PSCI Compliant : 0
                        Must use HVC for PSCI : 0

 [083h 0131   1]          FADT Minor Revision : 00
 [084h 0132   8]                 FACS Address : 000000007BF46240
 [08Ch 0140   8]                 DSDT Address : 000000007BF46280
 [094h 0148  12]             PM1A Event Block : [Generic Address Structure]
 [094h 0148   1]                     Space ID : 01 [SystemIO]
 [095h 0149   1]                    Bit Width : 20
 [096h 0150   1]                   Bit Offset : 00
-[097h 0151   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[097h 0151   1]         Encoded Access Width : 02 [Word Access:16]
 [098h 0152   8]                      Address : 0000000000001000

 [0A0h 0160  12]             PM1B Event Block : [Generic Address Structure]
 [0A0h 0160   1]                     Space ID : 01 [SystemIO]
 [0A1h 0161   1]                    Bit Width : 00
 [0A2h 0162   1]                   Bit Offset : 00
 [0A3h 0163   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0A4h 0164   8]                      Address : 0000000000000000

 [0ACh 0172  12]           PM1A Control Block : [Generic Address Structure]
 [0ACh 0172   1]                     Space ID : 01 [SystemIO]
 [0ADh 0173   1]                    Bit Width : 10
 [0AEh 0174   1]                   Bit Offset : 00
-[0AFh 0175   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[0AFh 0175   1]         Encoded Access Width : 02 [Word Access:16]
 [0B0h 0176   8]                      Address : 0000000000001004

 [0B8h 0184  12]           PM1B Control Block : [Generic Address Structure]
 [0B8h 0184   1]                     Space ID : 01 [SystemIO]
 [0B9h 0185   1]                    Bit Width : 00
 [0BAh 0186   1]                   Bit Offset : 00
 [0BBh 0187   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0BCh 0188   8]                      Address : 0000000000000000

 [0C4h 0196  12]            PM2 Control Block : [Generic Address Structure]
 [0C4h 0196   1]                     Space ID : 01 [SystemIO]
 [0C5h 0197   1]                    Bit Width : 08
 [0C6h 0198   1]                   Bit Offset : 00
-[0C7h 0199   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[0C7h 0199   1]         Encoded Access Width : 01 [Byte Access:8]
 [0C8h 0200   8]                      Address : 0000000000001050

 [0D0h 0208  12]               PM Timer Block : [Generic Address Structure]
 [0D0h 0208   1]                     Space ID : 01 [SystemIO]
 [0D1h 0209   1]                    Bit Width : 20
 [0D2h 0210   1]                   Bit Offset : 00
-[0D3h 0211   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[0D3h 0211   1]         Encoded Access Width : 03 [DWord Access:32]
 [0D4h 0212   8]                      Address : 0000000000001008

 [0DCh 0220  12]                   GPE0 Block : [Generic Address Structure]
-[0DCh 0220   1]                     Space ID : 00 [SystemMemory]
+[0DCh 0220   1]                     Space ID : 01 [SystemIO]
 [0DDh 0221   1]                    Bit Width : 00
 [0DEh 0222   1]                   Bit Offset : 00
 [0DFh 0223   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0E0h 0224   8]                      Address : 0000000000000000

 [0E8h 0232  12]                   GPE1 Block : [Generic Address Structure]
 [0E8h 0232   1]                     Space ID : 01 [SystemIO]
 [0E9h 0233   1]                    Bit Width : 00
 [0EAh 0234   1]                   Bit Offset : 00
 [0EBh 0235   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0ECh 0236   8]                      Address : 0000000000000000

Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29387
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:04:42 +00:00
Caveh Jalali 7696290004 mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz
With this change, coreboot thinks we're running at 1MHz:
	DW I2C bus 2 at 0xd1133000 (1000 KHz)

Elan eKT3644 IC Specification (trackpad) requires:
Low Time  larger than 500ns (61 * 8.3ns = 506ns).
High Time larger than 260ns (32 * 8.3ns = 265ns),
Data Hold_time larger than 0ns.
Start Condition Hold time larger than 250ns.
Rise/Fall time of less than 120ns.

HCNT controls both High Time and Start Condition Hold time.
LCNT controls Low Time.
SDA_HOLD controls Data Hold Time.

P2 Atlas "Rise time" is 90ns and "Fall time" is 32ns and tuned
using resistors on the board and must be considered when
adjusting any of the parameters since these times are all measured
at 30 or 70% of base and peak voltages (0v/1.8v).

The eKT3644 requirements are met with LCNT=69, HCNT=33, SDA_HOLD=20
which yields the SCL at around 950KHz - suboptimal but compliant.

Lower LCNT or HCNT results in "lost arbitration" errors or not complying
with eKT3644 requirements.

Verified by gaggery.tsai@intel.corp-partner.google.com.
Scope shots posted here:
https://b.corp.google.com/issues/78601949#comment177

BUG=b:78601949
BRANCH=none
TEST=Farzam provided test points on track pad for SCL/SDA/GND.
     Waveforms measured with oscilloscope and screen shots attached
     to bug (comment #177, #155, #100).
     Operate trackpad/touchscreen
     Review dmesg (kernel) output for correct speed, parameters, and
     no errors (e.g. "lost arbitration" or "host controller timeout")

Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Signed-off-by: Grant Grundler <grundler@chromium.org>
Tested-by: gaggery.tsai@intel.corp-partner.google.com
Tested-by: grundler@chromium.org
Reviewed-on: https://review.coreboot.org/29553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-11-16 10:02:37 +00:00
Lijian Zhao 80fde629cd mb/intel/whlrvp: Enable HDA controller driver
Enable HDA controller coreboot driver for Whiskey Lake RVP platform on
top of common code.

BUG=N/A
TEST=Build and boot up on whiskey lake rvp board, comfirm audio playback
is working.

Change-Id: I7daf1c741b92ff59b9cb4030d218e9c1054c4b79
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/28781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-11-16 10:02:08 +00:00
Marcello Sylvester Bauer a4266691e3 Linux/Linuxboot: share cmdline and initrd parser
Merge the command-line and initramfs parser from 'a linux payload'
and 'LinuxBoot'.

GOAL: merge 'a Linux payload' and 'LinuxBoot'

Change-Id: I2d2aef5d07453b98e115af6ee06318c690def785
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29510
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:01:20 +00:00
Elyes HAOUAS 9d917f67fe soc/intel/denverton_ns/Kconfig: Remove unused HSUART_FUNC
Change-Id: I1ec6f0687083c17314588c85af289b4b27c5441c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29598
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:00:00 +00:00
Elyes HAOUAS 134da98a51 amd/{nb/amdfam10,cpu/pi}/Kconfig: Remove unused symbols
Change-Id: I7019d70b7e6f8ae041a12d6bab83127e9e70868c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:59:29 +00:00
Elyes HAOUAS 88fa156544 soc/intel/common/Kconfig: Remove unused SOC_INTEL_COMMON_SMI
Change-Id: Ic4ea1d681d2677880b155713c34152ac0861146b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:58:45 +00:00
Elyes HAOUAS 16e136795a mb/intel/cougar_canyon2: Fix SMBIOS_ENCLOSURE_TYPE symbol
Change-Id: I9f4640ef040dc6a1d39ecb8b3378266e4dd5cec9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:57:53 +00:00
Elyes HAOUAS a6508a4510 soc/qualcomm/ipq{40xx,806x}/Kconfig: Remove unused MBN_ENCAPSULATION
Change-Id: I4cf5cd1d3bed7188590e4f143d8f14dc9e58b183
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16 09:57:08 +00:00
Elyes HAOUAS 316c9a36d8 soc/intel/{broadwell,skylake}: Remove unused SERIAL_CPU_INIT
Change-Id: I2296ab3c53a82ee990649e35e1370e1dd304e392
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:56:43 +00:00
Elyes HAOUAS 25c27b5595 mb/msi/ms9652_fam10: Remove unused VAR_MTRR_HOLE
Change-Id: Ibbc010c9550c0a50b1e913e198f9b575107572fb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:56:29 +00:00
Elyes HAOUAS 3cdf353323 mb/{google/cyan,intel/strago}: Remove unused DYNAMIC_VNN_SUPPORT
Change-Id: I4d0df30255d006c0399dde1b3ba8ee513d98dc0a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:55:43 +00:00
Elyes HAOUAS 4d25f96504 src/drivers/vpd: Remove unused VPD_DEBUG
Change-Id: Iba838309f8055d364c5f846ce29e628067d7b5f5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:55:09 +00:00
Elyes HAOUAS 414779db10 src/mainboard: Remove unused "HW_MEM_HOLE_SIZE_AUTO_INC"
Change-Id: I10e89de270a20dbd28647e8b0f8a2425c515b350
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16 09:54:06 +00:00
Peter Lemenkov 1c2ad45ec4 mb/{lenovo,roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macro
This macro is no longer used since commit dd2bc3f8 with Change-Id
I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite").

Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
2018-11-16 09:53:42 +00:00
Daisuke Nojiri 4e3cd74449 mb/google/kalista: Disable EC-EFS
Only input from the BJ port is wired to VSYS on Kalista. VBUS from
USB-C is for output only. In other words, Kalista is a source only
device from a USB/PD perspective.

This patch disables EC-EFS, which would be needed for the EC to jump
to RW to get PD power before the AP boots. Kalista will be always
supplied enough power to boot the AP through the BJ port.

CQ-DEPEND=CL:1330171
BUG=b:118386511
BRANCH=none
TEST=Boot Fizz. Verify normal boot, soft sync, recovery mode work.

Change-Id: Icd18662ae1e76f35eb9bcd521b1951aacc713252
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/29564
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 09:53:21 +00:00
Tristan Shieh ab1b83d5a4 mediatek: Refactor PMIC wrapper code among similar SoCs
Refactor PMIC wrapper code which will be reused among similar SoCs.
Move reusable code into the common folder.

BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot

Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16 09:51:54 +00:00
Matt DeVillier d3d0f07fd5 soc/intel/braswell: add vmx support via CPU_INTEL_COMMON
Braswell allready supported vmx, but offered no mechanism to unset it, nor
to set the lock bit required for Windows to recognize virtualization.
Enable this functionality by adding CPU_INTEL_COMMON config.

Test: build/boot Windows 10 on Braswell ChromeOS device, verify Windows shows
virtualization as enabled.

Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/29570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16 09:51:21 +00:00
Elyes HAOUAS f765d4f275 src: Remove unneeded include <lib.h>
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:50:51 +00:00
Elyes HAOUAS e9a0130879 src: Remove unneeded include <console/console.h>
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 09:50:29 +00:00
Elyes HAOUAS ead574ed02 src: Get rid of duplicated includes
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16 09:50:03 +00:00
Seunghwan Kim be11d9369b mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU only
GPP_D0 is NC in 1st SKU board design, so we should control GPP_D0
for only 2nd SKU.

BUG=none
BRANCH=poppy
TEST=emerge-nautilus coreboot

Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/29631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-16 09:49:36 +00:00
Nick Vaccaro 49abfca717 mb/google/poppy/variant/nocturne: Configure GPP_E1 for WLAN_WAKE_L
The GPP_E1 gpio was incorrectly being defined as a no-connect.
Configure GPP_E1 for the WLAN_WAKE_L signal as per the schematic.

BUG=b:119508897
TEST=Build and flash nocturne, boot nocturne and
 1) Verify nocturne can successfully suspend/resume from S3 and S0ix.
 2) Verify wake from wlan wakes device from S3 and S0ix.
    To do so,
    a) as root, execute "iw phy phy0 wowlan enable disconnect" on DUT
    b) connect DUT to mobile hotspot
    c) sleep device via "powerd_dbus_suspend"
    d) turn off hotspot, verify DUT wakes from S0ix
    e) enable hotspot again
    f) connect DUT to hotspot
    g) sleep DUT via "sudo echo mem > /sys/power/state"
    h) turn off hotspot, verify DUT wakes from S3

Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-16 09:49:08 +00:00
Elyes HAOUAS 1e8c9ad54f src: Remove unneeded include <pc80/keyboard.h>
Change-Id: I0dcdfb1fa782c7936a19de11adcf17387f49d9db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16 09:48:52 +00:00
Elyes HAOUAS b8a7f04267 sb/amd/cs5536: Remove unneeded include <cpu/x86/bist.h>
Change-Id: Ifae9d67bbba57b30ee9a2f31c448efcb27981c57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16 09:48:50 +00:00
Joel Kitching 21fdd89b0c cbfstool: add unprocessed flag for file exporting
Add an unprocessed flag (-U) which modifies how files are exported.
In the case of a compressed raw file, extract without decompressing.
In the case of a stage or payload, extract without decompressing or
converting to an ELF.

This can be useful for verifying the integrity of a stage or payload,
since converting to an ELF may not be a deterministic process on
different platforms or coreboot versions.

BUG=b:111577108
TEST=USE=cb_legacy_tianocore emerge-eve edk2 coreboot-utils chromeos-bootimage
     cd /build/eve/firmware
     /build/eve/usr/bin/cbfstool image.bin extract -r RW_LEGACY \
       -n payload -f /tmp/payload_1 -U
     START=$((16#`xxd -s 20 -l 4 -p tianocore.cbfs`))
     SIZE=$((16#`xxd -s 8 -l 4 -p tianocore.cbfs`))
     dd if=tianocore.cbfs skip=$START count=$SIZE bs=1 > /tmp/payload_2
     diff /tmp/payload_1 /tmp/payload_2
     rm /tmp/payload_1 /tmp/payload_2

Change-Id: I351d471d699daedd51adf4a860661877f25607e6
Signed-off-by: Joel Kitching <kitching@chromium.org>
Reviewed-on: https://review.coreboot.org/29616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16 09:47:35 +00:00
Werner Zeh 73bbcee932 fsp_broadwell_de: Switch to common SPI controller driver
The common SPI controller driver in src/southbridge/intel/common does
match the SPI controller included in the PCH of Broadwell-DE SoC. Switch
to the usage of this driver and delete the dedicated one for the FSP
based Broadwell-DE implementation.

TEST: Boot mc_bdx1 with SPI driver active in romstage

Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/29633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16 09:47:00 +00:00