Normally, selecting FSP_USE_REPO will select FSP_FULL_FD which then will
configure the proper paths for FSP_M_FILE and FSP_S_FILE. The override
in these two boards caused FSP_M_FILE and FSP_S_FILE being empty despite
ADD_FSP_BINARIES being selected by FSP_USE_REPO which is an invalid case
that needs to be avoided, so remove the board-level override of those
two options.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I20c8cebea8327d59f0f33d05b824a74bf2121f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The ADD_FSP_BINARIES override in the mainboard's Kconfig caused this
option to not be selected when FSP_USE_REPO is selected. Remove the
override to fix this problem. These two boards are the only ones in tree
that had an override for this option, so now the ADD_FSP_BINARIES option
is only defined in drivers/intel/fsp2_0/Kconfig.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23439f3134eef9460625addbff7efd64c5f65ae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This option is neither selected nor usable for the only remaining SoC
that uses this code, so drop the remaining parts. configure_hudson_uart
isn't called anywhere and isn't even compiled, since it's guarded by an
#if CONFIG(HUDSON_UART) block and the HUDSON_UART Kconfig option isn't
selected anywhere. Both the offsets used in the iomux_write8 calls and
the UART controller itself aren't listed in the BKDG #52740 Rev 3.05 for
the AMD Family 16h Models 30h-3Fh APUs which is the only SoC that uses
this code, so the code didn't even apply for this chip.
TEST=Timeless build for pcengines/apu2 results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3f462d1f83a0f1ba851329ebebb1f3263267fdc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This config selected ADD_FSP_BINARIES even though HAVE_INTEL_FSP_REPO is
only defined for Apollolake and not Geminilake that resides in the same
SoC directory and uses the same Kconfig file. This results in the paths
to the FSP binaries not being defined, in which case the
ADD_FSP_BINARIES option shouldn't be selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95123c4930b44a3b76c87768e130eb7359bbf625
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since the FSP binaries for Picasso are present in the amd_blobs repo,
select the ADD_FSP_BINARIES option if the Kconfig option to check out
that repo is set.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch ensures mp_run_on_all_aps() is passing 'MP_RUN_ON_ALL_CPUS'
macro rather hardcoding `0` while running `func` on all APs.
Change-Id: Icd34371c0d4349e1eefe945958eda957c4794707
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
EGPIO132 is the last documented GPIO on the GPIO controller in the NDA
version of the BKDG for AMD Family 16h Models 30h-3Fh Processors (#52740
Rev 3.06) which is the only SoC using this code, so define
SOC_GPIO_TOTAL_PINS as 133, since the internal GPIO numbers are
0-indexed. This definition will be needed the subsequent patch that'll
add the remote GPIO support to the common AMD GPIO code to make sure
that the compiler can optimize out the code path needed to support the
remote GPIO access which isn't available on this platform anyway.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I877d462c5e753c9bbb3461dbb10cde2adc2cb12c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown
transtion (S0->S3->S5), this will cause the device to boot again after
it has finished sequencing down to S5. Since S3 is not POR for ChromeOS
devices anymore, change this event to wake from S3 and S0ix to just
S0ix.
BUG=b:197039097
TEST=abuild
Change-Id: I91e5e0ab8301377817875b6fa9e3c0e1f96c1465
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add NixOS configurations for bootable live systems containing a set of
tools which might be useful for firmware development in general and for
working on coreboot.
There are two configurations provided. One for console-only and a
graphical one, which is mostly the same as the console image but it
comes with Gnome Shell as window manager and some graphical tools in
addition.
An image can be built using `build-console.sh`, respectively
`build-graphical.sh`. The resulting iso image can be found in
`result/iso/`.
The console image results in ~700MB, while the graphical one results in
~2GB.
Change-Id: Iaf49d198e99781434bd89d2a8a125a4988b77e1c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This patch updates debug message to specifically the case when SMBIOS
table 7 write would abort due to either `unknown` CPU or CPU `doesn't
have support for deterministic cache cpuid leaf`.
Change-Id: I288593b3f78ab858bf66c689e7cfb6ba2ff746d0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Don't attempt to fill the SMBIOS table if the CPU doesn't support
deterministic cache CPUID.
TEST=Able to fix the hang issue seen on ASRock E350M1 with commit hash
e2b5fee.
Change-Id: Id65dc963e235f7080370a32cf69bcc4bee94d28f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57306
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`cpu_get_cache_info_leaf()` function is responsible to report leaf
value for CPU that have support for deterministic cache cpuid. As per
available datasheets from AMD and Intel the supported CPUID leafs are
0x8000_001d for AMD and 0x04 for Intel. Hence, this CL skips returning
default leaf value as `0`.
TEST=Verified fixes: e2b5fee3b0 (arch/x86: smbios write 7 table using
deterministic cache functions) hang issue on ASRock E350M1.
Change-Id: Iee33b39298e7821ac5280d998172b58a70c8715b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57305
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are two different types of 682 SKU available with TDP
of 28W and 45W. This patch fix override values for power
limits for these 682 SKU. This patch also sets power limit
values dynamically based on machine ID and CPU TDP of SKU.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I796e56321ae9c8312530a4b8986cd73a2245f5fa
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57290
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
copy existing QSPI driver from /soc/qualcomm/sc7180 to common folder.
This common QSPI driver works in master mode and provides read/write
operation for the slave devices like flash.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I5b3816b823e14db1dd13f1eb4a6761c7a61604b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Introduce DDR One-Time-Training Support
Device reboots without training from second iteration
and also DDR training data is 32kb size, hence update
required in memlayout and to sync with upstream changes
the Fmap size even got bumped up.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
It supports the clock consumers for QUP, SDCC, PCIE, Display to be able
to configure & enable the desired clocks.
The clock driver also supports reset of subsystems like AOP and SHRM.
Also add support for Zonda PLL enable for CPU in common clock driver.
Refactor the SC7280 clock driver to use the common clock driver APIs.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get tdp value of CPU for different SKUs based on PKG POWER MSR.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I9fba0a64da2f1d79d633054dddd9fdf1d3d8e258
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Add GPIO IOMUX defines for the pins that are used in the mainboard code
which enables using the PAD_GPI and PAD_GPO macros.
TEST=Timeless build for APU2/3/4/5 results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
southbridge/amd/pi/hudson uses the common GPIO bank access code from
soc/amd, but doesn't provide all functionality that would be needed to
use the full functionality. Add a Kconfig option that switches off some
functionality in the common SoC GPIO access code, so that more of the
functionality proviced by the common SoC GPIO code can be used in the
AMD binaryPI chipset and board code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mapping of the package GPIO numbers to the GPIO numbers on the GPIO
controller isn't a 1:1 one, so add a comment about that to avoid
confusion. Also change the comment style to match the style guide.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie30bf5483ea2e2516d7e3fdd21ea9338362e526e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Also remove the unused amdblocks/acpimmio.h include in gpio_ftns.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: If121941c8a6ba88913653192740997aeef426548
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56784
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Override DdiPortAConfig as MIPI DSI
BUG=b:192521391
BRANCH=None
TEST=Built test coreboot image and boot on bugzzy board
Change-Id: If308f9d69fea56176527e7b67f36b29c43adb525
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Make adding the FSP-T file to CBFS depend on both ADD_FSP_BINARIES and
FSP_CAR Kconfig options being set. The FSP_T_FILE Kconfig option depends
on both, so also check if both are selected in the Makefile where it
tries to add the FSP-T to the CBFS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id347336f2751c6d871f31d89c30a1222037c2d69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The clock driver supports configuring the general purpose PLLs,
configuring the root clock generator (RCG), enable clock branch, enable
gdsc and also the block resets.
The common clock driver exposes PLL configuration functions and also
different Agera PLL enable functions for the CPU PLLs.
While at it, the common driver also supports reset of subsystems like
AOP and SHRM.
SC7180 clock driver is also refactored to use the common clock
driver APIs.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
As we move to use the common clock driver, the sc7180 clock driver,
watchdog and display drivers requires few cleanups, thus update the
impacted drivers.
Earlier the display client is expected to provide 2n divider value,
as the divider value in register is in form "2n-1".
mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0;
The older convention in the upcoming patches would be replaced with
the common macro of QCOM_CLOCK_DIV, thus need the divider needs to
be updated.
mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0;
To accommodate impacting the functionality, the half_divider is taken
care in the clock driver.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
CONFIG_DRIVERS_INTEL_MIPI_CAMERA and CONFIG_SOC_INTEL_COMMON_BLOCK_IPU
are getting selected for all ADLRVPs irrespective of ADL-P and ADL-M
(internal and external EC SKUs) hence, select those Kconfigs from
mainboard Kconfig rather Kconfig.name.
Also, select DRIVERS_INTEL_SOUNDWIRE as per alphabetical order.
TEST=No changes are seen while the .config file is getting auto
generated.
Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H.
Remove now-redundant mainboard code to set the `UserBd` UPD.
Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DIMM_MAX` Kconfig symbol once.
Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
variant_has_pcie_wwan() was always coming back as disabled because
find_dev_nested_path() couldn't find the device until the domain was
added to the array.
BUG=b:193036827
TEST=Boot guybrush with PCIe & USB WWAN devices.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Id94fa0b0ff5c29fa447e869220d27ccfe61438c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The RW_MRC_CACHE only needs to be 64K for Brya.
BUG=none
TEST="emerge-brya coreboot chromeos-bootimage", flash and boot
brya0 to kernel.
Change-Id: I74365b795e184b92f483ae2bf862791e235c5362
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56989
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for DSM methods as per the connectivity document
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:191720858
TEST=Check the generated SSDT tables for DSM methods
Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add support for the WTAS ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:193665559
TEST=Generated SAR file with the WTAS related configuration values and
verified that the SSDT has the WTAS ACPI table.
Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add support for the PPAG ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:193665559
TEST=Generated SAR file with the PPAG related configuration values and
verified that the SSDT has the PPAG ACPI table.
Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Existing SAR infrastructure supports only revision 0 of the SAR tables.
This patch modifies it to extend support for intel wifi 6 and wifi 6e
configurations as per the connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
The SAR table and WGDS configuration block sizes were static in the
legacy SAR file format. Following is the format of the new binary file.
+------------------------------------------------------------+
| Field | Size | Description |
+------------------------------------------------------------+
| Marker | 4 bytes | "$SAR" |
+------------------------------------------------------------+
| Version | 1 byte | Current version = 1 |
+------------------------------------------------------------+
| SAR table | 2 bytes | Offset of SAR table from start of |
| offset | | the header |
+------------------------------------------------------------+
| WGDS | 2 bytes | Offset of WGDS table from start of |
| offset | | the header |
+------------------------------------------------------------+
| Data | n bytes | Data for the different tables |
+------------------------------------------------------------+
This change supports both the legacy and the new format of SAR file
BUG=b:193665559
TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different
binaries generated by setting different versions in the config.star
Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
GPIO PM was disabled for brya to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. All devices currently tested on brya support 4us
long pulses. This change drops the GPIO PM override and re-enables
dynamic GPIO PM.
TEST=Boot brya to OS, ensure no TPM errors.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0c7b66b5514d8b80775ab7578ce7b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56926
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It doesn't make sense to store the orientation field directly in the
panel information structure, which is supposed to be reuseable between
different boards. The thing that determines orientation is how that
panel is built into the board in question, which only the board itself
can know. The same portrait panel could be rotated left to be used as
landscape in one board and rotated right to be used as landscape in
another. This patch moves the orientation field out of the panel
structure back into the mainboards to reflect this.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If2b716aa4dae036515730c12961fdd8a9ac34753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57324
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Windows will write to the century byte (0x32), causing the option table
checksum to be invalid and reset all options to their default values.
Move options and checksum to start after the century byte.
Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
It turns out that putting a device ref in an overridetree at a different
point in the tree will generate a duplicate device definition, such that
the change introducing this support was ignoring the device presence
specified by overridetree.cb and only using the baseboard configuration.
I believe testing of that change was not redone after the baseboard was
changed to disable the MST, so that conflicting behavior was not
noticed.
The incorrect behavior generated a disabled device for the MST at the
location specified by the baseboard, and one with the probe as a child
of the soc. At runtime this did a fw_config probe of the "I2C 00:4a"
device, and later probed a different "I2C 00:4a" which was already
disabled. As the disabled one came later, it seems to have completely
disabled the MST, discarding the results of the variant-specific probe.
BUG=b:185862297
TEST=10EC2141 device is now present on a Dali berknip
BRANCH=zork
Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57298
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Felix Held