Commit Graph

17 Commits

Author SHA1 Message Date
Patrick Rudolph fc1d50a365 Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled.
The very same code runs on some real devices and it runs in qemu
with KVM disabled.

The bugs are so strange that no root cause could be found yet.

Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-12 13:36:30 +00:00
Paul Menzel b9a5152cfa Documentation: Fix spelling of *assumptions*
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:06:59 +00:00
Patrick Rudolph 57907fcebf mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
* Enable optional x86_64 romstage, postcar and ramstage
* Add Kconfig for x86_64 compilation
* Add documentation for x86 qemu mainboards
* Increase CAR stack as x86_64 uses more than 0x4000 bytes

Working:
* Boots to Linux
* Boots to SeaBIOS
* Drops to protected mode at end of ramstage
* Enumerates PCI devices
* Relocateable ramstage
* SMM

Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29667
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19 10:50:49 +00:00
Patrick Rudolph e563815e05 arch/x86/boot: Jump to payload in protected mode
*   On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode.
*   Add a helper function to jump to arbitrary code in protected mode,
    similar to the real mode call handler.
*   Doesn't affect existing x86_32 code.
*   Add a macro to cast pointer to uint32_t that dies if it would overflow
    on conversion

Tested on QEMU Q35 using SeaBIOS as payload.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-19 09:06:43 +00:00
Patrick Rudolph 8daa12f7e0 arch/x86/postcar: Add x86_64 support
* Add support for loading GDT on x86_64.
* Add x86_64 assembly code to do the same as the x86_32 code.
* Separate x86_32 and x86_64 code.

Tested on qemu x86_32 and x86_64 using additional MTRRs.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-14 17:55:26 +00:00
Patrick Rudolph 03a79520d6 cpu/x86/smm: Add support for long mode
Enable long mode in SMM handler.
x86_32 isn't affected by this change.

As the rsm instruction used to leave SMM doesn't restore MSR registers,
drop back to protected mode after running the smi_handler and restore
IA32_EFER MSR (which enables long mode support) to previous value.

NOTE: This commit does NOT introduce a new security model. It uses the
      same page tables as the remaining firmware does.
      This can be a security risk if someone is able to manipulate the
      page tables stored in ROM at runtime. USE FOR TESTING ONLY!

Tested on Qemu Q35.

Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:28:32 +00:00
Patrick Rudolph d5321bf2fb Documentation: Add TODOs for secure SMM when using x86_64
Change-Id: I157238f18bc1c2eba0adc0b87caa9adaf3fc5d38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 07:27:52 +00:00
Paul Menzel 6663ad99cf arch/x86: Support x86_64 exceptions
*   Doesn't affect existing x86_32 code.

Tested on qemu using division by zero.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-05 19:56:09 +00:00
Arthur Heymans 55069d15d8 arch/riscv: Pass cbmem_top to ramstage via calling argument
Tested on the Qemu-Virt target both 32 and 64 bit.

Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10 11:46:10 +00:00
Patrick Rudolph b1ef725f39 cpu/qemu-x86: Add x86_64 bootblock support
Add support for x86_64 bootblock on qemu.

Introduce a new approach to long mode support. The previous patch set
generated page tables at runtime and placed them in heap. The new
approach places the page tables in memory mapped ROM.

Introduce a new tool called pgtblgen that creates x86 long mode compatible
page tables and writes those to a file. The file is included into the CBFS
and placed at a predefined offset.

Add assembly code to load the page tables, based on a Kconfig symbol and
enter long in bootblock.

The code can be easily ported to real hardware bootblock.

Tested on qemu q35.

Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04 11:58:58 +00:00
Patrick Rudolph c4d56d668f Documentation: Advertise support for OpenSBI
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
2019-08-06 12:04:01 +00:00
Patrick Rudolph c1b7e8a60b cpu/x86/pae/pgtbl: Add memset with PAE
To clear all DRAM on x86_32, add a new method that uses PAE to access
more than 32bit of address space.
Add Documentation as well.

Required for clearing all system memory as part of security API.

Tested on wedge100s:
 Takes less than 2 seconds to clear 8GiB of DRAM.
Tested on P8H61M-Pro:
 Takes less than 1 second to clear 4GiB of DRAM.

Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 08:45:50 +00:00
Xiang Wang 3d5bb2a5df Documentatioan: update stage handoff protocol
Change-Id: I170fc16675c2701f6ea133cfce6e5fabdfb0e8d3
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-06-21 09:28:56 +00:00
Patrick Rudolph f04e76bcf0 Documentation: Add arch x86
Describe state and assuptions made about x86_64 support.

Change-Id: I308a09b0eac269afd30df95ed3ea195238a6cfbe
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/30056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 10:31:07 +00:00
Paul Menzel b06f8ddfe8 Documentation/riscv: Improve `index.md`
1.  Add dot/period to the end of sentences
2.  Remove blank line at the end of the file
3.  Break lines after 75 characters
4.  Use RISC-V spelling
5.  Add comma for clarity

Change-Id: Icbe803dfbe92ca7850204a1a9f7175befe9c8bcf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28654
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30 02:10:44 +00:00
Jonathan Neuschäfer d3037bdf64 Documentation: Add and link the arch directory
Fixes: b159d5ba8f ("riscv: add documentation for stages and payloads")
Change-Id: I5ca8ed094c9b6d115da707375205872e782a66b2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-11 01:22:21 +00:00
Ronald G. Minnich b159d5ba8f riscv: add documentation for stages and payloads
Change-Id: Iff522e309e9cf9a31c1c79c24047d83d7fd0b00a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15 12:52:32 +00:00