If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig
does not exist in the coreboot tree (including submodules), drop it.
These files should be stored in the `site-local` subdirectory and the
paths specified for each board in `site-local/Kconfig`. For example:
config VGA_BIOS_FILE
default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200
Note that this is just an example. There are better ways to structure
one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option
would be one of them, though variants may still need special handling.
Also, update autoport to not generate `VGA_BIOS_FILE` defaults.
Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use the same function name as in soc/intel for this functionality. This
also brings the function name more in line with the extended version of
this function gpio_configure_pads_with_override which additionally
supports passing a GPIO override configuration.
This might cause some pain for out-of-tree boards, but at some point
this should be made more consistent, so I don't see a too strong reason
not to do this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC
chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers
while only allowing GPIO accesses through the GPIO API on the SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add GPIO IOMUX defines for the pins that are used in the mainboard code
which enables using the PAD_GPI and PAD_GPO macros.
TEST=Timeless build for APU2/3/4/5 results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The mapping of the package GPIO numbers to the GPIO numbers on the GPIO
controller isn't a 1:1 one, so add a comment about that to avoid
confusion. Also change the comment style to match the style guide.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie30bf5483ea2e2516d7e3fdd21ea9338362e526e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Also remove the unused amdblocks/acpimmio.h include in gpio_ftns.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: If121941c8a6ba88913653192740997aeef426548
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56784
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DEVICETREE` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the `smbios_full_table_len` function to consolidate table
length calculation. The case where the length of a table equals the
length of the structure happens when a table has no strings.
Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Factor out some boilerplate code into a helper `smbios_carve_table`
function, which zeroes out the table memory and fills in the header
fields common to all tables.
Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The initial value of `len` is never used. Declare and initialise all
local variables in a single statement to avoid this problem.
Change-Id: Ieb96758f4cd19d9d3f8fdc543e8ca17db06a2123
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Where applicable, use the size of the associated variable.
Change-Id: Ibbac2a82893232a6f87182a6a965b84a599d633e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
No board defines this macro. In preparation to drop OptionsIds.h files
from mainboards, remove commented-out references to `IDS_DEBUG_PORT`.
Change-Id: I67a10d863aeea9e1b91c38aa02d19106b7b97659
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: Ibc2876a5a8419ec4fa5a793bb996f5c14d989bac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: I9cd9fa0dc25b1143f8b4c1f20beffba638437398
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: Icae0ecae77a20e1568440e3191a29db33b5581d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Bank interleaving does not work on this platform, disable it.
AmdInitPost returns success thanks to this setting.
TEST=boot apu1 and see AGESA_SUCCESS after AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Bank interleaving does not work on this platform, disable it.
Additionally enable ECC feature on SKUs supporting it. AmdIntPost
returns success thanks to these settings.
TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after
AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I010645f53b404341895d0545855905e81c89165e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
No code in coreboot uses this option, so it might as well be dropped.
Change-Id: Ie58bab7e87831db08b9f398a777ba350920b707b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52639
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove CMOS options that are not read anywhere in the code. They may
have been used in the native AMD platform code, or got copied around
from board to board and never did anything to begin with.
Change-Id: Ib19ace4fa6e610a28e68fe2612b4e623f200f064
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52638
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we spot any error in the file, treat it as untested and
broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do this for consistency with later platforms.
Change-Id: Ia4903b40a8f617c59868aaa116115fa23603438c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Variable OSVR had a static value of 3 and OSFL() did not
actually call _OSI or _OS methods.
The conditional in HDA _INI method of OSVR is dropped and
use of DMA NoSnoop attribute remains disabled to retain
previous behaviour. For soc/amd/picasso a different decision
was made in CB:40782 as HDA _INI method was just dropped and
default configuration enables use of DMA NoSnoop attribute.
Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We deal with mb/lippert/frontrunner-af later since it currently
does not include <cimx/sb800/acpi/fch.asl>.
Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable PICM was not inside GNVS region and can use a static
initialisation value.
For most AMD platforms PICM default changes from 1 to 0.
Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.
Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use the same variable name as soc/intel to implement a common
_PIC method at top-level ASL.
Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Save for the IO_APIC2_ADDR definition, they are equivalent.
Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Most of these comments have been copy-pasted or serve no purpose other
than to eventually turn into misleading info. While the description of
the first 120 bits of CMOS could be useful, it should instead be added
to the documentation for the CMOS option infrastructure, or /dev/null.
Moreover, trim down newlines to no more than two consecutive newlines.
Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The passive clause is constructed with the past participle, which is
*defined* in this case. Fix all occurrences in AMD vendor code with the
command below.
git grep -l "is define at" src/mainboard/ | xargs sed -i 's/is define at/is defined at/'
Change-Id: I5aa0e6e064410b305aa5f2775271f6a8988da64b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46066
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
