coreboot has no CREDITS file.
Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch adds support to enable a linker workaround to a hardware
erratum on some early Cortex-A53 revisions. Since the linker option was
added very recently, we use xcompile to test whether the toolchain
supports it first. It is also guarded by a Kconfig since only a few
ARM64 SoCs will need this and it incurs a performance penalty.
BRANCH=none
BUG=none
TEST=Turned it on or off for Smaug and confirmed that it (dis)appeared
in verbose make output accordingly.
Change-Id: I01c9642d3cf489134645f0db6f79f1c788ddb00d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 57128785760c4dfa32d6e6d764756443a9323cb7
Original-Change-Id: Ia5dd124f484e38460d75fb864304e7e8b18d16b7
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294745
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11403
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
To allow a payload to define its own libpayload_init_default_cbfs_media,
default implementation needs to be defined weakly.
BUG=none
BRANCH=tot
TEST=dumped a cbfs file from depthcharge cli on jerry
Change-Id: Ice73ae5a63dfd49e79c0eeb92d4eade016d61c39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f308177fffb0d525fdb50f8d024568bb9025352
Original-Change-Id: I4721139aea3169c62c10a2a26582bd9277e4cb83
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/283061
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10783
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Without this, gdb_enter() is not defined.
Change-Id: I067dce371ee817d6ac77387fcbe42a9a7deb6438
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10755
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
There is no measurable performance impact, but
this positively impacts the memory used by payloads.
Change-Id: Ib2bdba4a7bf2a4c2391a20b3225bbb44422d3194
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10751
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This will make the code work with the different styles
of Kconfig (emit unset bools vs don't emit unset bools)
Roughly, the patch does this, and a little bit of fixing up:
perl -pi -e 's,ifdef (CONFIG_LP_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]`
perl -pi -e 's,ifndef (CONFIG_LP_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]`
Change-Id: Ib8a839b056a1f806a8597052e1b571ea3d18a79f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10711
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
libpayload is the only Kconfig based project under
the coreboot umbrella that is using Config.in as its
name for Kconfig config files. Rename that to Kconfig
as on the other projects for consistency.
Change-Id: I1c69ec13582d88409384b492484535dcc5e1ad20
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10520
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;
Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The current arm64 MMU interface is difficult to use in pre-RAM
environments. It is based on the memranges API which makes use of
malloc(), and early stages usually don't have a heap. It is also built
as a one-shot interface that requires all memory ranges to be laid out
beforehand, which is a problem when existing areas need to change (e.g.
after initializing DRAM).
The long-term goal of this patch is to completely switch to a
configure-as-you-go interface based on the mmu_config_range() function,
similar to what ARM32 does. As a first step this feature is added
side-by-side to the existing interface so that existing SoC
implementations continue to work and can be slowly ported over one by
one. Like the ARM32 version it does not garbage collect page tables that
become unused, so repeated mapping at different granularities will
exhaust the available table space (this is presumed to be a reasonable
limitation for a firmware environment and keeps the code much simpler).
Also do some cleanup, align comments between coreboot and libpayload for
easier diffing, and change all error cases to assert()s. Right now the
code just propagates error codes up the stack until it eventually
reaches a function that doesn't check them anymore. MMU configuration
errors (essentially just misaligned requests and running out of table
space) should always be compile-time programming errors, so failing hard
and fast seems like the best way to deal with them.
BRANCH=None
BUG=None
TEST=Compile-tested rush_ryu. Booted on Oak and hacked MMU init to use
mmu_config_range() insted of memranges. Confirmed that CRCs over all page
tables before and after the change are equal.
Change-Id: I93585b44a277c1d96d31ee9c3dd2522b5e10085b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f10fcba107aba1f3ea239471cb5a4f9239809539
Original-Change-Id: I6a2a11e3b94e6ae9e1553871f0cccd3b556b3e65
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271991
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10304
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
arch_program_segment_loaded ensures that the program segment loaded is
synced back from the cache to PoC. dcache_flush_all on arm64 does not
guarantee PoC in case of MP systems. Thus, it is important to track
and sync back all the required segments using
arch_program_segment_loaded.
BUG=chrome-os-partner:38231
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on smaug
Change-Id: Ic6fcc7e5e0cccbab317950f8abab0c494041d19a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 284e3784854f764159b64286cea366c66b6bce2c
Original-Change-Id: I5c35b9aa2ae9b5c1f2fcdef40ffb1cde7f49cc1a
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/263327
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9904
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to not duplicate the instruction cache invalidation
sequence provide a common routine to perform the necessary
actions. Also, use it in the appropriate places.
BUG=chrome-os-partner:38231
BRANCH=None
TEST=Compiles successfully for smaug and boots kernel
Change-Id: I1d311dbc70bf225f35d60bb10d8d001065322b3a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ab015156713eb7531378edbd1d779522681d529
Original-Change-Id: I8da7002c56139f8f82503484bfd457a7ec20d083
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/263326
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9903
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
size_t is an unsigned type and as such is a bad choice for a counting
down loop counter.
BRANCH=all
BUG=none
TEST=editing cli command line does not cause hangs any more
Change-Id: I0502553b5e2143052345edeb205a01558fccd9b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1c171f739497fcd26589976676ab94b23cd7ee8b
Original-Change-Id: I4aa38379ac356114fc91a32cced2fa45a00a09d6
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262714
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Tested-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The WG (write gate) bit in C0_EBase allows the upper two bits of
the exception base address to be set to something other than 2'b10,
thus allowing it to be relocated out of the traditional KSEG{0,1}
range. Since we're not using the segmentation features introduced
by EVA to relocate the unmapped segments, the exception vectors
should remain in KSEG0. Don't set the WG bit so that the upper
two bits of the exception base (2'b00, because of the identity
mapping) are ignored and we execute the exception vectors out of
KSEG0.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: Ie8b4eb6e41a328e7055736c9e3f6ff5ec83b9e13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5b002f5ae71c7729e467d4fe3fd8db187e15dea
Original-Change-Id: Id8b930db1e7a68f52dd61be4dfa9edaee2bebf7d
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246697
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9822
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add helper macros to convert between physical addresses and KSEG{0,1}
addresses. Also get rid of the virt_to_{bus,phys}_offset variables
as these are fixed values.
As nobody seems to be using getpagesize() on MIPS, no need to keep
virtual.c.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: Ia26c8eae53eb8f860747a6b321363776841d1a94
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c422b02e9a2a20d130913b1cfb835ad74c39ddca
Original-Change-Id: I9476cd225a08534830c700cba7bf9d3ef871757e
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/247190
Reviewed-on: http://review.coreboot.org/9821
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use bus_to_virt() to convert the physical address of the DMA
coherent region to an address in KSEG1 which is suitable for
device memory accesses.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: If382feda66f6d829f8b3548ab263cf603cab2e9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a88a175f6d6db81d3154fb5dd31a44363ab94653
Original-Change-Id: I9ad6435495df2c71d8f81a782f1c3dfcfd4aeb28
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246696
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9818
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There was a recent patch by Deepa Dinamani applied to coreboot's
cache.c which fixed a bug that occurred when icache is on but dcache
is off ("arch: armv7: Fix cache sync instructions."). Although this
bug is not likely to be encountered by the time libpayload is run,
it's worth applying it to keep things in sync.
BUG=none
BRANCH=none
TEST=n/a since we have icache and dcache enabled on all ARM platforms
when libpayload is run.
Change-Id: I83d9f96acb702975585e5d47c90e2ddaca488f6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31f985b58ac9227684fbe27481129ba01fd3ab8a
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I4ab0d97ef3a97dcd0fa96e10273c3b32486e0b40
Original-Reviewed-on: https://chromium-review.googlesource.com/243276
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Paging code is tricky and figuring out what is wrong with it can be a
pain. This patch tries to ease the burden by giving a little more
information for prefetch and data aborts, dumping the Instruction Fault
Address Register (IFAR), Instruction Fault Status Register (IFSR) and
Auxiliary Instruction Fault Status Register (AIFSR) or the respective
Data registers. These contain additional information about the cause of
the abort (internal/external, write or read, fault subtype, etc.) and
the faulting address.
BUG=None
TEST=I have read through enough imprecise asynchronous external abort
reports with this patch that I learned the bit pattern by heart.
Change-Id: If1850c4a6df29b1195714ed0bdf025e51220e8ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf3b4924121825a5ceef7e5c14b7b307d01f8e9c
Original-Change-Id: I56a0557d4257f40b5b30c559c84eaf9b9f729099
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223784
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of forcing boards to have DMA region below 4GiB, provide
Kconfig option DMA_LIM_EXCL that a board can use to set the upper
limit in MiB units on the address range reserved by DMA. By default,
this value is 0x1000 i.e. 4GiB limit on the DMA upper address.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Default value is seen as 0x1000.
Change-Id: Ie35d3844a0989486ae022f8922fdd4c9d7d57fb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6716cf312a103bc0440a558fc43c8c77869816e3
Original-Change-Id: I3ecbb4ec90995ab1568cb0924d5ce9467492697d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245250
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8800
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The raw_write_sctlr_current() cannot be used in mmu_disable() because
it pushes some registers to cached stack, and then just after cache
disabled, the value was gone.
BRANCH=none
BUG=none
TEST=build and boot on mt8173-evb
Change-Id: I512405b7917f27d16bdd3c51d9459827ad714e67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aafe64922cc4cd01ecb099db106d04538e3e57ff
Original-Change-Id: I0dda8518d14c46fae1fe76e3629bd4ee81c1e0ee
Original-Signed-off-by: HC Yen <hc.yen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/240323
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8799
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Allow read/write to registers at a given el. Also, make read/write
registers at current el call this newly added function.
BRANCH=none
BUG=none
TEST=build and boot on mt8173-evb
Change-Id: Id69f0fdc07193c5c7e997712f0cd99de6f41510b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c091917babc39d9ab997f51f81b486c9aa900c24
Original-Change-Id: I0944946642066b88331e497a92388e74e86902d0
Original-Signed-off-by: HC Yen <hc.yen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/240322
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8798
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The framebuffer structure lives in the coreboot tables. Those
tables have a checksum calculation applied over all the entries.
Therefore, one shouldnot be modifying fields within the coreboot
table entries because the calculated checksum would be wrong.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=On ryu, confirmed dev screen still works as well as cbmem utility
once booted.
Change-Id: I93830a8efe98aa848f2b0f8388688de0e93b2f82
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6026ca5ad0254c14c30412882dc63550656c7d16
Original-Change-Id: Ic9c164ded03d10d6f6f3ce15e9b38b1f6ce61a91
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230471
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8797
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Allocate noncacheable memory for frame buffer and save base
address to sys_libinfo.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Change-Id: I19a8079616376dc7c1a8ecdbd7499c2553b8c6c3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cebb5650167264902548339bb1a2b428f3b7f4ed
Original-Change-Id: I7bfbfefb92001632ce3d572a50e46188795c4ab8
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226404
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8796
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is important since mmu is disabled during the post_sysinfo_mmu_setup call
and calling printf can cause unaligned access.
BUG=None
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt with console_init
Change-Id: I5ef72ee449fdcf30186f97485cc532d6c56b2c5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 688ef3856d0502d057c9543ee7763601156e6385
Original-Change-Id: Ie376e394d084edd6c999fc9edde79f15a0264e7b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/222664
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8795
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide a function to obtain a new memrange with requested properties (type,
size, alignment, max_addr and other restrictions) from the set of available
memranges passed in coreboot table. One user of this function would be getting
memrange for dma, another one would be framebuffer.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: Ic5a63ca2dca6c71f4ca2d77e2e2c8180d32a38e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3cd75756e1405e044c029f2878bfcc9c8c962bdf
Original-Change-Id: I187d73a4d55d3c6f49afbe9852901672d25de8dc
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/222110
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8794
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
1. keep functions and objects used entirely within mmu.c as static.
2. DMA region finding needs to terminate. Therefore, the next address
to be attempted needs to be less then the current end address.
3. Ensure mmu_ranges passed to mmu_init_ranges_from_sysinfo() has
0 entries marked as used.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Booted ryu with RAM hole above cbmem tables below 4GiB.
Change-Id: I71a9cb89466978aa63fca5d8bee97b8af75ea206
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 66518fd86e676bbddf52e9d9afdd76d72c8e2222
Original-Change-Id: I5cb4e5009359cb04c4e1b5fe60845f80fbdff02c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/221725
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8793
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
What this change does:
1) Initialize limited page tables as soon as we jump into libpayload. Basically
two ranges are initialized. One is for the BASE_ADDRESS and other is for the
coreboot_tables. With page tables initialized and MMU enabled, we jump into
code to parse coreboot tables.
2) Once coreboot tables are parsed and we have complete picture of the memory,
we perform a complete page table initialzation and enable MMU and then jump to
payload.
Additionally, we also:
1) Initialize DMA memory on our own depending upon the memory map. It ensures
that the DMA buffer is placed in 32-bit memory.
CQ-DEPEND=CL:216826
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully and we are able to start execution of libpayload in
EL2 and reach kernel login prompt
Change-Id: I8a6203e465868bc2a3e5cc377e108f36cc58e2fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7695bb7afe34ea460282125a0be440e8994b01e4
Original-Change-Id: Ie0f47b7759d4ac65a6920f7f2f7502b889afda6d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216824
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Adds support for initializing mmu, setting up dma areas and enabling mmu based
on the memranges passed on in the coreboot tables.
CQ-DEPEND=CL:216826
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully
Change-Id: Id41a4255f1cd45a9455840f1eaa53503bd6fef3f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f2c6676bf51fcd85b61e9e08a261634a78137c4c
Original-Change-Id: I217bc5a5aff6a1fc0809c769822d820316d5c434
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216823
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Libpayload should be able to setup its own dma areas and not depend on coreboot
tables for passing this information. This patch and next allow libpayload to
setup dma areas while performing mmu_init
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully and dma areas are setup properly with the mmu init patch
Change-Id: I5f6fd19a957c7626a2bbe6b826c8987e64ed248f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f3552b8d3439a8b12d1e0b15ef67dcb14b8c96a
Original-Change-Id: I44d9f394fa349abd7182c4ba10f1eaefd6e4fdaa
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216822
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8789
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
By default we dont want to use the special DC instruction. Thus getting rid of
the DONT_USE_DC macro and enabling code appropriately in memset.S
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully and memset works fine for mmu init
Change-Id: Icb3193f4f0d122726dcdacbdcacbf53eba30e235
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 54f639ef2348acab54e32b18f6826a67bf52bc14
Original-Change-Id: Id89ec2c1731d21496eca617a3c03abaf48062908
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216820
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8787
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Allow more flexibility by reading and writing to system registers at current
EL. Instead of specifying what _ELx register to write to, code can specify
_current.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles and boots to kernel on ryu
Change-Id: Id38b675bfe67ca1e25f8c268192114e3f0bee800
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6d4d07e26fc964dc3aaebfe03db59596d90093e9
Original-Change-Id: Ic1d9e18e6fc016a04f17621a148e62d6cbd04ce7
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214577
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8785
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add library helpers to access standard arm64 registers. This library also
provides functions to directly read/write register based on current el. So, rest
of the code doesnt need to keep checking the el and call appropriate function
based on that.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Libpayload and depthcharge compile successfully for ryu
Change-Id: Ibc0ca49f158362d4b7ab2045bf0fbd58ada79360
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ca6da580cb51b4c23abdaf04fee2785e5780510
Original-Change-Id: I9b63e04aa26a98bbeb34fdef634776d49454ca8d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214575
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8784
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA and bring up board; works as
expected
BRANCH=none
Change-Id: I368494f388b82969dda0ce73a38824791efce616
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4c2bbcbdbcf706062724cffe2d5f15953468ace
Original-Change-Id: Id5c9b1d65c6ec87f2aba06995dc940c50afb041f
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245386
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add CPU frequency corresponding to SOC.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; behaves as expected.
BRANCH=none
Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604
Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241427
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8853
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The default string functions work with multiple of 4 bytes
(sizeof(unsinged long)); MIPS will use LW/SW instructions
for these operations and if the source and destination
addresses are not aligned it will trigger an exception.
Therefore, this implementation does all data access operations
per byte, because there is no guarantee that the provided
strings are properly aligned.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; behaves as expected
BRANCH=none
Change-Id: I05b43673deb954f022d12cb9c3d7baac26be2a34
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e13b3d31726404abd8c8e5c8780d3d3e16e032d
Original-Change-Id: I456e312eb6b7fee2eff10e461af7f578aed07648
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241885
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the basic build infrastructure and architectural support
required to build for targets using the MIPS architecture.
This will require the addition of cache maintenance.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA with Depthcharge as payload;
successfully executed payload.
BRANCH=none
Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf
Original-Reviewed-on: https://chromium-review.googlesource.com/219740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8741
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It turns out that CB_TAG_ACPI_GNVS is handled in both x86 specific and
common coreboot table parsing code. The MRC cache case used only by
x86 is handled in the common code.
This patch restores sanity and moves processing to where it belongs.
BRANCH=none
BUG=none
TEST=verified that arm and x86 targets build.
Change-Id: Iaddaa3380725be6d08a51a96c68b70522531bafe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0afae893d5027026cb666cd46e054aeae4e71f83
Original-Change-Id: I2c114a8469455002c51593cb8be80585925969a7
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225457
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There are three instances of coreboot.c in libpayload. for x86, arm
and arm64 architectures. The arm and arm64 instances are exactly the
same. The differences with the x86 instance are as follows:
- a very slightly different set of coreboot table tags is parsed (one
tag added and two removed)
- instead of checking a fixed address if it contains the coreboot
table, the x86 version iterates over two address ranges.
This patch refactors the module, leaving architecture specific
processing in arch subdirectories and moving the common code into
libc.
BUG=none
TEST=none yet
Change-Id: I1c7ad6f74e3498e93df78086ba0ff708c08e0a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3df209d58ebd5c5b1cf0168f6466e065d1ef3598
Original-Change-Id: I6dfed73f6ba5939f692d0f98d2774c0e0312a25f
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210770
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8750
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Make board ID value supplied in the coreboot table available to the
bootloader on all three architectures.
BUG=chrome-os-partner:30489
TEST=none yet
Change-Id: I6c2d39e94212b55650929d7d99896581d23f789d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 723e4a600a5d3a03e960169b04f8322f6dd2486b
Original-Change-Id: I7847bd9fe2d000a29c7ae95144f4868d926fb198
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210430
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8730
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add stub implementation for gdb arm64 support. Currently all functions are kept
empty to enable proper compilation of depthcharge and libpayload. As we get more
clear about context management and stuff, we can add details for gdb as well.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Original-Change-Id: I0a8729671ab0764d424c0e3d50af86433d05b1e8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/204877
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit d24e5c26b56a9882b3450b1e4988b56c3d73efd1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9b7d3d7060dd827ef4a46865e0f9a2b4e063d07d
Reviewed-on: http://review.coreboot.org/8125
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Stefan Reinauer