This change adds a macro `PAD_NC` for configuring no-connect pads. This
configures the pad as input with pull-down.
Change-Id: I47c41c88ccfebe2c5dd9a24f85a120af9c8f56b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change drops mainboard.asl from zork because none of the objects
defined in it are used.
Change-Id: I879b5614fb5d12c4814ee52f840a000744a7aab9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43520
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops mainboard.asl from zork because none of the objects
defined in it are used.
BUG=b:153879530
Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops _INI and OSFL methods under \_SB since they are not doing
anything useful. _INI only calls OSFL and OSFL initializes OSVR if not
already initialized and returns OSVR value. However, OSVR is not used
anywhere and hence both these functions can be dropped.
BUG=b:153879530
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4f3e1c93a855006cc115087fded20bfb76c1133e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43515
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Global variable `PMOD` that stores the interrupt mode used by OS is
required by all mainboards. This change moves the variable definition to
globalnvs.asl under picasso.
Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC
until _PIC() method is called by OS. Thus, this change also updates the
default value of PMOD as 0 i.e. PIC mode.
BUG=b:153879530
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I731c03d965882281a7a23f55894451210ba72274
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO_9 is associated with gevent 22. Correct all the misconfigurations
and use macros for clarity as to what bit offset is being used instead
of open coding things.
BUG=b:161205804
Change-Id: Ic4cfd62763d72d12a55f89585f24e07df6af0f4f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43516
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses read-modify-write to update ACP_I2S_PIN_CONFIG instead of
a write operation since the other bits in the register are reserved.
Change-Id: Ic64e1907858ec293c5f759e627d19c00d748a30e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43503
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for configuring ACP_PME_EN and ACP_I2S_WAKE_EN
using the mainboard setting for `acp_pme_enable` and `acp_i2s_wake_enable`
in the devicetree. This is required to get I2S_Wake event on headset jack
plug/unplug when using CODEC_GPI pad.
BUG=b:146317284,b:161328042
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Change-Id: I522d7497940f499fbc3181d866f2b44e979bba7a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1969104
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43495
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 56da63c3dc removed overriding that
field in the FADT.
Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Dali supports two SATA ports, but no PCIe alternate function on those
pins.
Change-Id: I27a13100e80565eb1dade2d703ba3d1f8b5f630f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The DXIO descriptors use the logical and not the physical lane numbers,
which are different.
Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently, the code and data in psp_verstage is ~59K. Adding the code
to save vbnv to the SPI rom increases that to 66K.
Getting rid of VERSTAGE_SIZE allows verstage to grow as it needs to.
BUG=b:161366241
TEST=Build & Boot Morphius with VBOOT_VBNV_CMOS_BACKUP_TO_FLASH enabled
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic6853b70073f9e781fc10402a2a47c9c8e0d49d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43486
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no reason to create a named variable. We can just return the
package.
BUG=b:153001807, b:154756391
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic0ca2e6d4fb833c68d29e9948a670ace7c89b6a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Extend the local APIC timer delay so that it can be started,
and waited for, independently.
Add an EOI so that more than one APIC timer interrupt is possible.
Previous to this, because there was no EOI, the first timer
interrupt the CPU took was also the last it would take --
apic_delay would only work one time.
Change-Id: Ib11aeee5b7da81287166ac68fc327e7ae62d1b84
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
mainboard_romstage_entry_s3() was dropped from zork (CB:43476). This
function call in picasso does not do anything and hence is being dropped.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I10e15422d7eef5af9c19737c32e433718b6479d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43477
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe
GPIOs can be configured early on in bootblock rather than waiting until
romstage. This change moves the call to variant_pcie_gpio_configure() to
happen in bootblock and drops romstage.c file.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in
romstage. This change moves the configuration of PCIe related GPIOs to
variant_pcie_gpio_configure() to keep all the configuration for WiFi and
non-WiFi PCIe pads in one place. It also drops the function
variant_romstage_gpio_table() as it is unused.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the power and reset GPIO configuration for non-PCIe devices is
dropped from romstage GPIO table, the tables for pre-v3 and v3 version of
schematics are exactly same. So, this change drops the duplicate table and
also removes the check for v3 schematics when configuring the pads in
romstage.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change keeps pen power enabled in sleep state to allow it to
charge in S3.
BUG=b:155422911
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6190496653878327f34a01f6a743db474d32e929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43452
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit a5ca4a0c75.
Reason for revert: Breaks coreboot tree because of non existent kconfig symbol
Change-Id: Ib8f55dc2f6444690945bc2dc64baad5d0c39cdf4
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently the common soc code automatically selects
POWER_STATE_DEFAULT_ON_AFTER_FAILURE which making other mainboard
options unselectable.
However, there're some cases that power state should change to different
states after reapplying power.
Make POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y but do not select it
in soc code so that we can disable it and select other options in the
mainboard code.
Tested on OCP Delta Lake.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifa853d81ee9477d2440ceaa67b2bd6b863ee52c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implement sending POST start/end command to BMC.
TEST=Read POST command log in OpenBMC,
if command received successfully, message may show as below,
root@bmc-oob:~# cat /var/log/messages |grep -i "POST"
2020 May 28 13:21:22 bmc-oob. user.info fby3-v2020.20.2:
ipmid: POST Start Event for Payload#1
2020 May 28 13:21:25 bmc-oob. user.info fby3-v2020.20.2:
ipmid: POST End Event for Payload#1
root@bmc-oob:~#
Signed-off-by: TimChu <Tim.Chu@quantatw.com>
Change-Id: I38b512ee97c0eda6ba54482a448ef9ffc27b4ddb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41993
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.
Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
We typically call checkpatch.pl through make lint which properly adds
the option to tell checkpatch that our lines may be 96 columns long.
However there's one mention of calling checkpatch directly and that
confuses people with complaints about overly long lines that exceed
80 columns.
The lint test that runs checkpatch (and with the right options)
can also be used on a per-directory basis, so offer that instead.
Change-Id: If21e925d2d2394c876724a44b0e23c9b2744c56b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This pin has been removed from recent revisions (or at least moved to a
pin that's not controlled like a normal GPIO). It has also never been
used on older ones (I think?). The same GPIO is now used as a SKU ID
pin, so make sure we're not incorrectly configuring it as an output
(although sku_id() overrides that later anyway, but it's still
incorrect).
BUG=b:160754995
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6e0d56e230d0bef172d7b78cc48263e9b6f059de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43471
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This information is redundant since it's already specified in
baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb
domain 0 is still required because sconfig uses it as an identity anchor
to match devicetree and overridetree.
BUG=b:157580724
TEST=Boot zork, usb functional
Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that Zork is using upstream coreboot, we need the template files
in the main branch.
BUG=b:157570490
TEST=n/a
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I6cab4ab0b414473e0a759dce81df9872a40d3f26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43419
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Up until now we have no way of adding transparency into our firmware
screens. Add set_blend() and clear_blend() functions to store alpha
value and rgb values to calculate alpha blending in
calculate_colors().
BUG=b:144969091,b:160839199
BRANCH=puff
TEST=dut-control power_state:rec
press ctrl-d
Ensure background is dimmed when dialog pops up
Change-Id: I95468f27836d34ab80392727d726a69c09dc168e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Check the output of `cbmem -t` for unknown timestamps. If present, ask
the user to rebuild `cbmem`.
Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If the AP actually needs to write to the TPM, then it is important and
the TPM should commit those changes to NVMEM immediately in case there
is an unexpected power loss (e.g. from a USB-C port partner reset upon
cold reboot request).
BRANCH=none
BUG=b:160913048
TEST=Verify that puff will no longer reboot loop when coreboot writes a
new Hmir (Hash mirror) in the TPM
Change-Id: I9597a55891d11bdf040d70f38b4c5a59c7888b8a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43414
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and
DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to
enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to
assert the DEVSLP signal as soon as there are no commands outstanding
to the device and the port specific Device Sleep idle timer has expired.
Device Sleep Idle Timeout values (PxDEVSLP.DITO and PxDEVSLP.DM) are
port specific timeout values used by the HBA for determining when to
assert the DEVSLP signal. They provides a mechanism for the HBA to apply
a programmable amount of hysteresis so as to prevent the HBA from
asserting the DEVSLP signal too quickly which may result in undesirable
latencies. This patch is created based on Intel Tiger Lake Processor
PCH Datasheet with Document number:575857 and Chapter number:12.
* PxDEVSLP.DM -> SataPortsDmVal: Enable SATA Port DmVal DITO multiplier.
Default is 15.
* PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout
(DITO), Default is 625ms.
BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer and TGL RVP.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42214
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.
BUG=b:153001807, b:154756391
TEST=Build Trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is no reason to create a named variable. We can just return the
package.
BUG=b:153001807, b:154756391
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This PCI ID is required in order for JSL devices to perform SSDT
generation for DPTF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Furquan Shaikh