Commit Graph

834 Commits

Author SHA1 Message Date
Stefan Reinauer 8e304e6616 fix cross compilation in abuild for certain scenarios
(coreboot.org build system internal)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 18:16:11 +00:00
Stefan Reinauer be84b01e18 fix some warnings by casting safely. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 13:20:33 +00:00
Stefan Reinauer 962242ad2d use $(MAKE) instead of hardcoded "make".. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 13:05:18 +00:00
Patrick Georgi 2d2589e682 Fix the concurrency issue of building romtool.
romtool is still built in util/romtool, as happens without this patch.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 10:01:21 +00:00
Patrick Georgi f16fb73087 I thought that romfs infrastructure is done now, but there were some
issues (see buildbot).
The romfs image was always built, and sometimes broke (because of
the different image layouts) for buildrom images. After the patch, these
issues are avoided by not adding payloads to the romfs image (they
wouldn't be read anyway). Both workarounds (in buildrom code for
romfs and vice-versa) aren't very pretty, but that's what our buildsystem
requires.
As I had to create a "communication channel" (via the romfs-support
files), I took the chance to also use it for compression
information, so if you configure lzma support, you'll get lzma
compressed payloads in romfs.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 16:17:05 +00:00
Stefan Reinauer 1b9a5c636e This patch implements --include=file.h for romcc.
The compile_file calls seem to be in the wrong order, but
romcc actually requires it that (probably some stack-like
file processing)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 14:04:06 +00:00
Patrick Georgi aed1f925a6 the attached patch is the last infrastructure change necessary for
romfs.
Everything else to make a target romfs aware happens in the targets.

What the patch does:
1. missing romfs.h include
2. special handling while creating coreboot.rom
While the romfs code path in the makefile doesn't actually use the file,
it's possible that the build of coreboot.rom fails in a romfs setup,
because the individual buildrom image is too small to host both coreboot
and payloads (as the payloads aren't supposed to be there). Thus, a
special case to replace the payload with /dev/null in case of a romfs
build.
There would be cleaner ways, but they're not easily encoded in the
Config.lb format.
3. config.g is changed to create rules for a romfs build

Targets should still build (they do for me)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 12:52:43 +00:00
Ronald Hoogenboom e729846b64 Ronald Hoogenboom writes:
I've attached a patch that removes the 3-mile-long compiler
commandlines, which vim's quickfix doesn't like so much. Instead of
putting all those -DXYZ='bla' on the compiler commandline, they are put
in a file called settings.h (as #define XYZ bla) and only a
--include=settings.h is put on the commandline.
This file is created unconditionally at the same time as when the
CPUFLAGS simply expanded make variable used to be created (not via a
target rule and dependency), so it shouldn't change anything.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-02 23:08:16 +00:00
Ronald G. Minnich 5d01ec0f80 This patch adds Jordan's romtool support for v2.
There are a few changes. The 20K bootblock size restriction is gone. 

ROMFS has been tested and works on v2 with qemu and kontron. Once this 
patch is in, those patches will follow. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 11:57:36 +00:00
Mondrian Nuessle 0f0f9bb9a2 flashrom: Board enable support for HP DL145 G3.
This is a BCM5785 based machine, WP# and TLB# need to be deasserted using
GPIO 2 and 5 from the PM registers of the southbridge.
This is very similar to the x3455 implementation.

Signed-off-by: Mondrian Nuessle <nuessle@uni-hd.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-30 13:20:01 +00:00
Uwe Hermann 83da8dcf60 - List SMSC LPC47N227 runtime register block as supported.
- Add missing contributor in README.

- Cosmetic fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-25 17:38:40 +00:00
Peter Stuge 5f28c09ce5 msrtool: If an MSR name lookup fails in msraddrbyname(), return the strtoul() conversion result.
Thanks to Mart for finding and reporting the problem!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-23 17:43:12 +00:00
Carl-Daniel Hailfinger 5182f67590 Move the Atmel AT45 comments about block and page sizes from the end of
the struct to the individual struct members to improve readability.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-19 12:18:13 +00:00
Stefan Reinauer 927377febe Add support for high coreboot table to mkelfimage
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 15:33:41 +00:00
Stefan Reinauer 764fe40f09 This patch adds "high coreboot table support" to coreboot version 2.
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
the coreboot table integrity, rendering the table useless.

By moving the table to the high tables area (if it's activated), this problem
is fixed.

In order to move the table, a 40 bytes mini coreboot table with a single sub
table is placed at 0x500/0x530 that points to the real coreboot table. This is
comparable to the ACPI RSDT or the MP floating table.

This patch also adds "table forward" support to flashrom and nvramtool.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 14:39:36 +00:00
Stefan Reinauer 3f72e32b06 This patch adds "high coreboot table support" to coreboot version 2.
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
the coreboot table integrity, rendering the table useless.

By moving the table to the high tables area (if it's activated), this problem
is fixed.

In order to move the table, a 40 bytes mini coreboot table with a single sub
table is placed at 0x500/0x530 that points to the real coreboot table. This is
comparable to the ACPI RSDT or the MP floating table.

This patch also adds "table forward" support to flashrom and nvramtool.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 14:39:25 +00:00
Stefan Reinauer 8f556be766 abuild: Don't forget CROSS_COMPILE anymore.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-15 09:55:17 +00:00
Stefan Reinauer 2f110a8006 trivial patch for abuild: allow powerpc-elf-gcc, too.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-14 16:33:22 +00:00
Stefan Reinauer 84a1f4e261 this commit should fix Ticket #122 (proper log files for all builds)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13 17:22:53 +00:00
Patrick Georgi d229677b61 20090310-3-scanbuild:
Add support for clang's scan-build utility to abuild. scan-build wraps
the compiler and runs its own compiler on the same sources to do some
static analysis on them. It adds an option "-sb" or "--scan-build" that
creates a coreboot-builds/$target-scanbuild directory for every $target,
containing the output of scan-build, which is a HTML documentation on
its results.
Be aware, that scanbuild significantly increases build time: A board
that takes 6-7 seconds normally requires 60 seconds with that option
enabled on my test system.
The patch also moves the stack-protector option down a bit, so it
applies to crosscompiled targets, too (which overwrote the compiler
settings before)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 15:43:02 +00:00
Stefan Reinauer cc44b06d9d abuild:
- add configure only mode to easily and quickly check Config.lb and Option.lb
  files
- fix up cross compiler handling
- don't use in-place sed, not all sed versions can do it
- use perl instead of date to avoid non-gnu date trouble

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 15:00:50 +00:00
Stefan Reinauer 6df0c62b68 Add support for the LPC47M182 to superiotool
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 14:48:20 +00:00
Marc Jones 8f210766d5 Add some basic K8 MSRs.
Fix bash script type.
Removed const return type on msraddrbyname() to fix gcc warning/error.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-08 04:37:39 +00:00
Carl-Daniel Hailfinger 3b1a955cce FreeBSD definitions of (read|write)[bwl] collide with our own. Before we
attempt trickery, we can simply rename the accessor functions.

Patch created with the help of Coccinelle.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Idwer Vollering <idwer_v@hotmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 22:26:00 +00:00
Carl-Daniel Hailfinger 59c36f97db During the conversion of flash chip accesses to helper functions, I
spotted assignments to volatile variables which were neither placed
inside the mmapped ROM area nor were they counters.
Due to the use of accessor functions, volatile usage can be reduced
significantly because the accessor functions take care of actually
performing the reads/writes correctly.

The following semantic patch spotted them (linebreak in python string
for readability reasons, please remove before usage):
@r exists@
expression b;
typedef uint8_t;
volatile uint8_t a;
position p1;
@@
 a@p1 = readb(b);

@script:python@
p1 << r.p1;
a << r.a;
b << r.b;
@@
print "* file: %s line %s has assignment to unnecessarily volatile
variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b)

Result was:
HANDLING: sst28sf040.c
* file: sst28sf040.c line 44 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 43 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 42 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 41 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 40 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 39 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 38 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 58 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 57 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 56 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 55 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 54 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 53 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 52 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);

The following semantic patch uses the spatch builtin match printing
functionality by prepending a "*" to the line with the pattern:
@@
expression b;
typedef uint8_t;
volatile uint8_t a;
@@
* a = readb(b);

Result is:
HANDLING: sst28sf040.c
diff =
--- sst28sf040.c        2009-03-06 01:04:49.000000000 +0100
@@ -35,13 +35,6 @@ static __inline__ void protect_28sf040(v
        /* ask compiler not to optimize this */
        volatile uint8_t tmp;
 
-       tmp = readb(bios + 0x1823);
-       tmp = readb(bios + 0x1820);
-       tmp = readb(bios + 0x1822);
-       tmp = readb(bios + 0x0418);
-       tmp = readb(bios + 0x041B);
-       tmp = readb(bios + 0x0419);
-       tmp = readb(bios + 0x040A);
 }
 
 static __inline__ void unprotect_28sf040(volatile uint8_t *bios)
@@ -49,13 +42,6 @@ static __inline__ void unprotect_28sf040
        /* ask compiler not to optimize this */
        volatile uint8_t tmp;
 
-       tmp = readb(bios + 0x1823);
-       tmp = readb(bios + 0x1820);
-       tmp = readb(bios + 0x1822);
-       tmp = readb(bios + 0x0418);
-       tmp = readb(bios + 0x041B);
-       tmp = readb(bios + 0x0419);
-       tmp = readb(bios + 0x041A);
 }
 
 static __inline__ int erase_sector_28sf040(volatile uint8_t *bios,

It's arguably a bit easier to read if you get used to the leading "-"
for matching lines.

This patch was enabled by Coccinelle:
http://www.emn.fr/x-info/coccinelle/


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@settoplinux.org>
-- 
http://www.hailfinger.org/


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 00:40:25 +00:00
Carl-Daniel Hailfinger ac12ecd27a flashrom: Use helper functions to access flash chips.
Right now we perform direct pointer manipulation without any abstraction
to read from and write to memory mapped flash chips. That makes it
impossible to drive any flasher which does not mmap the whole chip.

Using helper functions readb() and writeb() allows a driver for external
flash programmers like Paraflasher to replace readb and writeb with
calls to its own chip access routines.

This patch has the additional advantage of removing lots of unnecessary
casts to volatile uint8_t * and now-superfluous parentheses which caused
poor readability.

I used the semantic patcher Coccinelle to create this patch. The
semantic patch follows:
@@
expression a;
typedef uint8_t;
volatile uint8_t *b;
@@
- *(b) = (a);
+ writeb(a, b);
@@
volatile uint8_t *b;
@@
- *(b)
+ readb(b)
@@
type T;
T b;
@@
(
 readb
|
 writeb
)
 (...,
- (T)
- (b)
+ b
 )

In contrast to a sed script, the semantic patch performs type checking
before converting anything.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
Tested-by: Joe Julian


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-05 19:24:22 +00:00
Stefan Reinauer 2b34db8d1d coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 20:10:20 +00:00
Stefan Reinauer 9987ad806f This is a small fix for the last checkin (does not fix those two boards) that
caused same filenames to still cause objects being dropped from the build list
- which was the whole purpose of the patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 17:09:29 +00:00
Stefan Reinauer 21c8b5ab5c With this patch the v2 build system will create a directory hierarchy
similar to what v3 does. This is required to have two source files with
the same name but in different directories. (As in, two different SuperIOs on
board, with a superio.c each)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 12:50:32 +00:00
Zheng Bao a85c0059f3 flashrom: Add SST25VF040.REMS with TEST_OK_ PROBE READ
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-25 08:07:33 +00:00
Peter Stuge bc8744e1bf flashrom: SST29EE020A TEST_OK_ PROBE READ ERASE WRITE
Report by Holger Mickler. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-22 21:07:28 +00:00
Carl-Daniel Hailfinger 7ad11e8d33 Carl-Daniel's part:
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and 
mainboard_$VENDOR_$BOARD_config to mainboard_config.

Ron's part:
The config change that makes the naming change not break every build.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-18 20:41:57 +00:00
Myles Watson 94e340b22a Change 0x%p to %p. Thanks Stefan for catching the one I introduced in 3931.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-10 03:02:05 +00:00
Peter Stuge cd7e9b55dd flashrom: Fix broken flash chip base address logic
Elan SC520 requries us to deal with flash chip base addresses at locations
other than top of 4GB. The logic for that was incorrectly triggered also when
a board had more than one flash chip. This patch will honor flashbase only when
probing for the first flash chip on the board, and look at top of 4GB for later
chips.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09 20:26:14 +00:00
Peter Stuge 15884260e7 flashrom: MSI MS-7046 board enable
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: David Tiemann <davidtiemann@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-02 22:55:26 +00:00
Rudolf Marek e66c258f1b Following patch fixes VIA SPI (VT8237S). It needs to have opcodes
initialized same way as ICH7.

 Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
 Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-01 18:40:50 +00:00
Carl-Daniel Hailfinger b6dc72303c Factor out read and erase functions from flashrom main().
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-28 00:27:54 +00:00
Peter Stuge 3108a12e9b msrtool: Allow MSR symbols (names) to also be used as addresses.
Thanks for the idea Mart!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 17:18:31 +00:00
Peter Stuge c1d6ed9a21 msrtool: Linux /dev/cpu/*/msr returns the low 32 bits before the high 32 bits.
Thanks to Mart for spotting this!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 17:03:05 +00:00
Peter Stuge a8866243d8 flashrom: Add VT8237A PCI ID
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 15:29:27 +00:00
Peter Stuge 726c16d983 flashrom: Fix one dead increment and one dead assignment as found by clang.
Thanks Patrick!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 15:19:43 +00:00
Peter Stuge c39cb144e9 flashrom: Driver for ST M29F002T/NT/B. T/NT TEST_OK_ PROBE READ ERASE WRITE
Test report from Julia. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Julia Longtin <juri@solarnetone.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 06:42:02 +00:00
Peter Stuge f3bc765493 flashrom: Fix copypaste error in r3913.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 04:48:01 +00:00
Peter Stuge fbda0d3143 msrtool: AMD CS5536 probe implementation.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 04:12:58 +00:00
Peter Stuge 279cdbb37d msrtool: Make configure work with zsh, the default shell in Darwin.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 04:10:12 +00:00
Peter Stuge c800eeb39b flashrom: SST25VF040B using 0x90 identification and AAI write.
SST AAI is Auto Address Increment writing, a streamed write to the flash chip
where the first write command sets a starting address and following commands
simply append data. Unfortunately not supported by Winbond SPI masters.

From July 2008.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:37:40 +00:00
Peter Stuge 9ee44151cc flashrom: Decode SST25VF040B status register, also from July 2008.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:23:50 +00:00
Peter Stuge 37c4a96874 flashrom: Intel Desktop Board D201GLY
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:12:44 +00:00
Peter Stuge 36b3932f99 flashrom: Winbond SuperIO SPI driver.
Developed and tested to work on Intel D201GLY in July 2008.
Tested by a helpful person on IRC whose name I've since forgotten. Sorry!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:08:45 +00:00
Peter Stuge 8991302f54 flashrom: Export Winbond SuperIO register access functions in board_enable.c.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 02:34:51 +00:00