Commit Graph

38189 Commits

Author SHA1 Message Date
Angel Pons 8f0757ea94 nb/intel/sandybridge: Use arrays to program IOSAV
Instead of programming subsequences one-by-one, we might as well take
the whole sequence as an array and program all subsequences in one go.

Since the number of subsequences is now known in advance, handling of
global state can be simplified, which allows reusing the last sequence.

Change-Id: Ica1b2b20e04ae368f10aa236ca24d12f69464430
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19 22:51:51 +00:00
Angel Pons 1c505f8277 nb/intel/sandybridge: Move IOSAV functions to separate file
Change-Id: Icbe01ec98995c3aea97bb0f4f84a938b26896fab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-19 22:51:06 +00:00
Felix Held 2b48a6089c include/device/pci_ids: add model number to ATI GPU and HDA controller
Change-Id: I215058bcb0d53bfec974b8d3721cb4c998fcbee5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47702
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 22:02:09 +00:00
Martin Roth 11c765c1f1 mb/google/zork: Set GPIO 86 high on boot
GPIO 86 should be set high on boot to save power.

BUG=b:173340497
TEST=Build only
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I31ef1d2a1967d82ba5370462783a909417088d2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-19 20:58:33 +00:00
David Wu c913c7ead1 mb/google/volteer/var/terrador: Correct enable_gpio to GPP_F16
The GPP_F16 is for enable_gpio after check the schematic.

BUG=b:151978872
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I63f43c231e624ed034ef18e8f06942ff3622d821
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-19 20:19:23 +00:00
Ronak Kanabar fecc2f87a0 vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_02
The headers added are generated as per FSP v2385_02.
Previous FSP version was 2376.
Changes Include:
- add VtdIopEnable, VtdIgdEnable, and VtdIpuEnable UPDs in Fspm.h

TEST=Build and boot JSLRVP

Change-Id: I268eca1bcbbf26d4dc4ecf54d432cdb6ad49b4eb
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47500
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 18:26:58 +00:00
Angel Pons 27f606b721 doc/relnotes/4.13: Remove duplicated `CPU`
Change-Id: Ib423a0d4341560301138e06b00a704c2baae4867
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47767
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 17:13:22 +00:00
Nico Huber 2421b88381 doc/relnotes/4.13: Fix random spelling mistakes
Change-Id: I7486124fbe43f15bfbbf0875a58935133639b35f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 16:32:13 +00:00
Furquan Shaikh a8e7b45816 Doc/relnotes/4.13: Add details about resource allocator v4
This change adds details about the new resource allocator v4 in
coreboot to the release notes for 4.13.

Change-Id: I7071bdf0faffda61fc5941886c963181939c07e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-19 16:23:46 +00:00
Nico Huber 900c3a32a3 doc/relnotes/4.13: Add changes to log-level configurability
Change-Id: Ia7ef57d20ea5099f344ccbf58d76597cb0e82c85
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 16:22:23 +00:00
Werner Zeh 2609eaaa8f src/drivers/i2c/rx6110sa: Omit _HID temporarily
The current HID "RX6110SA" does not comply with the ACPI spec in terms
of the naming convention where the first three caracters should be a
vendor ID and the last 4 characters should be a device ID. For now
there is a vendor ID for Epson (SEC) but there is none for this
particular RTC. In order to avoid the reporting of a non ACPI-compliant
HID it will be dropped completely for now.

Once Epson has assigned a valid HID for this RTC, this valid HID will be
used here instead.

Change-Id: Ib77ffad084c25f60f79ec7d503f14731b1ebe9e2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47706
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 15:04:33 +00:00
Kyösti Mälkki b8c7ea0f69 ACPI S3: Replace acpi_is_wakeup()
It was supposed to return true for both S2 and S3, but
level S2 was never stored in acpi_slp_type or otherwise
implemented.

Change-Id: Ida0165e647545069c0d42d38b9f45a95e78dacbe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-19 14:48:31 +00:00
Kyösti Mälkki 67a2507c78 ACPI S3: Remove unused acpi_is_wakeup_s4()
Change-Id: Id4728b637c784ee2bff7b175e13f4c10419b7f1b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-19 14:44:27 +00:00
Felix Held 4e56f75bb5 soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig
By renaming the AMD SOC common Kconfig file the wildcard to source all
AMD SoC-specific Kconfig files won't match to it and it can be sourced
after all SoC-specific Kconfig files in the sub-directories are sourced.
This change allows adding new SoCs without having to edit the soc/amd
Kconfig file.

Change-Id: Iaaa5aad23eb6364d46b279101f3969db9f182607
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-19 14:29:14 +00:00
Felix Singer 1268d4081e doc/relnotes/4.13: Add note about PCI bus mastering Kconfig options
Change-Id: I66a636f554d18e08a209a7cfd6a59cf13a88f2e1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47409
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 13:23:30 +00:00
Felix Singer f5ce4b3778 mb/clevo/cml-u/l140cu: Extend Kconfig option text with L141CU
Extend the Kconfig option text of L140CU with L141CU since the hardware
of both is equal.

Change-Id: If0e5061fc345208688a678a4cdf7c5ecaf47c17d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-11-19 13:22:48 +00:00
Felix Singer f7b8cb542e mb/clevo/cml-u: Add comment to board selection
Change-Id: I531865416b1bf9c5a73c809590059e7d7c8f373a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47715
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 13:22:38 +00:00
Wisley Chen 35010ef9c5 mb/google/volteer: Add new Audio option to FW_CONFIG
Volteer has a new Audio option in FW_CONFIG. This patch adds
support for it and when enabled, programs GPIO pins for I2S
functionality.

BUG=b:171174991
TEST=emerge-volteer coreboot

Change-Id: I85bc37980957a3fb6c795858a4e4f44f3e3cc332
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-18 21:55:00 +00:00
Matt Ziegelbaum a04072c917 mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented
Ambassador is similar to puff. This change matches the
PcieRpSlotImplemented configuration with Puff's, originally made for
Puff in https://review.coreboot.org/c/coreboot/+/39986.

Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-18 18:48:29 +00:00
Matt Ziegelbaum 552133e161 mb/google/hatch/var/ambassador: update fan table and tdp config
Fan table: provided by the ODM (see attachment in bug) based on
measurements with EVT unit.

BUG=b:173134210
TEST=flash to DUT

Change-Id: I9f727f0f7e2eb7fe70385ebc843558d51e1860c5
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-18 18:48:21 +00:00
Subrata Banik ceee6d87ca mb/intel/adlrvp: Update HPD1/2 GPIO as per latest schematics
HPD_1: A19 -> E14
HPD_2: A20 -> A18

Change-Id: Idf3c8f4931bf8364bb9216a9369df7e05dcde047
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-18 18:13:23 +00:00
Felix Held 91797c1416 include/device/pci_ids: add model number to AMD GBE controller
Change-Id: I4499c383e63cd12a0fc11efd94ef396d9ad23789
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-18 17:54:22 +00:00
Felix Held b9fe66e0ab include/device/pci_ids: add model number to PCIe port and bus devices
Different models within family 17h have different PCI IDs for their PCIe
GPP port and internal bus devices.

Change-Id: I386df908ce5451b4484be2a2e4a9018c3d47d030
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-18 17:54:10 +00:00
Felix Held 0e5dde5d99 include/device/pci_ids: add model number to data fabric devices
Different models within family 17h have different PCI IDs for their data
fabric PCI devices.

Change-Id: I44f8d32c950710e962dc519495b08c92f357ed20
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-18 17:54:02 +00:00
Felix Held 52ba30226c include/device/pci_ids: deduplicate AMD family 17h northbridge ID
The code uses PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB instead;

Change-Id: Ia88550d377643741f78ff068e57d6a2d783306f3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-18 17:53:52 +00:00
Felix Held 9a8e8c605a include/device/pci_ids: use the right device ID for AMD Picasso GPU
The code that uses the GPU device ID uses the correct ATI vendor ID, but
the description wrongly used AMD as vendor. In the AMD APUs the GPU PCI
device and the corresponding audio controller use the ATI PCI vendor ID
while all other PCI devices in the SoC use the AMD PCI vendor ID.
Also move the two entries in a separate section right below the one they
were in.

Change-Id: Ia0b5bd4638f5b07c487f223321872563b36337e9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-18 17:53:45 +00:00
Felix Held 5a82e1dc20 soc/amd/common: remove SOC_AMD_COMMON_BLOCK Kconfig symbol
SOC_AMD_COMMON needs to be selected to be able to select
SOC_AMD_COMMON_BLOCK which only includes the Kconfig files from the
function block sub-folder. Removing SOC_AMD_COMMON_BLOCK and the
corresponding Kconfig file and make SOC_AMD_COMMON include all Kconfig
files from the sub-folders simplifies this a bit.

Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-18 16:08:17 +00:00
Kyösti Mälkki 561b5cfe42 ACPI S3: Do some minor cleanup
Drop extra function in the middle and adjust the post_code()
to happen right before jump to wakeup vector.

Change-Id: I951c3292f5dbf52a58471da9de94b0c4f4ca7c20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42613
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18 13:36:37 +00:00
Nikolai Vyssotski 9004f1d99d superio/smsc/sio1036: Support 16-bit IO port addressing
SMSC/Microchip 1036 can be strapped to 4E/4D and 164E/164D so make 
source code support 16 bits addressing.

Change-Id: I2bbe6f5b6dbd74299b34b0717e618dc736e7ad6f
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-18 13:12:11 +00:00
Wenbin Mei cdba52aaa9 mb/google/asurada: Configure pins mode for SD
Configure the pins for SD to msdc1 mode and change the driving
value to 8mA. Enable VCC and VCCQ power supply for SD.

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I11151c659b251db987f797a6ae4a08a07971144b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-18 06:13:41 +00:00
Yidi Lin dfd5ccee75 mb/google/asurada: Implement enable_regulator and regulator_is_enabled
SD Card driver needs to access two regulators - MT6360_LDO5 and
MT6360_LDO3. These two regulators are disabled by default.

Two APIs are implemented:
- mainboard_enable_regulator: Configure the regulator as enabled/disabled.
- mainboard_regulator_is_enabled: Query if the regulator is enabled.

BUG=b:168863056,b:147789962
BRANCH=none
TEST=emerge-asurada coreboot

Change-Id: I391f908fcb33ffdcccc53063644482eabc863ac4
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46687
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18 06:13:26 +00:00
Yidi Lin 99e6dd9f74 ec/google/chromeec: Add more wrappers for regulator control
google_chromeec_regulator_enable is for enabling/disabling
the regulator. google_chromeec_regulator_is_enabled is for
querying if the regulator is enabled.

BUG=b:168863056,b:147789962
BRANCH=none
TEST=emerge-asurada coreboot

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ia804242042b0026af19025a0c4a74b3ab8475dab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-18 06:13:12 +00:00
Yidi Lin 9ee02095fa mb/google/asurada: Implement board-specific regulator controls
Currently, five regulator controls are implemented for DRAM
calibration and DVFS feature.

The regulators for VCORE and VM18 are controlled by MT6359.
The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360
via EC.

BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-18 06:13:03 +00:00
Hsin-Hsiung Wang 9247d12839 soc/mediatek/mt8192: add pmic MT6315 driver
MT6315 is a buck converter for Mediatek MT8192 platform.
Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616.

BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I6b47473ee5d56a197bd21d4ab9b539d9663b6636
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45400
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18 06:12:50 +00:00
Hsin-Hsiung Wang ed7bb85031 soc/mediatek/mt8192: add pmic MT6359P driver
MT6359P is a PMIC chipset for Mediatek MT8192 platform.
Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205.

BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I62f69490165539847b8b7260942644533b15285b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45399
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18 06:12:25 +00:00
Hsin-Hsiung Wang 22f8370def soc/mediatek/mt8192: add pmif driver
MT8192 uses power management interface (PMIF) to access pmics by spmi
and spi, so we add pmif driver to control pmics.

BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I32fc28f72d9522133baa06f9d67c383f814d862c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45398
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18 06:12:09 +00:00
Joel Kitching ec6cff2f20 vboot: stop implementing VbExDisplayScreen
This function is no longer required to be implemented since
EC/AUXFW sync was decoupled from vboot UI.  (See CL:2087016.)

BUG=b:172343019
TEST=Compile locally
BRANCH=none

Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I43e8160a4766a38c4fa14bcf4495fc719fbcd6c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-18 05:49:46 +00:00
Jamie Ryu 6ecd4c65e7 mb/google/volteer: Update flashmap descriptor to add ME_RW_A/B region
The current CSE firmware update implementation adds CSE RW binary to
FW_MAIN_A/B and this increases the boot time due to the size increase
of these regions leading to higher loading and hashing time.

To mitigate this issue, CSE RW binary is moved from FW_MAIN_A/B to new
region, ME_RW_A/B under RW_SECTON_A/B, and this updates the flashmap to
add ME_RW_A/B region for CSE RW binary.

BUG=b:169077783
TEST=build with cse rw binary, flash and verify volteer2 boots to OS.
Verify me_rw binary is added to ME_RW_A/B region.

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46431
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18 01:26:52 +00:00
Sridhar Siricilla 361e364635 soc/intel/common: Move CSE RW into new FMAP region to optimize boot time
CSE RW blob which will be used by coreboot to update CSE's RW partition,
is packed part of FW_MAIN_A and FW_MAIN_B. This will increase the size of
FW_MAIN_A and FW_MAIN_B. So, accordingly load and hash calculation of
FW_MAIN_A (or FW_MAIN_B) increases during verstage. It increases the boot
time by around 300ms.

The patch address the boot time by pulling CSE RW blob outside of
FW_MAIN_A and FW_MAIN_B. So, it creates new FMAP region within
RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions
(ME_RW_A and ME_RW_B) as a CBFS file.

Boot Time Measurement details when CSE RW blob is added in the
ME_RW_A and ME_RW_B.
 --------------------------------------------------------
| Platform |   Old Boot Time      |   New Boot Time      |
 --------------------------------------------------------
| JSL      |  1.3s                |   1.06s              |
 --------------------------------------------------------
| TGL      |  1.63s               |   1.36s              |
 --------------------------------------------------------

Changes:
 1. Makefile change to accommodate CSE RW blob into  ME_RW_A/ME_RW_B
 2. Kconfig change to define CBFS name and default file name for RW blob
    metadata.
 3. CSE Lite Driver

BUG=b:169077783
TEST=Verified on JSL & TGL platforms

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-18 01:26:44 +00:00
V Sowmya 0759346cd6 mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update
This patch modifies flash layout to add ME_RW_A/B to add
the CSE RW blob and also enable the CSE RW update feature for
JSLRVP

BUG=b:169077783
TEST= Built for jslrvp. Verified that CSE RW and metadata files
      are included in cbfs.

Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-18 01:26:37 +00:00
V Sowmya f2e8a7ae6b mb/google/dedede: Modify flash layout to add ME_RW_A/B regions
Existing implementation adds the CSE RW update binary to FW_MAIN_A/B
regions and this has significant impact on boot time due to the
increase in the size of these regions leading to higher loading
and hashing time.

This patch modifies flash layout to add new ME_RW_A/B fmap regions
in the RW_SECTION_A/B.

BUG=b:169077783
TEST= Built for dedede. Verified that CSE RW binary is added to the
CSE_RW_A/B fmap region.

Change-Id: I23a3e22a569488b39beb4d12f5b6309c7c742992
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-18 01:26:30 +00:00
V Sowmya 338b83c7b8 soc/intel/common: Generate the CSE RW metadata and add to FW_MAIN_A/B
In the existing implementation CSE RW metadata file is generated by
scripts and to avoid incompitable issues between coreboot and the
scripts this patch adds the follwing changes,
* Move the metadata generation to the coreboot Makefile.
* Add CBFS component type struct to create a metadata file during
  the compile time.
* Extract the CSE RW version from SOC_INTEL_CSE_RW_VERSION config
  and update the major, minor, hotfix and build versions using the
  compile time flags.
* Compute the hash of CSE RW binary in hex format using the openssl
  and use the HASH_BYTEARRAY macro to convert the 64 character hex
  values into the array.
* Add the me_rw.metadata cbfs file to FW_MAIN_A and FW_MAIN_B
  regions.

BUG=b:169077783
TEST= Built for dedede. Verify that metadata file was generated
and added to the FW_MAIN_A/B. Extracted it using cbfstool and
verfied that metadata was generated properly.

Change-Id: I412581400a9606fa17cf4398faffda923f07b320
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-18 01:26:23 +00:00
V Sowmya f99055266b soc/intel/common: Add Kconfig to enable the CSE FW Update feature
Add the Kconfig to enable the CSE FW Update feature and also to
ensure all the configs are set by the mainboards to enable this
feature.
This config by default disables the CSE FW update feature for JSL
and TGL platforms. It will be enabled after splitting and including
the CSE RW and CSE RW metadata blobs in the CBFS.

BUG=b:169077783

Change-Id: I12810031224f79aba8a4057725ae0ed5a9b36d7e
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-18 01:26:15 +00:00
V Sowmya 187f06f07e soc/intel/common: Add Kconfig for CSE RW firmware version
This patch adds a kconfig SOC_INTEL_CSE_RW_VERSION to pass the
CSE RW firmware version from the mainboard. This will be extracted
by makefile to update the cse_rw_metadata structure.
Right now the required tool to extract the CSE RW version from
the blob is still under development and after the official version
of the tool is released, version will be extracted by parsing the
CSE RW blob.

BUG=b:169077783

Cq-Depend: chrome-internal:3402224, chrome-internal:3397863,
chromium:2473603, chromium:2473603, chromium:2535950
Change-Id: I62691ee3ede7d4cd21f821381f5d1519f9061fd9
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47430
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18 01:26:08 +00:00
Tim Chen f7140c425a mb/google/dedede/var/metaknight: Add touchscreen settings
Add Elan and Goodix touchscreen settings.

BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware

Change-Id: Ib2acd31a8076533c3b927d37127e7d27bac0bb57
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-17 20:43:43 +00:00
Marc Jones b7e591e2da soc/intel/xeon_sp: Fix SKX SATA drive boot issue
SKX FSP doesn't support X2APIC setup, but CPX does. The CPX DMAR
table needs the X2APIC opt out flag set. This fixes the hang loading
a kexec'd kernel. The change is easy to see in the coreboot output:
[DMA Remapping table] Flags: 0x3
or in the DMAR ACPI table.

Change-Id: Iec977c893b70e30875d9a92f24af009c1e90389e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-17 18:20:46 +00:00
Martin Roth d5c3d9ca82 mb/google/zork: Power off fingerprint sensor on shutdown
When the system shuts down, turn the fingerprint sensor off. This sets
the GPIOs correctly for the next boot.  The fingerprint sensor was
previously left on, and was just powering down when the rails went low.

On suspend, the fingerprint sensor stays awake and puts itself in a low
powerstate mode based on the SLP_Sx_L pin states.

BUG=b:171837716
TEST=Fingerprint sensor still works after S3, GPIO state on the boot
following a shutdown is low.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3837b58372d8f4a504535e76bd21c667d68f8995
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-17 16:54:16 +00:00
Elyes HAOUAS 6aaf7db719 src: Add missing 'include <console/console.h>'
"Die()" needs <console/console.h>.

Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-17 09:50:24 +00:00
Elyes HAOUAS 27718ac87f src: Add missing 'include <console/console.h>'
"printk()" needs <console/console.h>.

Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-17 09:01:14 +00:00
James Chao add3a06268 mb/google/reef/variants/: add Naya NT6AN256T32AV-J2
BUG=b:172843935
BRANCH=coral
TEST=emerge-coral coreboot chromeos-bootimage

Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com>
Change-Id: I70195acc33218d3ad4c77acfdbc8f6ed93ab144e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47382
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-17 08:48:54 +00:00