Commit Graph

37657 Commits

Author SHA1 Message Date
Daniel Kang b4b8c1d174 mb/google/volteer: Add "i2c-allow-low-power-probe" property for
cameras

There is a patch https://lkml.org/lkml/2020/9/3/235 which allows i2c
device can support driver probe without power up the device.
In order to support this, need add coreboot add
"i2c-allow-low-power-probe" property.

BUG=b:169058784
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check it blinks. It should not blink.

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I46f90ff8d412b18c7ee4bd7f22f9a7db771eb84f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-09-29 17:18:27 +00:00
Patrick Rudolph dc2f0e39ae cpu/qemu-x86/car: Move long mode entry right before c entry
This fixes non-emulation platforms as those are using 32bit code
after the bootblock_crt0 entry, like setting up CAR and updating
microcode, which isn't yet converted to support long mode.

This is a noop for the only supported x86_64 platform and all
x86_32 platforms.

Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29 12:27:04 +00:00
Krishna Prasad Bhat 20f580b6f9 soc/intel/jasperlake: Add IGD, MCH Device ID
Add IGD Device ID and MCH Device ID for Jasperlake.
Reference is taken from Jasperlake EDS volume 1(Document Number:
613601).

TEST=Build and boot Jasperlake platform.

Change-Id: I00ee7950ffa378b428a76bf367a9a05ab287e7ed
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29 06:52:40 +00:00
Michael Niewöhner 8e60571f6e mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader
PcieRpSlotImplemented should only be set to 1 for PCIe ports
implementing a PCIe slot. Drop it for the on-board card reader.

Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29 06:01:34 +00:00
Angel Pons c88a4794c8 nb/intel/gm45: Answer question about conversion stepping A1
The datasheet briefly mentions what this mysterious stepping is about.

Change-Id: I5bc1040b74fcdf3822b15e7564f8e4ccebd7d45f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45449
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29 06:00:49 +00:00
Arthur Heymans 2f7d4c362c cpu/x86/smm/smihandler.c: Implement smm_get_save_state()
This will be used in common save_state handling code.

Change-Id: I4cb3180ec565cee931606e8a8f55b78fdb8932ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44320
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29 05:59:59 +00:00
Arthur Heymans ac0d2ee2de cpu/x86/smm/smmhandler.c: Get revision using C code
This allows to remove some assembly code.

Tested with QEMU Q35 to still print the revision correctly.

Change-Id: I36fb0e8bb1f46806b11ef8102ce74c0d10fd3927
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29 05:59:37 +00:00
Maulik V Vaghela 258ceb7507 mb/intel/jslrvp: Update PMC as hidden device
This change allows treating the PMC as a 'hidden' PCI device on
JasperLake, so that the MMIO & I/O resources can be exposed as
belonging to this device, instead of the system agent and LPC/eSPI.

Original patch for jasperlake SoC here:
CB:42018

This change was missing for JasperLake rvp board.

TEST=Checked PMC init function is called and also checked PCI resource
for PMC device 1f.2.

Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29 03:48:27 +00:00
Pratik Prajapati 823e73e143 soc/intel/common: Add config option to enable TME/MKTME
Add config option to enable TME/MKTME.
The spec is available at: "https://software.intel.com/sites/
default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption-
Spec.pdf"

Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I181aed2bf4a79005fe42e3e133b5faee91201dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29 03:47:38 +00:00
Maxim Polyakov c65f1f95dc util/intelp2m/apl: Remove unused plat-spec function
Change-Id: I42074387a08b66b038ad2939f31be263eaa3af0e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44473
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 15:44:23 +00:00
Maxim Polyakov be96c62b1e mb/google/fizz/endeavour/gpio: Reflow long lines
Use the 96 character limit.

Change-Id: I865288051869e50602a579a6999b1b23ef68ec2f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 15:44:04 +00:00
Subrata Banik ac17fad84e Revert "soc/intel/xeon_sp: Improve performance efficiencies"
This reverts commit d51449d017.

Reason for revert: Causing compilation issue as below

src/soc/intel/xeon_sp/cpx/acpi.c: In function 'acpi_create_rhsa':
src/soc/intel/xeon_sp/cpx/acpi.c:825:4: error: initialization
discards 'const' qualifier from pointer target type
[-Werror=discarded-qualifiers]
    &hob->PlatformData.IIO_resource[socket];
    ^
Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44998
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 14:28:22 +00:00
Tom Hiller 9e7c99dcae Intel GBE 82579LM bincfg set and spec
Using bincfg, generate Intel 82579LM GBE region firmware.

* Intel 82579LM is used in Lenovo models including x220 and x230.
* PXE is disabled.
* Intel 82579V variant could be generated with a few modifications to
set.  Noted in set file comments.

Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28 09:44:45 +00:00
Maxim Polyakov fd76c5e540 util/intelp2m: Remove unnecessary tabs
Change-Id: I5aa4b9ac4fa1ceb6f3c2ade214d47b29246ece55
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-28 09:42:24 +00:00
Eric Lai 5f43369bec mb/google/octopus/variants/fleex: Only do LTE power off for LTE sku
Only do LTE power off for LTE sku in order to save extra 130ms delay
for non-LTE sku.

BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2020-09-28 09:41:55 +00:00
Elyes HAOUAS 40ed6f2f78 mb/clevo/cml-u/Kconfig: Remove MAINBOARD_SMBIOS_PRODUCT_NAME
MAINBOARD_SMBIOS_PRODUCT_NAME is duplicated.

Change-Id: I011f83c4d4e0657256839db207bfd1517922744c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-28 09:41:04 +00:00
Raul E Rangel 96c704a167 soc/amd/picasso: Set eMMC preset UPDs
Now that all boards have bootable driver strengths and init frequency,
we can pass them to FSP.

BUG=b:159823235
TEST=Boot ezkinil to kernel and print presets.

SDHC0x8F0 Initialization 3.3V or 1.8V => 0x03ff
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x3ff: SdClkFreq
SDHC0x8F2 Default Speed 3.3V => 0x0004
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x4: SdClkFreq
SDHC0x8F4 High Speed 3.3V => 0x0002
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x2: SdClkFreq
SDHC0x8F6 SDR12 1.8V => 0x0008
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x8: SdClkFreq
SDHC0x8F8 SDR25 1.8V => 0x0004
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x4: SdClkFreq
SDHC0x8FA SDR50 1.8V => 0x0002
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x2: SdClkFreq
SDHC0x8FC SDR104 1.8V => 0x4000
 14 => 0x1 [A]: DvrStrength
 10 => 0: ClkGen
 00 => 0: SdClkFreq
SDHC0x8FE DDR50 1.8V => 0x0002
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x2: SdClkFreq
SDHC0x900 HS400 => 0x4000
 14 => 0x1 [A]: DvrStrength
 10 => 0: ClkGen
 00 => 0: SdClkFreq


Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fe5c0a5a5ecf292ce8703e9c9ea80b6f1b6440e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28 09:39:49 +00:00
Raul E Rangel 94be1f7399 mb/google/zork: Set eMMC presets
They should be tuned per board to get the best signal and boot time.

This fixes the HS400 preset, so it's correctly set to A. It also changes
the SDR50 and DDR50 presets to B. We can't boot correctly when DDR50 is
set to A.

I chose 1 as the init kHz value since that's what depthcharge uses to
calculate the init clock.

BUG=b:159823235
TEST=Boot Ezkinil and dump SDHCI preset registers.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28 09:39:39 +00:00
Raul E Rangel 5590d9aa75 soc/amd/picasso: Add eMMC driver strength and init kHz settings
This allows passing in the presets to FSP.

I will set the UPD values after all the zork boards have had their
presets correctly set. This way we don't override the UPD defaults with
0s.

BUG=b:159823235
TEST=Build test

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28 09:39:25 +00:00
Jonathan Zhang 60d800537b mb/ocp/deltalake: add LPC device entry in ACPI
PCH LPC device is on CSTACK. Add LPC ACPI device entry.

Without this change, following error message shows up in target OS
boot log:
ACPI BIOS Error (bug): Failure looking up [\_SB.PCI0.LPCB], AE_NOT_FOUND (20180105/dswload-211)
ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20180105/psobject-252)
ACPI Error: AE_NOT_FOUND, (SSDT:COREBOOT) while loading table (20180105/tbxfload-228)
ACPI Error: 1 table load failures, 1 successful (20180105/tbxfload-246)

Also TPM device is not created.

TESTED=Booted DeltaLake DVT, run following command in target OS:
[root@dhcp-100-96-192-153 ~]# dmesg | grep tpm
[    7.331890] tpm_tis MSFT0101:00: 2.0 TPM (device-id 0x1B, rev-id 16)

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I8614f6951389bd5c8f8f33522d0a9a9160ac3f66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-09-28 09:39:11 +00:00
Jonathan Zhang 1ba42a9ca2 soc/intel/xeon_sp/cpx: add ACPI name for CSTACK
Add ACPI name for CSTACK. The name is PC00 to match with ACPI table
generated.

The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment
does not support multiple PCIe stacks, eg. IIO stacks. For now, assign
the name to PCIe domain. In future, the name needs to be assigned to
CSTACK.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I24a6f29734452426218419cdcf66702edde96f46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-28 09:39:02 +00:00
Jonathan Zhang db202bad09 soc/intel/common/block/lpc: add acpi name
Add ACPI name for LPC device. The name matches with what is in
soc/intel/common/block/acpi/acpi/lpc.asl.

Since several Intel SOCs select CONFIG_SOC_INTEL_COMMON_BLOCK_LPC,
remove duplicated acpi name assignments.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If418c83caafe5d9e2af135a8946cbe5eb687b9ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28 09:38:39 +00:00
Jonathan Zhang 339fa7389b doc/mb/ocp: update deltalake server documentation
Upon completion of 2nd build/test/release cycle of Deltalake server
alternative firmware engineering, update the document.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I1806526bd477ed407bb7fd36c7fe4ce0e57b72f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28 09:37:57 +00:00
Jonathan Zhang 7614099b8e vc/intel/fsp/fsp2_0/CPX-SP: upgrade to ww38 FSP release
Intel CPX-SP FSP ww38 release made some changes to FSP-M header
file. Those changes do not need corresponding soc code change.

TESTED=built image with ww38 FSP RELEASE binary, booted DeltaLake
DVT to target OS.

Change-Id: I320c4a674f9f4d37c30ce6df510f18ad1ae057eb
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:37:01 +00:00
Eric Lai 58a706af96 mb/google/octopus/var/fleex: Use Wifi SAR table for non-LTE sku only
Use Wifi SAR table for non-LTE sku only.

BUG=b:169115341
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I086fa14a9f23e4a0fc0ef8085040219c932dbf17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45640
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 09:36:11 +00:00
Patrick Rudolph 0348bbe971 include/cpu/x86/tsc: Fix rdtsc on x86_64
The used assembler code only works on x86_32, but not on x86_64.
Use the inline functions to provide valid rdtsc readings on both
x86_32 and x86_64.

Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: Icf706d6fb751372651e5e56d1856ddad688d9fa3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-09-28 09:36:00 +00:00
Francois Toguo 597922ecb4 arch/x86/smbios: Add SMBIOS Thread Count
Add Thread Count in SMBIOS type 4 "Processor Information".
Modify Thread Count 2 according to SMBIOS spec, it should
be the number of threads per processor socket.

TEST="dmidecode -t4" to check.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I0e00ba706eecdc850a2c6a4d876a7732dcc8f755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:34:59 +00:00
Ravi Sarawadi f1a0049599 mb/volteer: Use Genesys Logic GL9755 for Delbin, Volteer2
Enable newly added PCIe Gen2 to SD 4.0 card reader controller GL9755
for Delbin and Volteer2.

BUG=b:166141961
TEST=Boot to kernel on Delbin, Volteer2 boards. Check PC10 in IDON.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I2589ab2334625ec0d20dbdd5f3a31d98235aad2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45708
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 09:34:39 +00:00
Patrick Rudolph 19a60a4b5d arch/x86/Kconfig: Move pagetables down by 4K
In case of 64K bootblock the pagetables don't fit, as the CBFS header
also needs a few bytes.

Fixes build error on platforms that use 64KiB bootblock.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37394
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 09:34:12 +00:00
Matt DeVillier 25a2ca9628 mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params
Some Librem Minis exhibit issues with 6Gbps SATA operation on certain
SSDs, setting the Receiver Equalization Boost Magnitude adjustment
resolves this, so limiting SATA speeds to 3Gbps is no longer needed.

Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues
booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7

Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:33:54 +00:00
Matt DeVillier b5eae2868b mb/purism/librem_skl: Enable and set SATA tuning params
Some Librems have issues with 6Gbps SATA operation on certain
SSDs, setting the Receiver Equalization Boost Magnitude adjustment
resolves this.

Test: build/boot Librem 15v3 with Crucial SATA SSD, observe no issues
booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7

Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:33:46 +00:00
nick_xr_chen 0d5ac7440a mb/google/volteer/variants/eldrid: Configure GPP_S4 and GPP_S5
GPP_S4 and GPP_S5 use as DMIC pins that need to be defined as NF2

BUG=b:168564129

Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2020-09-28 09:33:37 +00:00
Kevin Cheng 1f2c59b099 mb/google/volteer/var/terrador: Enable audio SMBIOS OEM string
It needs to use probe statement in overridetree.cb to enable the cache
of fw_config field implemented by cb:44782 and cb:44783.

BUG=b:161963281
TEST= dmidecode -t 11 shows correct audio fw_config.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
	String 1: DB_USB-USB4_GEN2
	String 2: AUDIO-MAX98373_ALC5682I_I2S_UP4

Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Change-Id: I68c19b67d945aaca3e9ebec87eb27a4b07e1a49e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28 09:33:28 +00:00
Kevin Chiu b521f8acc6 mb/google/zork: update telemetry settings for berknip
update telemetry to improve the performance.

BUG=b:168581158
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. pass AMD SDLE test

Change-Id: Ib93905cd89132664b06f2476e94494e96980642c
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28 09:33:00 +00:00
Christian Walter 90b0d85e73 Documentation/mainboard: Add Missing OCP Delta Lake Link
Change-Id: I379d6a7b72a0398c34ea8eeda09ccd663fc372ce
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:32:50 +00:00
Ren Kuo bf3466beb2 mb/google/dedede/var/magolor: apply DPTF setting
add tcc, critical, passive policy, and pl values from thermal team

BUG=b:168353037
TEST=build and verify by thermal tool

Change-Id: I887d494ff097a881d519a456f24578a278323051
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45453
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 09:32:38 +00:00
Ren Kuo 03e74ba5de mb/google/dedede/var/magolor: Add ACPI camera support
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU
2. add IPU/VCM/NVM/CAM0 in devicetree

BUG=b:166527568
TEST= build and verify function by cam ap on DUT

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Ica6aa8ddc03a1dab5b548a759825dd3a4de3101f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45329
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 09:32:31 +00:00
Karthikeyan Ramasubramanian e99d634ae2 mb/google/dedede/var/madoo: Clean-up static camera ASL file
Camera ACPI tables are generated at run-time for all variants of Dedede.

BUG=None
TEST=Build madoo variant.

Change-Id: Icb74c01a0a6dbc620466b64cd2b5652408ca41b9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-28 09:32:20 +00:00
Angel Pons 201b1a8380 soc/intel/common/../pmclib.h: Include <types.h>
This file uses `bool` and `size_t` types, so <stdint.h> isn't enough.

Change-Id: I8099142d92cc8ca6721f76522f3d30d4b6b9ee80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28 09:32:04 +00:00
John Zhao 4792f8f5eb superio/common: Fix NULL pointer dereferences
Coverity detects the dev->link_list NULL pointer dereferences while
calling report_resource_stored. Add sanity check for dev->link_list to
prevent NULL pointer dereference.

Found-by: Coverity CID 1419488
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I953a6524fff509a7833896392b25a3245c8cd705
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:31:28 +00:00
nick_xr_chen d8279fdb6d mb/google/volteer: Improve Eldrid Port 1 USB2 Eye Diagram
In order to pass DB type-C USB2 eye diagram, DB USB2 PHY register needs 
to be overridden.

port#1
PortUsb20Enable=1
Usb2PhyPetxiset=7
Usb2PhyTxiset=7
Usb2PhyPredeemp=3
Usb2PhyPehalfbit=0

BUG=b:169105751
Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: If076c644783fa2992ac062d6469f9c49e6d5ff24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28 09:31:18 +00:00
Felix Singer 1bdbcd7510 azalia_device.h: Add new macro to configure pins as NC
Change-Id: I740d0d756599688165458a9c6e925d5d94754bb2
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45604
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 09:30:57 +00:00
Michael Büchler ba49d859ee mb/acer/g43t-am3: add Acer G43T-AM3 mainboard
Adds a new port for the Aspire G43T-AM3. It is from an Aspire M3800
desktop model of which I only own the mainboard. The silkscreen label
calls it "G45T/G43T-AM3 V:1.0". In DMI data it is additionally called
Acer EG43M.

The Aspire M5800 model seems to use the same mainboard. The BIOS you can
download from Acer is identical for both.

Various similar mainboards by Acer exist: G41T-AM, G43T-AM, G43T-AM4,
Q45T-AM, to name a few. ECS has some models that are obiously based on
the same design, e.g. G43T-WM and G43T-M.

This model is a microATX-sized board with an LGA 775 socket, four DDR3
DIMM slots, one PCIe x16 slot, one PCIe x1 slot and two PCI slots based
on the Intel G43 chipset.

The port was started by copying mb/intel/dg43gt (not going to lie here)
and adapting things by looking at dumps from the system when running
with the vendor BIOS. Serial console output is possible by soldering to
a point at the corresponding Super I/O pin.

The service manual for the board was helpful for setting the correct PCI
IRQ links. It can be found publicly on the internet as the "Acer Aspire
M3800 Service Manual".

Working:
- CPUs from Pentium Dual-Core E2160 to Core 2 Quad Q9550 at FSB1333
- Native raminit
- All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
- PS/2 mouse
- PS/2 keyboard (needs CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500)
- USB ports (8 internal, 4 external)
- All six SATA ports
- Intel GbE
- Both PCI ports with various cards (Ethernet, audio, USB, VGA)
- Integrated graphics (libgfxinit)
- HDMI and VGA ports
- boot with PCIe graphics and SeaBIOS
- boot with PCI VGA and SeaBIOS
- Both PCIe ports
- Flashing with flashrom
- Rear audio output
- SeaBIOS 1.14.0 to boot slackware64
- SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS)
- Temperature readings (including PECI)
- Super I/O EC automatic fan control
- S3 suspend/resume
- Poweroff

Not working:
- Resource issues with the VGA BIOS of a PCI rv100-based card
- Super I/O voltage reading conversions

Untested:
- The other audio jacks or the front panel header
- On-board Firewire
- EHCI debug
- VBT (was extracted and added, but don't know how to test)
- Super I/O GPIOs

Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:30:04 +00:00
John Zhao d51449d017 soc/intel/xeon_sp: Improve performance efficiencies
Coverity detects performance inefficiencies as IIO_RESOUCE_INSTANCE
structure (size 623 bytes) is PASS_BY_VALUE. Fix it with
PASS_BY_REFERENCE.

Found-by: Coverity CID 1432759
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9ae9ae38fe2c13c5433aa5e1dcbb30ebd30622ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28 09:29:03 +00:00
Sumeet R Pawnikar 06b35e5ced mb/intel/tglrvp: Add DTT support for tglrvp
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board.
Set power limits and CPU sensor thresholds for DTT based thermal control.

BRANCH=None
BUG=None
TEST=Build and boot on tglrvp board

Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-28 09:27:17 +00:00
Iru Cai 27dc761d08 ec/hp/kbc1126: Support not putting EC firmware in CBFS
For mainboards using the HP KBC1126 EC interface, but with a different
EC implementation, we don't put the EC firmware in the CBFS image. Add
a Kconfig option to prevent the build system warning on not inserting
the EC firmware.

After this change, building coreboot for EliteBook Folio 9480m will
not have a warning on not inserting the EC firmware.

The build system still builds a working coreboot image for EliteBook
2560p, and gives a warning if not choosing to insert the EC firmware.

Change-Id: I3be83a13d138d3623064ef2803f3e3a340207ead
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-28 09:26:54 +00:00
Nico Huber 90381231ea soc/intel/skl: Fix error code of send_global_reset()
With commit f2eb687d19 (soc/intel/{cnl,icl,skl,tgl,common}: Make
changes to send_heci_reset_req_message()) the return value was
changed on a single path. Update the other paths too, even though
it's the discouraged 0-is-failure.

Change-Id: I179a6a4b1e13565dd58c908eb2a9725052a4de9d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28 09:26:10 +00:00
Chris Wang 6dbf4c8f03 mb/google/vilboz: update telemetry settings
update the telemetry setting for second SDLE testing(for APU power adjusting).
Those values are used to power calibration the APU power and achieving
the best performance.

BUG=b:160698427
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44804
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 09:25:46 +00:00
John Zhao 19e22f554e drivers/spi: Check return value for error handling
Coverity detects calling function spi_sdcard_do_command without checking
return value. Fix this issue by checking return value for error
handling.

Found-by: Coverity CID 1407737
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie0d28806b5c0b4c6d509e583d115358864eeff80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28 09:24:33 +00:00
Evgeny Zinoviev 920d2b77f2 cpu/intel/206ax/acpi.c: Fix get_cores_per_package
Current implementation uses CPUID 0Bh function that returns the number
of logical cores of requested level. The problem with this approach is
that this value doesn't change when HyperThreading is disabled (it's in
the Intel docs), so it breaks generate_cpu_entries().

- Use MSR 0x35 instead, which returns the correct number of logical
  processors with and without HT.

- Rename the function to get_logical_cores_per_package, which is more
  accurate.

Tested on ThinkPad X220 with and without HT.

Related to CB:29669.

Change-Id: Ib32c2d40408cfa42ca43ab42ed661c168e579ada
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:24:11 +00:00