Nothing can actually use this as the EC cannot speak
using baytrail's SERIRQ protocol. Also, the voltage
bridge is going away so nothing will be hooked up to it.
Therefore disable this it.
BUG=chrome-os-partner:24693
BRANCH=rambi
TEST=Built and booted.
Change-Id: I406bb9c227578ec0a75eaf67143b3b27cb7880ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182082
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5042
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Problem with UMA region allocation was fixed when MTRRs changed to use
memrange implementation.
Change-Id: I420dac30de2836a91596d81f88bb45b46f248532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5719
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Short list of known issues for this patchset:
* Suspend/Resume - does not work
* Combi pci card for SD/MMC card reader with IEEE1394 - not found
* Shutdown - sometimes does not work as expected
* At least mysterious harddrive i/o
Change-Id: Iaba8d1f5e471cfeca20d82f4e1b416641e1f2ae9
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/5672
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
This improves boot time in 2 ways for a firmware upgrade:
1. Normally MRC would detect the S0 state without an MRC cache
even though it's told to the S5 path. When it observes this
state a cold reset occurs. The cold reset stays in S5 for
at least 4 seconds which is time observed by the end user.
2. As the EC was running RW code before the reset after firmware
upgrade it will still be running the older RW code. Vboot will
then reboot the EC and the whole system to put the EC into RO
mode so it can handle the RW update.
The issues are mitigated by detecting the system is in S0 with
no MRC cache and the EC isn't in RO mode. Therefore we can do the
reboot without waiting the 4 secs and the EC is running RO so
the 2nd reboot is not necessary.
BUG=chrome-os-partner:24133
BRANCH=rambi,squawks
TEST=Booted. Updated firmware while in OS. Rebooted. Noted the
EC reboot before MRC execution.
Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182061
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5040
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
It's helpful to have a generic function that will tell
the EC to reboot if the EC isn't running a specified
image. Add that and implement google_chromeec_early_init()
to utilize the new function still maintaing its semantics
of if recvoery mode is enabled the EC should be running its
RO image. There is a slight change in that no communication
is done with the EC if not in recovery mode.
BUG=chrome-os-partner:24133
BRANCH=rambi,squawks
TEST=Built and boot with recovery request. Noted EC reboot.
Change-Id: I22240f6a11231e39c33fd79796a52ec76b119397
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182060
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5039
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Added a method in each temp sensor to disable the aux trip points
and then a wrapper function to call this method for each enabled
temperature sensor.
The event handler function is changed to not use a switch statement
so it does not need to be serialized. This was causing issues
with nested locking between the global lock and the EC PATM mutex.
Some unused code in temp sensors that was added earlier is removed
and instead a critical threshold is specified in _CRT.
The top level DPTF device _OSC method is expanded to check for the
passive policy UUID and initialize thermal devices. This is done
for both enable and disable steps to ensure that the EC thermal
thresholds are reset in both cases.
Additionally the priority based _TRT is specified with TRTR=1.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, load esif_lf kernel drivers and start
esif_uf application. Observe that temperature thresholds are set
properly when running 'appstart Dptf' and that they are disabled
after running 'appstop Dptf'
Change-Id: Ia15824ca42164dadae2011d4e364b70905e36f85
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182024
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5037
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Set critical temperature thresdholds to 70C. This will cause DPTF
framework to shut down the system so it may need to be higher or
lower but will need some testing.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, start DPTF framework and observe it
using specified critical thresholds.
Change-Id: Ibbf6d814295eb5ff006cb879676b7613f5eb56a3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182025
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5038
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The PATx methods will be passed a temperature in deci-kelvin,
so it needs to be converted back to kelvin before being sent
to the EC.
The PAT disable method is changed to take the temperature ID
as an argument so individual sensors can be disabled.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, load esif_lf kernel drivers and
esif_uf userspace application. Start and stop DPTF and see
that temperature thresholds are set to sane values.
Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182023
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5036
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Remove some unused functions from CPU participant that were
confusing the userland component since the CPU does not have
an ACPI managed sensor.
- Guard the charger participant with an ifdef so it can be
left out if not supported.
- Use the EC methods for setting auxiliary trip points and for
handling the event when those trip points are crossed.
- Add _NTT _DTI _SCP methods for thermal sensors. I'm not
clear if these are required or not but they seem to be expected
by the other DPTF framework components.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi and load ESIF framework
Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181662
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5028
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The EC now supports two auxiliary programmable trip points for
thermal monitoring. These are expected to be used by DPTF and
need to be exported.
In order to support these the header was updated from the latest
chrome ec source.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I257d910daac4e36280c0cecf4129381a32ffcb9a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5027
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The SMI on TCO timer timeout policy was copied from other
chipsets. However, it's not very advantageous to have
the TCO timer timeout trigger an SMI unless the firmware
was the one responsible for setting up the timer.
BUG=chromium:321832
BRANCH=rambi,squawks
TEST=Manually enabled TCO timer. TCO fires and logged in
eventlog.
Change-Id: I420b14d6aa778335a925784a64160fa885cba20f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181985
Reviewed-on: http://review.coreboot.org/5035
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The PMC in baytrail maintains an additional set
wake status in memory-mapped registers. If these
bits aren't cleared the device won't be able to
go to S5 or S3 without being immediately woken up.
Therefore clear these registers.
BUG=chrome-os-partner:24913
BRANCH=rambi,squawks
TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work
correctly.
Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181984
Reviewed-on: http://review.coreboot.org/5034
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
When CONFIG_ELOG is selected the reset, power, and wake
events are logged in the eventlog.
BUG=chrome-os-partner:24907
BRANCH=rambi,squawks
TEST=Various resets and wake sources. Interrogated eventlog
to ensure results are expected.
Change-Id: Ia68548562917be6c2a0d8d405a5b519102b8c563
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181983
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5033
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The memory reference code doesn't maintain some of
the registers which contain valuable information in order
to log correct reset and wake events in the eventlog. Therefore
snapshot the registers which matter in this area so that
they can be consumed by ramstage.
BUG=chrome-os-partner:24907
BRANCH=rambi,squawks
TEST=Did various resets/wakes with logging patch which
consumes this structure. Eventlog can pick up reset
events and power failures.
Change-Id: Id8d2d782dd4e1133113f5308c4ccfe79bc6d3e03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181982
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5032
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
While backing out the empty pc80 keyboard struct we encountered some
special cases where chip.h is used for other purposes. Deal with these
cases.
Change-Id: Ib11a46cfd14d050d5daa213623b9d8a401c06410
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5621
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is a empty struct that has propagated through the superio's & ec's
but really does nothing. Time to get rid of it before it adds yet more
cruft. However, since this touches many superio's at once we do this in
stages by first changing the function type to be a pure procedure.
Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5617
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.
Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The SoC needs to provide a 32k clock signal SUSCLK for
some modems to work properly, so this enables the signal.
BUG=chrome-os-partner:24425
TEST=Manual, check SUSCLK pin with a scope.
Change-Id: Ibc0d5bb38a2c3e16f381dfc256097fdced67fd1c
Reviewed-on: https://chromium-review.googlesource.com/180101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5722
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Tested-by: build bot (Jenkins)
eMMC CLK was incorrectly configured as PULL_UP, but should have been
PULL_DOWN. 2K pulls somehow masked this problem.
BUG=chrome-os-partner:24353
TEST=Verify eMMC is bootable on Rambi on boards that previously failed
with an all-20K, all-PU eMMC pin configuration.
BRANCH=None
Change-Id: I0cbb6ebbb6818f83402b99330728266b09a0f5d6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5026
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
The BISOC.EXIT_SELF_REFRESH_LATENCY field should
not be updated from the default.
BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: I6e701a520513372318258648e998dd8c7ab29ea4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180730
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5025
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Not used currently on rambi board. Disable in case it
saves power.
BUG=chrome-os-partner:23862
BRANCH=none
TEST=build and boot on rambi
Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180084
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5020
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
With the ACPI GNVS exported and depthcharge changed to
initialize eMMC in ACPI mode we can now put the SCC
devices into ACPI mode.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot on rambi, test eMMC and SD card
Change-Id: I39716198f8227c0c3293ac23eb09660792e2c51b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179901
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5018
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Make sure reg_script is executed before the device is put into
ACPI mode.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi from eMMC in ACPI mode
Change-Id: I4090babbfc7fb0f3be4da869386e998d87a513ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5017
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Since this file will get added to payloads it is useful if it
exports what offset in NVS it lives.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode
Change-Id: I52860980c91dfe2525628e142b34ca192e69b258
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179848
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5014
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Make use of the ITE common Super I/O framework and there-by removing any
hard coding of Super I/O base address.
Change-Id: I14af89d2727d7c6bac0f9840043c430726297429
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5717
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Following the reasoning of:
cf7b498 superio/fintek/*: Factor out generic romstage component
Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5585
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Provide devicetree.cb RAMstage configuration of this superio component.
Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5668
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
No need to pass CPP down to SeaBIOS, it's not
architecture specific and they define their own
variable.
Change-Id: I811aaf3929fa11cc01b7f168ccd310008e21e60c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5715
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove arch-level Kconfig menu option as it shows all available architectures in
make menuconfig. Instead pull the bootblock options for choice and update image
to top-level Kconfig since it is already present for both x86 and arm.
Change-Id: Iab9c4539f05cd54a7f751565fefcaf7b6f0edc86
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5673
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Lines with 'select SERIAL_CPU_INIT' where redundant with the
default being yes. Since there is no 'unselect SERIAL_CPU_INIT'
possibility, invert the default and rename option.
This squelches Kconfig warnings about unmet dependencies.
Change-Id: Iae546c56006278489ebae10f2daa627af48abe94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5700
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Turn on WDT support in the devicetree. Turn off CIR support.
Dispense with old commentary.
Change-Id: Icf0c0e12a0ed7ce6c3b6176653e076ffc2ba937e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5698
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Turns out there are a few minor differences of the LDN's in the AD rev.
of this Fintek chip. 0x07 is in fact the WDT so renaming and remove the
now incorrect io mask. Add missing CIR LDN functionality and touch up
src inline doc.
Change-Id: I440aebad71d62d199d3283dd061933e76b21dda5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5696
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
In order to use the same reference code on S3 resume
that was booted the program needs to be cached. Piggy
back on the ramstage cache to save the loaded reference
code program.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed. Noted locations of reference
code caching and load addresses in console.
Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179777
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5013
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Allow ramstage cache to be used from ramstage proper. Also
add a helper function for checking validity of ramstage
cache structure.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179775
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5011
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Certain code paths want to know if S3 resume is
happening. However, the current baytrail code doesn't
note S3 resume early enough. Therefore, mark S3
resume just after pattr setup.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179774
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5010
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The inclusion of reg_script_run_on_dev() allows
for removing some of the chained reg_scripts just
to set up the device context. Use the new reg_script
function in those cases.
BUG=None
BRANCH=None
TEST=Built and booted. Didn't see any bizarre dmesg or coreboot
console output.
Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438
Signed-off-by: Aaron Durbin <adurbin@chromium.og>
Reviewed-on: https://chromium-review.googlesource.com/179541
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5009
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Aaron Durbin