Commit Graph

20598 Commits

Author SHA1 Message Date
Lee Leahy 8bad6d2f90 cpu/x86: Fix various issues detected by checkpatch.pl
Fix the following errors and warning detected by checkpatch.pl:

ERROR: spaces required around that '=' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: need consistent spacing around '|' (ctx:WxV)
ERROR: need consistent spacing around '|' (ctx:VxW)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '==' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:ExV)
WARNING: space prohibited between function name and open parenthesis '('

TEST=Build and run on Galileo Gen2

Change-Id: I61d08055b207c607d5b7d72b0094ad8e24fbd106
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:11:10 +01:00
Lee Leahy 5f94541329 src/cpu/x86: Remove space between * and variable name
Fix the following error detected by checkpatch.pl:

ERROR: "foo * bar" should be "foo *bar"

TEST=Build and run on Galileo Gen2

Change-Id: I8b5342df3f42dbb4576aecf5b0a59f195ae8511e
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18839
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16 04:10:47 +01:00
Lee Leahy 28c3f23b46 mainboard/intel/galileo: Add vboot support
Add the necessary files and changes to support vboot.

TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield

1.  Obtain and install a SparkFun CryptoShield.
    https://www.sparkfun.com/products/13183

2.  Edit src/mainboard/intel/galileo/Kconfig to select
    VBOOT_WITH_CRYPTO_SHIELD

3.  Use make menuconfig to update the config values and select a
    payload that will fit.  I used SeaBIOS which does not boot.

4.  Build coreboot

5.  Use the command file below to generate the signed coreboot image.

6.  Flash build/coreboot.rom onto the Galileo board

7.  The test is successful if verstage detects that it needs recovery
    after Phase 1.  This is expected because the image does not contain
    the GBB section.

8.  Flash build/coreboot.signed.bin onto the Galileo board

9.  The test is successful if verstage reaches Phase 4 and selects SLOT
    A to load the rest of the files.

commands:
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob

dd  conv=fdatasync  ibs=4096  obs=4096  count=1553  \
if=build/coreboot.rom  of=build/coreboot.signed.rom

dd  conv=fdatasync  obs=4096  obs=4096  seek=1553  if=gbb.blob  \
of=build/coreboot.signed.rom

dd  conv=fdatasync  ibs=4096  obs=4096  skip=1680  seek=1680  \
count=368  if=build/coreboot.rom  of=build/coreboot.signed.rom

gbb_utility                       \
--set --hwid='Galileo'            \
-r $PWD/keys/recovery_key.vbpubk  \
-k $PWD/keys/root_key.vbpubk      \
build/coreboot.signed.rom

3rdparty/vboot/scripts/image_signing/sign_firmware.sh  \
build/coreboot.signed.rom                              \
$PWD/keys                                              \
build/coreboot.signed.rom

Change-Id: I02eb0ef647cd34c13a5fe8be0bdbe1bb38524d0c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18821
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16 04:10:25 +01:00
Lee Leahy 1b39f176a9 drivers/i2c/tpm: Add support for Atmel TPM (AT97SC3204)
The I2C interface for the Atmel AT97SC3204 TPM varies greatly from the
existing I2C TPM support.  The Atmel part just passes the commands and
responses from the TIS layer across the I2C interface.

TEST=Build and run on Galileo Gen2 with Crypto Shield and vboot enabled

Change-Id: Ib2ef0ffdfc12b2fc11fe4c55b6414924d4b676dd
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18800
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16 00:04:46 +01:00
Lee Leahy e0668e4e1f drivers/i2c/tpm: Add TPM (TIS) debugging support
Add debugging support for the TIS transactions for the I2C TPM chips.

TEST=Build and run on reef

Change-Id: Ibc7e26fca781316d625f4da080f34749f18e4f9b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-16 00:04:31 +01:00
Lee Leahy 52ab30b13b drivers/i2c/tpm: Fix issues detected by checkpatch
Fix the following warnings detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: braces {} are not necessary for single statement blocks
WARNING: Unnecessary parentheses - maybe == should be = ?
WARNING: line over 80 characters
WARNING: missing space after return type

TEST=Build and run on Galileo Gen2

Change-Id: I56f915f6c1975cce123fd38043bad2638717d88c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18832
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15 20:56:03 +01:00
Vincent Palatin 08824ec8d4 google/eve: Update MCU GPIOs configuration
Keep the BOOT0 pin triggering the MCU bootloader as an input,
so the Servo debug board doesn't have to fight with the PCH to program
it, the net already has an external pull-down to ensure that the MCU is
in normal mode at boot.

By default, do not drive the FP sensor reset from the PCH, the MCU is
now managing the reset line (but the PCH still has a connection on the
current boards).

BRANCH=none
BUG=b:36025702
TEST=manual testing, program the MCU through a Servo v2 board, and use
the FP sensor through the MCU and verify it is not stuck under reset.

Change-Id: I19113b5d78013d0ab6ec5a72c6f71dd4c67a88e8
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/18830
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-15 19:54:47 +01:00
Duncan Laurie 57e9e3be5f google/eve: Apply default AC/DC loadline settings
Set the AC and DC loadline values based on the KBL-Y 2+2 defaults
that are applied by FSP.  These will be tuned later and are exposed
as defaults so the engineers know what to start with.

BUG=b:36228330
BRANCH=none
TEST=Build and boot on Eve and check debug FSP output to ensure that
it is applying the provided loadline values

Change-Id: Ieae4f2b201d8210e75bdb9438070a3a2e1fda6b7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18820
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2017-03-15 19:48:57 +01:00
Duncan Laurie 86db469871 intel/skylake: Support for setting AC/DC loadline
Add options to set the AC and DC loadline values for each supported
VR type so these can be tuned on a per-board basis in devicetree.cb.

BUG=b:36228330
BRANCH=none
TEST=Build and boot on Eve and check debug FSP output to ensure that
it is applying the provided loadline values

Change-Id: I2a5533d2c9fd86351c86584e3738e80ac4c1f915
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18819
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-15 19:45:55 +01:00
Duncan Laurie 4fa8a6f4fe intel/skylake: Fix bug in VR configuration with FSP 2.0
With the move to FSP 2.0 the number of VR types supported was
reduced to 4, and the VR_RING type is no longer present.

This means all existing boards using FSP 2.0 are incorrectly
passing VR configuration into FSP as the values corresponding to
"GT Sliced" and "GT Unsliced" have changed.

Fix this by updating the skylake SOC VR handling to account for
changes in the FSP configuration and no longer provide VR_RING
type when using FSP 2.0.

BUG=b:36228330
BRANCH=none
TEST=manual: build and boot on Eve

Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2017-03-15 19:45:42 +01:00
Duncan Laurie 2661a9f517 google/eve: Use rt5514 instead of 4ch DMIC
On this platform the DMICs are connected to the rt5514 DSP instead
of directly connected to the SOC.  Use the new rt5514 NHLT blob
instead of the 4ch DMIC blob and add the required I2C and SPI
entries in devicetree so this can get probed properly.

BUG=b:35585307
BRANCH=none
TEST=build and boot on Eve P1 and check for rt5514 driver enumerated
by the kernel

Change-Id: I0f2cb532771ee1857df7f33c52a96acf96dc1f54
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18817
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-15 18:32:40 +01:00
Duncan Laurie 4a75a66d67 intel/skylake: nhlt: Add support for rt5514 NHLT blob
Add support for describing the NHLT blob for the rt5514 DSP.
Currently this only supports 4 channel capture.

BUG=b:35585307
BRANCH=none
TEST=build and boot on Eve P1

Change-Id: Ib59b56222f9aa65370fdcf9ddf25145c571b1b2e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18816
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-15 18:32:27 +01:00
Duncan Laurie 7273e18399 acpi: device: Add macro for active high level triggered IRQ
Add the missing macro for ACPI_IRQ_LEVEL_HIGH so it can get
used by devicetree when necessary.

BUG=b:35585307
BRANCH=none
TEST=Add rt5514 SPI device with active high level IRQ on Eve board
and check that it is enumerated in the kernel

Change-Id: I25c7b035a198efb218f0f6b4ba3f4a1bf532bcea
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18815
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-15 18:32:06 +01:00
Kyösti Mälkki 7f3741840c AGESA f14: Fix infinite loop
Fix regression after commit:
  22f32c7 cpu/amd/agesa: Unify init files

Change-Id: I36fb7369084c68577df69abc251c84dad64f7015
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18822
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2017-03-15 14:11:50 +01:00
Mario Scheithauer 0853055ef7 siemens/mc_apl1: Clean up the code
This patch make some general adaptations in relation to commit 6a489237
(mainboard/intel/leafhill: Clean up).

- add necessary defaults to Kconfig
- remove irrelevant entries from FMD file
- include romstage file for better understanding

Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18808
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-15 13:53:57 +01:00
Lee Leahy 70bb05715a soc/intel/quark: Read the rmu.bin file from read-only region
Always read the rmu.bin file from the read-only section of the SPI
flash.  Without this change vboot attempts to read this file from the
A or B section of the flash.

TEST=Build and run on Galileo Gen2

Change-Id: Ied8eaa2cd37645bf401aa957936943946bfd6182
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18803
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15 05:12:15 +01:00
Lee Leahy 36984d85e7 src/lib: Clean up general issues found by checkpatch.pl
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: Bad function definition - void init_timer() should probably be void init_timer(void)
ERROR: Prefixing 0x with decimal output is defective
WARNING: Comparisons should place the constant on the right side of the test
WARNING: char * array declaration might be better as static const

TEST=Build and run on Galileo Gen2

Change-Id: I9f618eea95e1f92fa34f4f89da27c0b16ae7f4ee
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18763
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15 05:05:04 +01:00
Lee Leahy 491c5b60d0 src/lib: Move assignment out of if condition
Fix the following error detected by checkpatch:

ERROR: do not use assignment in if condition

TEST=Build and run on Galileo Gen2

Change-Id: I5a08d1647db66bd5d480f81e90d473999c222acf
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18761
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15 05:04:45 +01:00
Lee Leahy 006d73d2e2 soc/intel/common: Wrap lines at 80 columns
Fix the following error detected by checkpatch.pl:

ERROR: code indent should use tabs where possible

TEST=Build and run on Galileo Gen2

Change-Id: Ief4b96073b3df30e45bf5d802ca3b190e7f431a7
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18753
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15 04:59:35 +01:00
Andrey Petrov c5f3685f44 soc/intel/apollolake: Cache FPF status value in flash
Since asking CSE to read FPF status turned out to be slow in some
cases, cache and save returned value on first boot only. Value is
read from flash on consequent boots.

BUG=b:35586975
BRANCH=reef
TEST=boot twice, make sure cached FPF status is loaded from
flash the second time.

Change-Id: I6e56a35407c9097616ccb05a557fded7b639c88a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18774
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15 03:43:05 +01:00
Andrey Petrov 2e726f605d mainboard/google/reef: Add FPF_STATUS FMAP region
Add FPF_STATUS region under MISC_RW. The purpose of the region is to
store FPF status.

Change-Id: I2997b3d39a94bf444df51068f254edcf49c47afd
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18773
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15 03:42:55 +01:00
Lee Leahy 48b69aca47 Revert "mainboard/intel/galileo: Add vboot support"
This reverts commit a50ced2eba.

Change-Id: I4f7d3177015bfe280111843014c310e0d333cb17
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18814
Tested-by: build bot (Jenkins)
2017-03-15 01:28:57 +01:00
Julius Werner 5fae829410 libpayload: usbhub: Force enumeration of all connected ports on init
We have found a non-compliant USB hub (RealTek RTS 5413) that does not
set a port's Connect Status Change bit on its USB 3.0 half if the port
had already been connected while the hub was being reset. To work around
this bug, this patch adds code to initially request the status of every
port after a hub was enumerated, clear the Connect Status Change bit if
set, and then enumerate the port iff it is currently connected,
regardless of whether the change bit was set. A similar behavior can
also be found in the Linux kernel.

BRANCH=oak
BUG=b:35929438
TEST=Booted Elm with this change, my USB 3.0 sticks enumerate now even
if they had been plugged in since boot.

Change-Id: I8a28252eb94f005f04866d06e4fc61ea265cee89
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18729
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-15 00:54:23 +01:00
Lee Leahy a50ced2eba mainboard/intel/galileo: Add vboot support
Add the necessary files and changes to support vboot.

TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield

1.  Obtain and install a SparkFun CryptoShield.
    https://www.sparkfun.com/products/13183

2.  Edit src/mainboard/intel/galileo/Kconfig to select
    VBOOT_WITH_CRYPTO_SHIELD

3.  Use make menuconfig to update the config values and select a
    payload that will fit.  I used SeaBIOS which does not boot.

4.  Build coreboot

5.  Use the command file below to generate the signed coreboot image.

6.  Flash build/coreboot.rom onto the Galileo board

7.  The test is successful if verstage detects that it needs recovery
    after Phase 1.  This is expected because the image does not contain
    the GBB section.

8.  Flash build/coreboot.signed.bin onto the Galileo board

9.  The test is successful if verstage reaches Phase 4 and selects SLOT
    A to load the rest of the files.

#!/bin/sh
#
#  The necessary tools were built and installed using the following
commands:
#
#        pushd 3rdparty/vboot
#        make
#        sudo make install
#        popd
#
#  The keys were made using the following command
#
#        3rdparty/vboot/scripts/keygeneration/create_new_keys.sh  \
#                --4k --4k-root --output $PWD/keys
#
#
#  Create the GBB area blob
#
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob

#
#  Add the empty GBB to the coreboot.rom image
#
dd  conv=fdatasync  ibs=4096  obs=4096  count=1553  \
if=build/coreboot.rom  of=build/coreboot.signed.rom

dd  conv=fdatasync  obs=4096  obs=4096  seek=1553  if=gbb.blob  \
of=build/coreboot.signed.rom

dd  conv=fdatasync  ibs=4096  obs=4096  skip=1680  seek=1680  \
count=368  if=build/coreboot.rom  of=build/coreboot.signed.rom

#
#  Add the keys and HWID to the GBB
#
gbb_utility                       \
--set --hwid='Galileo'            \
-r $PWD/keys/recovery_key.vbpubk  \
-k $PWD/keys/root_key.vbpubk      \
build/coreboot.signed.rom

#
#  Sign the firmware with the keys
#
3rdparty/vboot/scripts/image_signing/sign_firmware.sh  \
build/coreboot.signed.rom                              \
$PWD/keys                                              \
build/coreboot.signed.rom

Change-Id: I96170412e7bbc2b9c747ff5e2c845f29220353ed
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18041
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14 23:55:40 +01:00
Lee Leahy 1e24bf3f71 soc/intel/quark: Pass S3 wake status to fsp_silicon_init
Fix build error with FSP 1.1.  Pass the S3 wake status to
fsp_silicon_init.

TEST=Build and run on Galileo Gen2

Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18805
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14 23:54:54 +01:00
Lee Leahy 66b0d55d32 soc/intel/quark: Add ESRAM display to FSP 1.1
Add ESRAM display to FSP 1.1

TEST=Build and run on Galileo Gen2

Change-Id: Ia47b0bdba65606a7f0695332d298fc1e910b0e2f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18804
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14 23:54:37 +01:00
Lee Leahy 6edb314050 soc/intel/quark: Return NULL for top_of_memory
Return NULL for top_of_memory when the register has not been set.

TEST=Build and run on Galileo Gen2

Change-Id: If79cac68c2a64aa9bf3be72d3cfc4c73fceef12b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18802
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14 23:54:11 +01:00
Lee Leahy 33efd98cfd vboot: Allow other platforms to use soft reboot workaround
Add a Kconfig value to enable other platforms to use the soft reboot
workaround.

TEST=Build and run on Galileo Gen2

Change-Id: I5a7ebd200229654128d367ecb50647ff69bb5258
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18798
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14 23:10:00 +01:00
Lee Leahy c253a92299 drivers/intel/fsp1_1: Only display MMCONF address if supported
Disable the display of the MMCONF_BASE_ADDRESS if it is not supported.

TEST=Build and run on Galileo Gen2

Change-Id: Ie4f0fbf264662b5bc12ca923f25395e5e91defea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18801
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14 23:06:21 +01:00
Arthur Heymans 98e77c77fd util/autoport: Create superiotool logs
Change-Id: I29797ac6078c0488cb75a8e510bfd5ddf49e4b8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18483
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2017-03-14 23:03:29 +01:00
Denis 'GNUtoo' Carikli 7d234f2e69 GDB_WAIT: Clarify Kconfig description
The user has to know in which stage gdb is waiting to be able to
use symbolic debugging.

Change-Id: Ia992e7a2077b92c45546ae56c5fb648775f8f63b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12709
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-14 22:20:47 +01:00
Barnali Sarkar b7fa7fbbd7 soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOB
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB
and save it in CBMEM.

BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".

Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18275
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-14 17:53:20 +01:00
Nico Huber 0ff3b392a9 buildgcc: Search for `xz` too
Change-Id: I05d5f26f7cf9ab41b14aaecfe421b88ef9a2394a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18775
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-14 16:59:45 +01:00
Arthur Heymans 1b69d73530 board_status/towiki.sh: Fix Socket for Sandy and Ivy Bridge
Change-Id: I4c94209c424f56516033c07c4365401a6b217a37
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18478
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-14 02:32:36 +01:00
Katherine Hsieh 20e86be181 google/sand: Remove support for tablet mode switch
Sand is not convertible and no EC sensor sends event from EC to AP.
That event default is tablet mode, we don't have to enable tablet event.

Modify the ec.h, is based on <baseboard/ec.h>

BUG=b:36108742
BRANCH=reef
TEST=emerge-sand coreboot, boot to OS and touchpad and keyboard can work.

Change-Id: I6b6b45b5b4daf2c430ed18130f39eab0bd9a9812
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18737
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14 02:27:19 +01:00
Lee Leahy b8f5323107 soc/intel/quark: Add the verstage files
Add the files to support verstage for vboot.

TEST=Build and run on Galileo Gen2

Change-Id: Icf87075012c08cf581c17d579e0763888c707265
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18040
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 21:25:27 +01:00
Lee Leahy f59a75c99d src/lib: Remove semicolon from end of macro
Fix the following warning detected by checkpatch.pl:

WARNING: macros should not use a trailing semicolon

TEST=Build and run on Galileo Gen2

Change-Id: Ie1d966b0f1f8fff401d6314fd2ef005ab6ac69db
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18764
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-13 21:24:26 +01:00
Lee Leahy 3e1cab447b src/lib: Remove unnecessary code
Fix the following warnings detected by checkpatch.pl:

WARNING: break is not useful after a goto or return
WARNING: Statements terminations use 1 semicolon
WARNING: else is not generally useful after a break or return
WARNING: void function return statements are not generally useful

TEST=Build and run on Galileo Gen2

Change-Id: I6f095c4e9cb1ee4ff2ebdf095ef612e1a8393231
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18762
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-13 21:23:58 +01:00
Lee Leahy 49fd42dc65 commonlib: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:

TEST=Build and run on Galileo Gen2

Change-Id: I811763c6de57dfdf5456579f63e83dca29d37d61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18751
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 21:23:21 +01:00
Lee Leahy 07441b5ae6 soc/intel/apollolake: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

TEST=Build for reef

Change-Id: I4fbe95037ca4b52e64ba37e5c739af4a03f64feb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18728
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:52:40 +01:00
Lee Leahy a444753596 soc/intel/apollolake: Fix issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: switch and case should be at the same indent
ERROR: do not use assignment in if condition
WARNING: Statements terminations use 1 semicolon
WARNING: unnecessary whitespace before a quoted newline
WARNING: else is not generally useful after a break or return

TEST=Build for reef

Change-Id: I5486936dbf19b066c76179d929660affa1da5f16
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18727
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:48:31 +01:00
Lee Leahy 2d154e8213 soc/intel/apollolake: Fix position of storage class
Fix the following error and warning detected by checkpatch.pl:

ERROR: inline keyword should sit between storage class and type
WARNING: storage class should be at the beginning of the declaration

TEST=Build for reef

Change-Id: I2ed418cc3b4a989eb1101013944169429bf147c2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18726
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:47:37 +01:00
Lee Leahy d8fb362ea0 soc/intel/apollolake: Fix parenthesis issues
Fix the following errors and warning detected by checkpatch.pl:

ERROR: space required before the open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: return is not a function, parentheses are not required
WARNING: space prohibited between function name and open parenthesis '('

TEST=Build for reef

Change-Id: I31f854adf3269ba6f77c4044fb3748bb1957841c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18725
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:46:40 +01:00
Lee Leahy 0096d07274 soc/intel/apollolake: Fix unsigned warnings
Fix the following warning detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=Build for reef

Change-Id: Ifc45ce90d466d087cd20af72ddfc8486d2f1492c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18724
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:45:16 +01:00
Lee Leahy 4430f9f75d soc/intel/apollolake: Remove unnecessary braces
Fix the following warnings detected by checkpatch.pl:

WARNING: braces {} are not necessary for any arm of this statement
WARNING: braces {} are not necessary for single statement blocks

TEST=Build for reef

Change-Id: Ifab09c023faa7da215945f1aedd391f4b2a1a04c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18723
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:44:24 +01:00
Lee Leahy 1d20fe77cb soc/intel/apollolake: Indent code using tabs
Fix the following error and warnings detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs

TEST=Build for reef

Change-Id: Id7a758463b95274c5e8bbdd67da0955f1ae78aac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18721
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:42:02 +01:00
Lee Leahy 320b7ca44b soc/intel/apollolake: Fix spacing around operators and commas
Fix the following errors detected by checkpatch.pl:

ERROR: spaces required around that '==' (ctx:VxO)
ERROR: space required before that '-' (ctx:OxV)
ERROR: spaces required around that '=' (ctx:VxW)
ERROR: spaces required around that '=' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: need consistent spacing around '+' (ctx:VxW)
ERROR: space prohibited before that '++' (ctx:WxB)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space required after that ',' (ctx:VxV)

TEST=Build for reef

Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18720
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:41:48 +01:00
Lee Leahy 68571c144e soc/intel/apollolake: Fix space between type, * and variable name
Fix the following errors detected by checkpatch.pl:

ERROR: "foo * bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"

TEST=Build for reef

Change-Id: I4a762d8fa762057a06e601dfed10538adc5d8bc8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18719
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:41:25 +01:00
Lee Leahy bab8be229a soc/intel/apollolake: Move brace to beginning of line
Fix the following error detected by checkpatch.pl:

ERROR: open brace '{' following function declarations go on the next line

TEST=Build for reef

Change-Id: Icb92dc49c6e7b8dfea60bc0395f3db7316c4e34c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18722
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:39:52 +01:00
Lee Leahy 6a566d7fbe src/include: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

Changed a few comments to reduce line length.  File
src/include/cpu/amd/vr.h was skipped.

TEST=Build and run on Galileo Gen2

Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18687
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:23:37 +01:00