When displaying a 800x600 bitmap on 2560x1800 panel, the image
is shown very small. So, set the fb to 1280x800 (based on tegra
dsi driver default mode setting), a 800x600 image can be shown
relatively proportional to panel size.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I1e360aeaec97b9df5d86e46951ab1326610260d2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 67c2a381322721a24b1b7f9ac366073b7e3c490c
Original-Change-Id: I62cbe9de1d1002293df20f8b1d752905c6ef33aa
Original-Reviewed-on: https://chromium-review.googlesource.com/229912
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9521
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
panel spec such as resoultion, bits per pixel are
needed to pass to depthcharge/payload for displaying
bitmap onto panel.
Enable display code only if mainboard selects
MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for
boards that do not support display init yet.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and
dev mode.
Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b
Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad
Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/9519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Chrome OS support needs to be enabled on urara. This patch adds a
placeholder file to keep Chrome OS support code.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=none
Change-Id: I0731469934f04bd68914f09db5d64758c5d01545
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 169c62c9443c3b9fcab23b312b5cb18ba79437f4
Original-Change-Id: I8ec328d4f965ff80d17847f2f8ce62b402c42a46
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226179
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9466
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is needed for audio playback after we disconnect PP1800_CODEC
from DACREF to avoid noise coupled on PP1800_CODEC, which makes
recording noisy.
For recording, DACREF comes from mic vref pump voltage.
For playback, DACREF comes from internal 1.8V.
BUG=chrome-os-partner:32953
BRANCH=samus
TEST=Set MICBIAS to 2.970V on Samus, playback/recording is clean
Change-Id: I65fb6dbfab54c7c4de6496fd4a0d666baead28ec
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 3e62a61f6cf6042f6d653a827698b55ac86e2d2b
Original-Change-Id: I27430691e469dd7f4056d99438ce080062b58b9a
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241179
Reviewed-on: http://review.coreboot.org/9500
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The default micbias1 voltage is 1.476V (1.8V * 0.82) which does
not match what's specified on the schematic. This patch sets
the voltage to 2.970V (3.3V * 0.90) according to the schematic.
BUG=chrome-os-partner:32953
BRANCH=samus
TEST=Set MICBIAS to 2.970V on Samus and verified with a scope
Change-Id: I1ced834a5afe2de3fccf4bcff8ec9c8e5718f60a
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 176f9272801a3de5ed6fc05ade06042e2a2c0a5c
Original-Change-Id: Icdbc1b5f65fe28591d54544372bdc2dacb50e9c1
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241178
Reviewed-on: http://review.coreboot.org/9499
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reduce the SATA Gen3 TX voltage amplitude by 210mV based
on the provided test results to help with SATA validation.
BUG=chrome-os-partner:34121
BRANCH=samus
TEST=build and boot on samus and ensure SATA is still working,
firmware image will be provided for full validation.
Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a
Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241800
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9496
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order for recovery request to be cleared with software sync disabled
we need to implement this function in the mainboard.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=boot in recovery with software sync disabled, ensure that the next
boot will not boot in recovery again.
Change-Id: Ie9c845396dfc6ab65296b2f18a86e23590c833d6
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 430f85608cc3b59a68a86dba64ffe428bfc216a9
Original-Change-Id: Iac15b6a1b23cc971231339439bceb013f4a031bd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241052
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9492
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With recent changes in the 3.14 kernel and the switch to not
using X the panel backlight is not geting turned on until
chrome is started which means the splash screen is not visible.
If we set the backlight PWM in coreboot then it will at least
turn on for the early boot process.
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=boot on samus in normal mode and see the boot splash logo
Change-Id: I81e6b90617acb181b4de3365f8f56ec3b846b78b
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: f850fe3faff268a64f18e6bd176ec1126b921e3b
Original-Change-Id: I622bef8af9bb6b753fe228b33ecdc4aae76af131
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240853
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9491
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We'll need to find a real ACPI device ID for
the rt5677 SPI driver. "RT5677AA" is temporary.
BUG=chrome-os-partner:33495
BRANCH=samus
TEST=load firmware via SPI; hotword detection works
Change-Id: I6dc55c4641c27a38570debe841a6afeb048eb868
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: f0d7013b62c78deb82db1a431f079c79eded5270
Original-Change-Id: Ifb4a1b12776669e21c0b7c4679246717d72981ad
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/235902
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9486
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To support the ACPI device specific properties that conform to the
existing devicetree bindings for this codec (in upstream kernels)
add a _DSD object to the existing codec device.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=build and boot on samus
Change-Id: Ice808ba7bf2f0378ac5a38afd27dbf6c8cac0da5
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: b3fc2d7e5a5878b1fff7627f803b883b38fea28d
Original-Change-Id: I344636171a3086a72087314503bfc99de5945b1f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238857
Original-Reviewed-by: Ben Zhang <benzh@chromium.org>
Reviewed-on: http://review.coreboot.org/9483
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This combines the board version reading and parsing to
a separate file that is compiled in both romstage (for
early serial output) and ramstage (for smbios tables).
It also adds a new board version that is wrapped back
to number zero as we are running out of available IDs.
BUG=chrome-os-partner:32895
BRANCH=samus
TEST=build and boot on samus EVT1 and EVT2 and check
for proper board versions reported in console and smbios.
Change-Id: I8c8f17708ced7167277a98529ff4597589f53095
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 3ab8bba1021a8dd41dd2210ba73efd2231eb596c
Original-Change-Id: I2aa03e7486a9581f94dc4e12f6f29eb0c5b3bdbb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229041
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9473
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
PHYSICAL_REC_SWITCH is set n by default and y for panther and stumpy.
BUG=none
BRANCH=ToT
TEST=Built nyan_blaze using vboot1/2. Built falco, lumpy, nyan,
blaze, parrot, rambi, samus, storm, pinky with default configuration.
panther and stumpy are not tested because they currently don't build on ToT.
Original-Change-Id: Ic45f78708aaa7e485d2ab459fd1948524edb412f
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227940
Original-Reviewed-on: https://chromium-review.googlesource.com/229602
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit edb2ba347b48887ffe450586af0351e384faad59)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I277f665cd4f3e1c21745cdc5c7a2cfe148661abe
Reviewed-on: http://review.coreboot.org/9444
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Adds AM1ML board. This board has AM1 Socket and supports all
new AM1 APUs from AMD. Based on asrock/imb-a180 board.
Successfully tested with SeaBIOS and Linux 3.8.x and Windows XP.
Successfully tested audio, video, network, PS/2 keyboard and mouse,
PCIe x16, COM port, SATA and USB.
LPT port is not tested yet and it’s unknown if it’s work.
Change-Id: I9ebb9acc590d38e47579adc263f45ae3f607684e
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: http://review.coreboot.org/9293
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
This isn't done in upstream.
Change-Id: Ief1fea0f231d609372f065f6f6aee7bceaf31efc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9458
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This should allow the max98090 codec to play beeps via
AHUB/I2S1 thru the depthcharge sound driver.
BUG=none
BRANCH=none
TEST=Saw max98090 codec init signon and register dump.
No sound yet.
Change-Id: I1ee0b61f5cbfe587ebd16b7dd9dce08d9d62c2c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4ee2ce3704711a9e00531b7599a1bcf194203ec
Original-Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229496
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Mike Frysinger <vapier@chromium.org>
Reviewed-on: http://review.coreboot.org/9429
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
1. Add page address, an i2c address, into register address table
2. Add pmic read function
3. Add more registers and setting values.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: Ieef0737205b20add3ff8990f62dd8585a4e8c557
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dcf42c299e25023991be331b724acd0fd9f32c2
Original-Change-Id: I227b3e9390e6fc020707d4730c19945760df6ca2
Original-Reviewed-on: https://chromium-review.googlesource.com/226902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: http://review.coreboot.org/9420
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Take codec out of reset (GPIO_PH1 aka CODEC_RST_L) and enable LDO2
(GPIO_PR2/KB_ROW2 aka AUDIO_ENABLE). Muxes are setup and the two
GPIOs are set to output and driven high.
BUG=chrome-os-partner:32582
BRANCH=none
TEST=RealTek ALC5677 codec shows up in I2C6 scan at address 0x2D,
can read/write registers.
Change-Id: I236850452d401fd89b4f59eb03f132c0be32fb20
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fe3b0c1a3f5d6264b83d7a7e2363dc3f3235cbf
Original-Change-Id: Iedce7bb9f8e61d3b8cd693fc5e567323d89f8046
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/228920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9419
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Proto 0,1,2 boards had pwr btn active high. Proto 3 onwards boards will have pwr
btn active low. Thus, select power btn polarity based on board id.
BUG=chrome-os-partner:33545
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu proto 1.
Change-Id: I9b06b10358b91d40cfdb418ef8cf4da1ae833121
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7100a42b53a09ed4cb298f88d6f804f46fecacb5
Original-Change-Id: Icdf51b9324385de00f5787e81018518c5397215f
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229011
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9418
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This deprecates TERTIARY_BOARD_ID. Instead, a board will set
BOARD_ID_SUPPORT (the ones affected already do) which will set
GENERIC_GPIO_SUPPORT and compile the generic GPIO library.
The user is expected to handle the details of how the ID is encoded.
BUG=none
BRANCH=none
TEST=Compiled for peppy, nyan*, storm, and pinky
Change-Id: Iaf1cac6e90b6c931100e9d1b6735684fac86b8a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93db63f419f596160ce2459eb70b3218cc83c09e
Original-Change-Id: I687877e5bb89679d0133bed24e2480216c384a1c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228322
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9413
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch makes a few cosmetic changes:
- Rename tristate_gpios.c to gpio.c since it will soon be used for
binary GPIOs as well.
- Rename gpio_get_tristates() to gpio_base3_value() - The binary
version will be called gpio_base2_value().
- Updates call sites.
- Change the variable name "id" to something more generic.
BUG=none
BRANCH=none
TEST=compiled for veyron_pinky and storm
Change-Id: Iab7e32f4e9d70853f782695cfe6842accff1df64
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c47d0f33ea1a6e9515211b834009cf47a171953f
Original-Change-Id: I36d88c67cb118efd1730278691dc3e4ecb6055ee
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228324
Reviewed-on: http://review.coreboot.org/9411
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
slowly raise to max cpu voltage to prevent overshoot,
and in our experience,when cpu run in 1.8GHz,the
vdd_cpu must up to 1.4V
BUG=chrome-os-partner:32716, chrome-os-partner:31896
TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1400mv
and measure the overshoot is 1440mv
Change-Id: I759840bd8cf57a5589bf1862d04803f80f804164
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 567f616ff091883ed3275b407859c9399db981b2
Original-Change-Id: I9bb739b49ae4b4f7a60133fa38b0fe51b95c0d78
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226753
Original-Reviewed-by: Doug Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9408
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There are changes in upcoming board revs that need to take
different action depending on board revision. Update the
enumeration to reflect upcoming reality.
BUG=chrome-os-partner:33578
BRANCH=None
TEST=Built and booted.
Change-Id: Ib51393e04d3255bbd44e5d77a2a7903109beebf4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de8d629678c0ae17af9f7145e04d95f43c927ee0
Original-Change-Id: I64cdeab806e7a665051f1d47bbf044413f7a1196
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227681
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9407
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The gpio_get_tristates() function prints out the values
observed while processing the GPIOs. Additionally, the
values for the normalization were completely consecutive.
Therefore, this indirection can be removed.
BUG=chrome-os-partner:33578
BRANCH=None
TEST=Built and booted.
Change-Id: I088a2f1c7601c014a7f8a9eb228efa9bb80f1e01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 02e52554b9cbf85034feb9aedc50f09b70893e32
Original-Change-Id: I17d85891087e3128790329a5f05cbdab4cbc950e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227680
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9406
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Add the Whirlwind board ID to the enum
- Replace comparisons of the board ID with 0 to the proto0 constant
TEST=Booted Storm with this coreboot version
BUG=none
BRANCH=none
Change-Id: I53be0b06c3444936a8bd67653e03b93bcb87e328
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e055ef27ef1e07be09d80b2298384889214bf0d
Original-Change-Id: I75c7c98732c3d4569611de54d7aa149dd3b0fb7d
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225460
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9404
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch runs basic NAND initialization code on Proto 0.2 boards which
have been reworked for NAND. It makes sense to do this in coreboot for
two reasons:
- In general, it is reasonable for coreboot to initialize clocks and such
in preparation for depthcharge's use. Waiting times can be pooled, and
the initialization itself here is very fast.
- There is a kernel bug which requires that the clock is already initialized
before the kernel loads NAND support. coreboot is a more sensible place
to put a workaround than depthcharge because depthcharge initializes
things lazily, but when booting from USB, depthcharge won't need to look
at NAND.
This change involves bringing in an additional header file, ebi2.h, from U-Boot.
TEST=Booted a kernel from USB and verified that NAND came up without any
depthcharge hacks, whereas previously a USB-booted kernel would be unable
to access NAND even with the same drivers compiled in due to an initialization
failure.
BUG=chromium:403432
BRANCH=none
Change-Id: I04e99cb39d16848a6ed75fe0229b8f79bdf2e035
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9be29da5ccad9982f146ae00344f30598ef2371c
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Change-Id: I1760ecb4e47438311d80e34326e45578c608481c
Original-Reviewed-on: https://chromium-review.googlesource.com/225277
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9402
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The function to read board IDs from tristate GPIOs currently supports
two output modes: a normal base-3 integer, or a custom format where
every two bits represent one tristate pin. Each board decides which
representation to use on its own, which is inconsistent and provides
another possible gotcha to trip over when reading unfamiliar code.
The two-bits-per-pin format creates the additional problem that a
complete list of IDs (such as some boards use to build board-ID tables)
necessarily has "holes" in them (since 0b11 does not correspond to a
possible pin state), which makes them extremely tricky to write, read
and expand. It's also very unintuitive in my opinion, although it was
intended to make it easier to read individual pin states from a hex
representation.
This patch switches all boards over to base-3 and removes the other
format to improve consistency. The tristate reading function will just
print the pin states as they are read to make it easier to debug them,
and we add a new BASE3() macro that can generate ternary numbers from
pin states. Also change the order of all static initializers of board ID
pin lists to write the most significant bit first, hoping that this can
help clear up confusion about the endianness of the pins.
CQ-DEPEND=CL:219902
BUG=None
TEST=Booted on a Nyan_Blaze (with board ID 1, unfortunately the only one
I have). Compiled on Daisy, Peach_Pit, Nyan, Nyan_Big, Nyan_Blaze, Rush,
Rush_Ryu, Storm, Veryon_Pinky and Falco for good measure.
Change-Id: I3ce5a0829f260db7d7df77e6788c2c6d13901b8f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2fa9545ac431c9af111ee4444d593ee4cf49554d
Original-Change-Id: I6133cdaf01ed6590ae07e88d9e85a33dc013211a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219901
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9401
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We've had gpiolib.h which defines a few common GPIO access functions for
a while, but it wasn't really complete. This patch adds the missing
gpio_output() function, and also renames the unwieldy
gpio_get_in_value() and gpio_set_out_value() to the much easier to
handle gpio_get() and gpio_set(). The header is renamed to the simpler
gpio.h while we're at it (there was never really anything "lib" about
it, and it was presumably just chosen due to the IPQ806x include/
conflict problem that is now resolved).
It also moves the definition of gpio_t into SoC-specific code, so that
different implementations are free to encode their platform-specific
GPIO parameters in those 4 bytes in the most convenient way (such as the
rk3288 with a bitfield struct). Every SoC intending to use this common
API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most
4 bytes in length. Files accessing the API only need to include <gpio.h>
which may pull in additional things (like a gpio_t creation macro) from
<soc/gpio.h> on its own.
For now the API is still only used on non-x86 SoCs. Whether it makes
sense to expand it to x86 as well should be separately evaluated at a
later point (by someone who understands those systems better). Also,
Exynos retains its old, incompatible GPIO API even though it would be a
prime candidate, because it's currently just not worth the effort.
BUG=None
TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and
Veyron_Pinky.
Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e
Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220975
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9400
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Retrieving MAC address from VPD should be the board responsibility,
add a call to the recently introduced function.
BRANCH=storm
BUG=chromium:417117
TEST=verified that MAC addresses still show up in the device tree on
storm
Change-Id: Ib8ddc88ccd859e0b36e65aaaeb5c9473077c8c02
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 285cb256e619ef41c7f11680b3fa5310b1d93cf1
Original-Change-Id: I3913b10a425d8e8621b832567871ed4861756381
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223797
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9399
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This patch aligns bg4cd to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Cosmos.
Change-Id: I32a4407f7deb2b1752b6220a140352724f320637
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0b6bb6990417863010258632374c3f5ac19350c9
Original-Change-Id: Ia5299659ad186f2e7d698adfa7562396e747473f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224506
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The SOC code should include the SPI controller driver when configured.
Enable SPI support for cosmos.
BRANCH=none
BUG=chrome-os-partner:32631
TEST=cosmos builds
Change-Id: I8212f191b7d80f0bee86f746813edaf8e5ee6db1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fd4853be5157247bb73fc22b9d4f8300228fe6ce
Original-Change-Id: If7e12e2fb04e63c36d9696d13e08397b91a77a8c
Original-Commit-Id: 7b1d095e5df6a864d3564bbf7a20cc211f75629a
Original-Change-Id: If9dd80cb96120d34a0865f7882cd62e45fed749d
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223750
Original-Reviewed-on: https://chromium-review.googlesource.com/223752
Reviewed-on: http://review.coreboot.org/9356
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With this descriptor added ramstage properly allocates memory
resources and creates entries in coreboot table. This also allows to
proceed to booting depthcharge, as it now can be loaded into the
existing memory.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the set of patches applied the firmware properly finds
depthcharge in CBFS, uncompresses it and attempts to start:
...
Booting payload fallback/payload from cbfs
Loading segment from rom address 0x9b000058
code (compression=1)
New segment dstaddr 0x80124020 memsize 0x2099a0 srcaddr 0x9b000090 filesize 0xbbe
Loading segment from rom address 0x9b000074
Entry Point 0x80124038
Loading Segment: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe
lb: [0x0000000080000000, 0x0000000080013858)
Post relocation: addr: 0x0000000080124020 memsz: 0x00000000002099a0 filesz: 0x0000000000000bbe
using LZMA
[ 0x80124020, 8012596c, 0x8032d9c0) <- 9b000090
Clearing Segment: addr: 0x000000008012596c memsz: 0x0000000000208054
dest 80124020, end 8032d9c0, bouncebuffer 8ffd4f50
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 129 run 34579421 exit 129
Jumping to boot code at 80124038
ERROR: dropped a timestamp entry
CPU0: stack: 9a00c800 - 9a00d800, lowest used address 9a00d498, stack used: 872 bytes
entry = 80124038
Change-Id: I15809e146407d66b04f2a97c47c961fdccb8e175
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a1577c5532a064426a3ea88b6f7f30ccdae24eaf
Original-Change-Id: Ifed5550f2c18430e9ae06ad1ecacaa13191b5995
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232571
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9192
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
32K is a more appropriate room for Pistachio bootblock.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=there is no bootblock overflow even when compiled with -O0.
Change-Id: I454746ce0b9daabc93ccbf3316655fac836af8ff
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 56adf22ba12f5a7c69d11c0c720996de32ca9149
Original-Change-Id: I74b6674aea95b1138e2168527239e2cfb4a7ad42
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232291
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9190
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch aligns tegra124 to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Nyan, Nyan_Big and Nyan_Blaze.
Change-Id: Ia82ab86b2af903690cc6c9d310f7bdda3425ea7c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d23774e071ec22781991ff20fbf63802f620c88
Original-Change-Id: Ia126cff8590117788d1872e50608c257d2659c1f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224504
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9326
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch aligns ipq806x to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Storm.
Change-Id: Icb81a77e6f458625f5379a980e8760388dd3a1f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1bf23774c9ffa5d08c211f3658d39adcfa47b339
Original-Change-Id: I283cc7e6094be977d67ed4146f376cebcea6774a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224502
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9368
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Patrick Georgi <pgeorgi@google.com>
This patch is the start of a series to change all non-x86 SoC-specific
headers to be included as <soc/header.h> instead of the old
<soc/vendor/chip/header.h> or "header.h". It will add an include/soc/
directory under every src/soc/vendor/chip/ and append the .../include/
part of that to the global include path.
This matches the usage of <arch/header.h> for architecture-specific
headers and had already been done for some headers on Tegra. It has the
advantage that a source file which does not know the specific SoC used
(e.g. Tegra files common for multiple chips, or a global include file)
can still include SoC-specific headers and access macros/types defined
there. It also makes the includes for mainboard files more readable, and
reduces the chance to pull in a wrong header when copying mainboard
sources to use a different-related SoC (e.g. using a Tegra124 mainboard
as template for a Tegra132 one).
For easier maintainability, every SoC family is modified individually.
This patch starts out by changing Rk3288. Also alphabetized headers in
affected files since we touch them anyway.
BUG=None
TEST=Whole series: compared binary images for Daisy, Nyan_Blaze,
Rush_Ryu, Storm, Urara and Veyron_Pinky. Confirmed that they are
byte-for-byte identical except for timestamps, hashes, and __LINE__
macro replacements. Compile-tested individual patches.
Change-Id: I4d74a0c56be278e591a9cf43f93e9900e41f4319
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4ad8b6d2e0280428aa9742f0f7b723c00857334a
Original-Change-Id: I415b8dbe735e572d4ae2cb1df62d66bcce386fff
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222025
Reviewed-on: http://review.coreboot.org/9349
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
check the cpu and gpu temperature in romstage,
if over 120 degrees celsius,shut down the device.
BUG=None
Test=Boot on veyron_pinky rev2, write value
3421(125 celsius) to grf_tsadc_testbitl register,
the device will be shut down
Change-Id: I275d643ce8560444a9b42ee566d5fd63ebcda35e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0c597489dc0637ffa66ee9db0c4f60757f8889f
Original-Change-Id: If406d6a4f6201150f52ea7fc64cd50b45778d7aa
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223259
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch aligns tegra132 to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Rush_Ryu.
Change-Id: I5cdf4008a65db84f15c937ef53aab5e4d3ef24c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5c5c63d7b6399d3eb8a211b15d47829fe93a591
Original-Change-Id: Ifafd4d42d4fb04a1c37e8a5f23877c2b550cf44c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224505
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9369
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Solving the DACR bug will mean that XN bits suddenly become enforced on
non-LPAE systems, and we will no longer be able to execute out of a
region mapped DCACHE_OFF. When we enable the MMU in romstage we are
still executing out of SRAM, so we would instantly kill ourselves.
Solve this issue by enabling the MMU earlier (in the bootblock) and
mapping the SRAM regions as DCACHE_WRITETHROUGH. They should really be
DCACHE_WRITEBACK, but it looks like there might be hardware limitations
in the Cortex-A12 cache architecture that prevent us from doing so.
Write-through mappings are equivalent to normal non-cacheable on the A12
anyway, and by using this attribute we don't need to introduce a new
DCACHE_OFF_BUT_WITHOUT_XN_BIT type in our API. (Also, using normal
non-cacheable might still have a slight speed advantage over strongly
ordered since it should fetch whole cache lines at once if the processor
finds enough accesses it can combine.)
CQ-DEPEND=CL:223783
BUG=chrome-os-partner:32118
TEST=None (depends on follow-up CL)
Change-Id: I1e5127421f82177ca11af892b1539538b379625e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7b079f4b6a69449f3c7cc18ef0e1704f2006847
Original-Change-Id: I53e827d95acc2db909f1251de78d65e295eceaa7
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223782
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9342
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Jimmy Zhang