This patch aligns pistachio to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Urara.
Change-Id: I0609b307695ba6a922384ac34dd604bffcb20692
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0a577918babf26adf10baa0f56a7065f5659d285
Original-Change-Id: I3ed405a3efdeec28965538d19a22f2b5b8204f01
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224503
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch aligns exynos5420 to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Peach_Pit.
Change-Id: If97b40101d3541a81bca302a9bd64b84a04ff24a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 570ca9ed6337d622781f37184b2cd7209de0083f
Original-Change-Id: I338559564e57bdc5202d34c7173ce0d075ad2afc
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224501
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9324
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch aligns exynos5250 to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Daisy.
Change-Id: I39805c0346e117a0f9b2667763ecaa428f0f55a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db6762f0c8425371d9860f908a5cefdeee8d1abc
Original-Change-Id: Ic358061ddcbbe7d83a95ca11247b8b505b20491d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224500
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9323
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch aligns broadwell to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Auron and Samus.
Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e
Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224507
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This patch aligns baytrail to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Rambi.
Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083
Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.
The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).
BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.
Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Restructure get_option() calls to avoid unnecessary return value checks
by pre-assigning defaults to the options being retrieved.
Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4
Signed-off-by: Varad Gautam <varadgautam@gmail.com>
Reviewed-on: http://review.coreboot.org/8631
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
x201 has 2 sata ports. 1 port for hard drive and 1 port for the dock.
Tested on x201 with hdd in port 1 + cdrom in port 2.
Change-Id: I1ee8c547392257d4f2e00a5d48e21447a84f79c0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8657
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The nehalem smi finalize handler was just copied from sandybridge,
without even changing the function name.
TEST=Built and tested on x201t with additional patch to use finalizers
Change-Id: Ifb44eeaaa6e03556deeb5d12ed1147e02d6d6eb9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8292
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
before the rkclk_init(), we must set rk808
buck1 voltage up to 1300mv
BUG=chrome-os-partner:32716, chrome-os-partner:31896
TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1300mv
and check the cpu frequency up to 1.8GHz
Original-Change-Id: I6a8c6e35bd7cc6017f2def72876a9170977f206e
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/222957
Original-Reviewed-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 2e7e7c265691250d4a1b3ff94fe70b0a05f23e16)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Iff89d959456dd4d36f4293435caf7b4f7bdaf6fd
Reviewed-on: http://review.coreboot.org/9260
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This device is not used in current builds and should be
disabled to help EMI.
BUG=chrome-os-partner:34117
BRANCH=samus
TEST=build and boot on samus
Change-Id: I5c34f1f6c84d9de04a42e16fa32f57d4f9d1e478
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 00a9b2ad8512f84beff7358dad0ec028478c57d2
Original-Change-Id: I62541e343dcaa3cd31c81b73d8c27a5efcf3ad60
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234403
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9282
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a new memory type for the next build, and rename the existing
ones to drop the Gb suffix.
BUG=chrome-os-partner:33924
BRANCH=samus
TEST=build and boot on samus
Change-Id: Iedcd3823aa80c93fc2aadbc486d74b40c9bd4279
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: bcc9827965182a7d0d5325189d55eb76f5c2f0e7
Original-Change-Id: I47d2b7e58f51f3ee00cd7797da3f8353f509f8b5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230769
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9278
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently the rt5677 codec outputs 6MHz PDM clock which is
out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS
pin is pulled down to PGND with a 47k resistor, so the
expected PDM clock is 64*FS (~3MHz) according to its datasheet.
The corresponding kernel patch that adds the PDM clock config
option is https://chromium-review.googlesource.com/#/c/230303/
BUG=chrome-os-partner:33303
BRANCH=samus
TEST=flash coreboot with this patch and see PDM CLK went
from 6MHz to 3MHz on samus with a scope.
Change-Id: Icf2c61930175bede1ee8ebc2b0fb17c2938b806c
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: b9ba4597515b2fbcc72fa22e296357c454175648
Original-Change-Id: I09acdf47bab4f641981491a84197de234918435e
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230344
Original-Reviewed-by: Dylan Reid <dgreid@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9277
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This value apparently changed to 0x27 in the hardware but was
never adjusted in firmware.
BUG=chrome-os-partner:33790
BRANCH=samus
TEST=build and boot on samus
Change-Id: Ib610fc6522715e3c841c337d420ec63563bec798
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: e01d3b47bf49861e9d53fc8db41890fe4c91ff9b
Original-Change-Id: I10ca7b77068491e143f8bf2463b481eada910618
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230232
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9274
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This will be connected to the coded for firmware upload.
BUG=chrome-os-partner:33495
BRANCH=samus
TEST=build and boot on samus, check that GSPI driver is loaded
Change-Id: Ife41394e31af9dab03495b34609cb119525f9b19
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: bbf26154da675845251c54f71d1df9df8d2a4fd5
Original-Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228835
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9273
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With EVT2 systems GPIO9 is now used for touchpad wake.
BUG=chrome-os-partner:32232
BRANCH=samus
TEST=suspend/resume by touchpad on samus, with kernel workaround
to disable setting of T19 in atmel driver mxt_suspend()
51 | 2014-11-03 12:41:34 | ACPI Enter | S3
52 | 2014-11-03 12:41:37 | ACPI Wake | S3
53 | 2014-11-03 12:41:37 | Wake Source | GPIO | 9
Change-Id: I67c1a6591dc287fc780889950e78c731a5a65d44
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 8512a6e5266edaf77d300f47bd26c501f00361d7
Original-Change-Id: I8120747986e694b64d464826f87c9afa68af157a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227157
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The codec interrupt needs to be active high because multiple
interrupt sources share this line:
1) Headphone plug detect
2) Mic present
3) Hotword detect
These interrupt sources are OR-ed together.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=Jack detection works on samus
Change-Id: If35fe8493ab30d878d9fac2251acee62c776b0eb
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 348608fe61f7848db2bfd22502a0c259d24f8980
Original-Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220588
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9268
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GPIO IRQ support has been added in upstream rt5677 driver,
with new jack detect platform config options.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=headphone and mic detect works on Samus
Change-Id: I68a675ccd1fec3e5329d57aadad3229053092026
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4b90fa2f557f603661e25c9e1b4712eea15c8502
Original-Change-Id: I379087b8acdb13e65776a18c9ee3a58d4cb4e73c
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224513
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9266
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This matches the label exported by the GPIO controller in the
kernel and allows more speicific matches if there are other
devices that also export GPIOs.
BUG=chrome-os-partner:33098
BRANCH=samus
TEST=crossystem wpsw_cur returns 1
Change-Id: I96f8d0f7f9fd584be4a6f14d13e04db0a88951a8
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 736679136a0a72874304eaeae1ac58633cd2ce14
Original-Change-Id: I655549d0f0eca341581bfbf845162d8b9f5e993d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224136
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since the PD software sync is slow enable support for displaying
a screen telling the user that something is happening.
BUG=chrome-os-partner:32379
BRANCH=samus
TEST=manual testing:
1) in normal mode, with EC/PD in RW, ensure that they are rebooted
to RO and the VGA Option ROM is loaded and the wait screen is
displayed, and then the system is rebooted at the end and the
VGA Option ROM is not loaded.
2) same as #1 with EC/PD in RO already, same result
3) same as #1 with system in developer mode, same result except
there is no reboot at the end of software sync
4) same as #1 with system in developer mode and EC/PD in RO,
ensure that there is no extra reboot at the beginning or end of
software sync.
Change-Id: Ib6c4cc03952768ece76832efc84f665c52191ffb
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 6971d74ff50ced0ef94d5fec26c0e6a071d207b2
Original-Change-Id: I125744f58c6b84df1af3943d9be98fe55c7117d5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223850
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9264
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of having this in mosys just have coreboot report the
board version in SMBIOS tables.
BUG=chrome-os-partner:32359
BRANCH=samus
TEST=build and boot on samus, check /sys/class/dmi/id/product_version
Change-Id: I09d235752f4c870f99fb8c6a280e2bf9aba7e137
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 08413589ba84b07ff64c9116ca5fcc991cee3b89
Original-Change-Id: Ib851d2e79ed721dcbc1c2f2eda6da50cac064cf3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223096
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9263
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is the specific codec setup platform data for samus.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=emerge-samus coreboot
Change-Id: I00d4a2f73810f5f7bad49922321fb1c340289770
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 813c45bc3fdd7a2fb84df0e24bd470003bf4eafa
Original-Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/221539
Original-Reviewed-by: Ben Zhang <benzh@chromium.org>
Reviewed-on: http://review.coreboot.org/9261
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Snow was renamed to daisy a long time ago. The only reason, it seems,
the directory was still there, was a stray board_info.txt file that
probably went in shortly after the rename.
Change-Id: Iba08665e8486fcfeb214fcd05206a5f5683aea82
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9302
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This re-factors rockchip_spi to remove speed_hz which will instead be
passed in via rockchip_spi_init(), thus making it easier to support
other boards which may have different slave devices attached.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10
Original-Reviewed-on: https://chromium-review.googlesource.com/220411
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c
Reviewed-on: http://review.coreboot.org/9245
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This patch moves init for I2C, SPI, ChromeOS GPIOs to the
board-specific bootblock init function on Pinky, the idea being
to isolate SoC code so that it's more readily adaptable for
different boards.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I75516bbd332915c1f61249844e18415b4e23c520
Original-Reviewed-on: https://chromium-review.googlesource.com/220410
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 0a7dec2fe70679c3457b0bfc7138b4a90b6217c8)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib2c2e00b11c294a8d5bdd07a2cd59503179f0a84
Reviewed-on: http://review.coreboot.org/9243
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Since the UART which is used for the serial console may change from
board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's
Kconfig into Pinky's Kconfig.
BUG=none
BRANCH=none
TEST=built and booted on pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34
Original-Reviewed-on: https://chromium-review.googlesource.com/221438
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 53bff629f2e9865656beabd81e6ce1eab7c728a9)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I65835c07a49dc3a3518c6bb24a29bc6ae7dd46c9
Reviewed-on: http://review.coreboot.org/9242
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add ddr3-samsung-2GB config and modify 533mhz linit.
Support ddr3 freq up to 800mhz.
Enable ODT at LPDDR3.
BUG=None
TEST=Boot Veyron Pinky
Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220113
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d
(cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9239
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=None
TEST=Boot Veyron Pinky and test the VDD_LOG
Original-Change-Id: Ie2eef918e04ba0e13879e915b0b0bef44aef550e
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219753
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Change-Id: I444b47564d90b3480b351fdd8460e5b94e71927c
(cherry picked from commit 4491d9c4037161fd8c4cc40856167bf73182fda6)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9240
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
BUG=None
TEST=Boot Veyron Pinky and measure i2c clock frequency
Original-Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219660
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Change-Id: Ie7ac3f2d0d76a4d3347bd469bf7af3295cc454fd
(cherry picked from commit 4b9b3c2f8b7c6cd189cb8f239508431ee08ebc52)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9241
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
This gives the EC some time to wake-up between asserting /CS and
starting a transfer.
BUG=chrome-os-partner:32223
BRANCH=none
TEST=verified ~100us delay using logic analyzer on Pinky
Original-Change-Id: I9874e65abd405874c43c594d8caeeff9e1300455
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220243
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Alexandru Stan <amstan@chromium.org>
Original-Commit-Queue: Alexandru Stan <amstan@chromium.org>
Original-Tested-by: Alexandru Stan <amstan@chromium.org>
Change-Id: I103542517d3ebd7da4f0394b3ae4f68f58403b1e
(cherry picked from commit bdb67fe489b7cbea7a26492fa0536ca452434052)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9238
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch adds support for the board changes in rev2 (board_id = 0001).
It also moves the existing mainboard.c code around a bit to group it by
component.
BUG=chrome-os-partner:32139
TEST=Booted on rev1. Confirmed SD card still works. Confirmed power
button was still as broken as before.
Original-Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220251
(cherry picked from commit 9428e0d1b784b27790b3b3dbbb18a769e51c6fd3)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8d3479aa314f8c6f1591c1b69b0a3827234fc730
Reviewed-on: http://review.coreboot.org/9237
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The codec interrupt needs to come from codec GPIO1, so use the
HOTWORD_DET GPIO as the codec IRQ and the DSP_INT as the wake.The
This means codec interrupt is GPIO46 which is PIRQO and should be
interrupt 30.
Also add GPIO defines for the GPIOs attached to the codec itself.
These are defined by index, and I used the same "jack detect" and
"mic present" indices that were used in baytrail.
The codec interrupt to the host is added at index 2 and the
hostword detect interrupt to the host is added at index 3.
These can be changed as we work through the implementation in the
kernel driver.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=build and boot on samus
Change-Id: Id9cb083ddf9df161be314da4148740ed9f4d0fe6
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 3958efb28813c664a8a4219f78bdd0fcfe75c706
Original-Change-Id: I1c1ac1b6095fab7e3f4412555db4f9a9138e528b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220326
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9216
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Move _PRW to the ACPI devices for the touchpad and touchscreen.
Add a _DSW method, but disable it by default for now until a
spurious wake issue can be resolved.
BUG=chrome-os-partner:32232
BRANCH=samus
TEST=build and boot on samus, ensure trackpad does not
spuriously wake the system.
Change-Id: I3160248ef6dfeccdec765553643d9b8de2bb2ed1
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 85d14842aefdb29c750009c0092f055587172dac
Original-Change-Id: Ic4763f2cb5f3a59d04b236cee94906025661c615
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220325
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9214
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Define specific GPIOs in gpio.h instaed of smihandler.c
- Add battery status event to SCI list
- Remove old proto board version defines and SPD index usage
- Do not disable cmd_pwr training now that it works on EVT board
BUG=chrome-os-partner:32196,chrome-os-partner:29117
BRANCH=samus
TEST=build and boot on samus
Change-Id: I50f1599aa4266ed61749cc7f4229a9384b498df2
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0e3ebcb8659c92874d3ca89fa3a6795c9b6eebfa
Original-Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220321
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9220
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to not break FAFT, and to have a quicker recovery
mode boot, reboot the PD controller into RO image in romstage.
This is done before the EC since rebooting the EC into RO will
also reboot the host.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=boot samus EVT into recovery with 'dut-control power_state:rec'
and ensure that the PD controller is rebooted to RO in romstage.
Change-Id: Ieb51717c17fdcbda7aa63b6a9404959e8736c08f
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 19237f6a338fa1c593867d8dfda1edcd376878af
Original-Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218904
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9205
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Mark GPIO42 as unused according to Samus schematics
BUG=None
TEST=Make the chnage; Pass the build process; Need someone having
the board perform the verification.
Change-Id: Ib53a3ae062d414a2c98ec0756e759760d179e3fd
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4e0f8f3276c575ff60fbda709de5d3cfe31a5900
Original-Change-Id: Ifd6a0d2de8af0fe3af4a14f44ce572b41b77509c
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217344
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9199
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
CQ-DEPEND=CL:218766
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Change-Id: Ib3eed77553433e9f8c70af8b148729e628c95747
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 56b3e8c02a4e45653a5369ce47dcbce0c18f7194
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Icbee95350949bd9bfa4490a8a4b6bbf09beb4170
Original-Reviewed-on: https://chromium-review.googlesource.com/221019
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9224
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
echo is evaluated by a shell builtin producing non-binary
spd data of the form '-e -n \<byte>'. Correct this by
using printf builtin which does the equivalent and is
more cross platform friendly.
Boards changed:
gizmosphere/gizmo
gizmosphere/gizmo2
google/bolt
google/falco
google/link
google/peppy
google/rambi
google/samus
google/slippy
pcengines/apu1
Change-Id: Iefdaf59903b9682cc88c94fd991883b560616492
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9196
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In commit 72a8e5e751 the
Makefile's were updated to use named types for cbfs
file addition. However, the call sites were not checked to
ensure the types matched. Correct all call sites to use the
named types.
Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9195
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Some of the files which include cbfs_core.h don't even need
the header definition while others just need the cbfs API
which can be obtained from cbfs.h.
Change-Id: I34f3b7c67f64380dcf957e662ffca2baefc31a90
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9126
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Indicate to rest of coreboot that MAINBOARD_HAS_CHROMEOS
instead of auto-selecting it.
Change-Id: I61cde263f4ad7bd6758a61fc54c456c2ad2f343e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9153
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These binaries were being added to CBFS using hexadecimal values instead
of the CBFS binary type names. The same value was being used in
different places for different things.
For example, the value 0xAB is used for SPDs, MRC & FSP binaries.
This patch uses CBFS type names instead of hex values everywhere a
hex value was previously used.
Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8978
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This doesn't even compile in downstream.
Change-Id: Ic7b3736db86e8de155e0f37afa970ce5095396fa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9164
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The ASUS KFSN4-DRE has a physical BIOS recovery jumper;
force coreboot into fallback mode if that jumper is set.
Change-Id: I513299c3e3261fc76133a49813685d48c53a172a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9156
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Use the run_ramstage() function to load and run ramstage.
Change-Id: I783801bf506fa2f9608eefe1cd20257292c80af5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
The actual level required to take the ethernet switch out of reset is
low, not high.
BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
switch's LED blink once, as was the case with proto0.
Change-Id: If4004ac5c2dc837270d4cb840d96ce92021d231e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9fa69d22de901cd0843948de0f95a66a2aa99353
Original-Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217416
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9121
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The proto0.2 hardware connects gpio26 (sw reset) to the ethernet
switch reset pit. The output stays low (or high-z) after power up,
which holds the switch in reset. Deassert the signal at startup on
hardware rev 1 and later.
BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
switch's LED blink once, as was the case with proto0.
Change-Id: I4c5a0cc499563a33aa7d29be7767d0ec5d93c20f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6788962172c6e29e193fa3e85ca79cb83a96e154
Original-Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217087
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9120
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Figuring out board_id on storm requires reading tertiary gpios, which
takes time. Let's calculate it once and reuse it when necessary.
BUG=none
TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2
respectively.
Change-Id: I69f6afa3de8a175a1d723e95902efd15607e68b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 080c839c1c0c1b5e389b2382144ef67535bb4ff1
Original-Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217086
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9119
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The proto0 storm hardware has the TPM reset line wired to the SOC GPIO22
pin instead of the system reset. This causes all kind of TPM behavior
problems and requires frequent power cycles. Adding explicit TPM reset
makes all those problems go away.
BUG=chrome-os-partner:30705, chrome-os-partner:30829
TEST=tried resetting proto0 at different moments during boot up - the
TPM does not fail anymore.
Change-Id: Idfa16e6e868336f38861edeb75703fff3f35172c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5e07815c227089b7f266ba5329812bf309b87e6
Original-Change-Id: Ia877fcd9efaf3ba12c8fe8c2958bd81c4bf22799
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211497
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9118
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Storm provides three real and two fake gpios. To keep things simple,
define them all as active low and provide appropriate values for the
fake ones.
BUG=chrome-os-partner:30705
TEST=with the appropriate depthcharge change booted proto0, observed
appropriate behavior following the dev switch setting
Change-Id: I248b90ee06d226a223b6fc0993f209acdd58c77d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d48d1dcc88df0c1bd4c50f14dd2e7cd1dd4fba5d
Original-Change-Id: Icb7fb55949fa97ead9d19f0da76392ee63bbb5b8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210922
Reviewed-on: http://review.coreboot.org/9117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There's no need to add DMA ranges for these boards as
that memory is allocated within dpethcharge now. Additionally,
the DRAM_DMA_* Kconfig options were removed resulting in 0
values.
BUG=None
TEST=Built rush and ryu.
BRANCH=None
Change-Id: I597437960e4fddbf6d26f0b15ddeefc4557adc8b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f26b503d759b2bac902e58e928d7c625c1a6c575
Original-Change-Id: I52bb8f760a56226c75611f7981570a44d56f242e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219710
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9101
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Do the absolute minimum needed to allow the DPAUX mux ctl write
for I2C6. This leaves HOST1X off (reset and clock disabled) to
avoid a conflict with any kernel display driver init.
I2C6 init/enable will be moved to ramstage in the next CL.
BUG=chrome-os-partner:31820
BRANCH=none
TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good.
Change-Id: I42106778a26c5a1d1483cc308b8314599c391539
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24a9ebfda31c620b24e5c765dc950b87e3e5587b
Original-Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/218900
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9093
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With the generic spin table support in place, use that.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=None
Change-Id: I7c9ebd16cd7d5e938e686df2225c612581382983
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb0d79f89e27fcd51cc751a94008b3801f5c6d0b
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Change-Id: Ic9949144ed1e9a952290d50b6726bf5891547896
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218657
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9087
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With the generic spin table support in place, use that.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Booted into kernel.
Change-Id: I8644f8a81b24bf4e00f8fac1d1018f9db77c952f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1a4fe27070a80c8448051ec0565120901378673
Original-Change-Id: Id0832a4553101a366f011099e0744f6630d91924
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218656
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9086
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Rush builds were throwing a _sync_sp_el0 exception due
to commit 65af2f3d (tegra132: support arm64 SMP bringup).
Fixed by copying over the rush_ryu devicetree.db, which
adds all the CPUs to the device tree. Basically the same
as commit 8f61ca2da but for rush.
BUG=None
BRANCH=None
TEST=Booted rush OK, brought up rush kernel from USB.
Change-Id: Ia91260ed36364ae1cfdd28932f09df9486c7e638
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 649391a402527cef1465d5a948323ad95c77917d
Original-Change-Id: Ic9e34494ec8e6ad82e6020df6ad6fecd8763ac7e
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217792
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9067
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Now that arm64 and tegra132 has cpu devicetree support stop
using the bring_up_secondary_cpu option.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and brought up 2nd core.
Change-Id: I3ffca6c1fa0932d8aafea30a160608b5593ae154
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c45b22ce9fd0345c3e599fd814993db66e2b96cc
Original-Change-Id: I210bea73f8249de15f99d0c062600e789184eefd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216928
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9059
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The static gpio_t initializers are stylish, but they are still a little
too annoying to write and read in day-to-day use. Let's wrap that in a
macro to make it a little easier to handle.
BUG=None
TEST=None
Change-Id: If41b2b3fd3c3f94797d314ba5f3ffcb2a250a005
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 102a5c0a800f43d688d11d1d7bbc51e360341517
Original-Change-Id: I385ae5182776c8cbb20bbf3c79b986628040f1cf
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220250
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9052
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a mainboard-specific bootblock function that will be used
to set up some board-specific parameters which are currently set up
in the SoC bootblock function.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Change-Id: I86c90f7ade824fb9d6b71ca3349d1ce9eb4772fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03e0bb2eaca7a54c3df95b21d856ef4114d3c833
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ibee7076ebd6080f04b0697067e85ce8b6b2230e4
Original-Reviewed-on: https://chromium-review.googlesource.com/220399
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9050
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Danube has become Pistachio, let's rename all instances where this SOC
is mentioned.
BUG=none
TEST=board urara still builds
Change-Id: Iea91419121eb6ab5665c2f9f95e82f461905268e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58696cc7c77a70dca2bfd512d695d143e1097a78
Original-Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220401
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: http://review.coreboot.org/9048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Not much is happening yet, when the board is enabled (in the next
patch), all three components build successfully, the map files show
them placed where expected and the bopotblock is wrappeed in a BIMG
header.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: Ib7396189f4bee0fdd6a8ce5c9ab1277806cb5dcc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1ca9efe59a7fcb99412410d509a7f9a91b6ef3ec
Original-Change-Id: I573cfb70f5c1e612dfa0a55d3d22d92f00584c66
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214600
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9047
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add all the CPUs to the device tree.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Brought up 2nd core on ryu in kernel.
Change-Id: I4cc51f30897e3bd6c1b275a95d5da34ce7ae320e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 485de634a49d606dc6e7168f047eb9365e26415f
Original-Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216426
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9034
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This function is breaking display bring up in the kernel. While
this functionality may be needed it's not until there is a
necessity to beep and/or bring up the display in firmware.
BUG=chrome-os-partner:31820
BRANCH=None
TEST=Sean ran with this patch and the display indeed did come up.
Change-Id: I5cf8a6c6e6941ee138991933215f96f5562382be
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 038bc1d53028409d0640c78fb62c7025ba12dcb9
Original-Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216421
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9031
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are not needed/were never really used. SDRAM init will now
be done in sdram.c, not the BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built rush_ryu AOK.
Change-Id: Id046592415574badb97026224e1e525c174eece4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aab1045817125cb022c8e8b89b85ef14e581baa7
Original-Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/215863
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9030
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The power button signal is driven from the silego part.
It's active high when the button is pressed.
BUG=None
BRANCH=None
TEST=Booted with power button pressed. vboot saw the press and
requested a shut down.
Change-Id: Ifff1bd8d4340849e0c218812fd401b61c90c5743
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b6bd7c0de38e1078b85f1671493c6d2948d43149
Original-Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214847
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9028
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of calling out the gpio index and port numbers use
real names. It's semantically clearer and there's only one
place to adjust the hardware values.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted.
Change-Id: I4a0bc034fe4f648b73ebf6389d8669fe15db1d8f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f2af2e32903b3df64f3f25a42fb42b0b629152c
Original-Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215542
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9027
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The kernel doesn't have the logic for bringing up the plld.
Therefore, configure it in the firmware. The clock used
is an interim value until the display controller sequencing
is fully implemented.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Noted configured freq is close to requested. Also, no
more plld errors observed from the kernel.
Change-Id: I0788c83843699ec7cef52b3a219ebb9b0db9082f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b44956ec87e9083aebe589349cbe168f7f101d8b
Original-Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214841
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9026
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instruct the SoC to bring up the 2nd core.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Brought up 2nd core in Linux.
Change-Id: I4b31ea5f1466c43abce273b2bfb6a4d06b7faa63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 74c62e62a6790de65e303123abee2be1dfffbee3
Original-Change-Id: I5f5febc4719951188106041f73625231eafe1b08
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214778
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9022
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:30748
TEST=Verify that LTE modem appears on USB during kernel boots on Ryu.
Change-Id: I5b73a632ab827abe9c064a097e04d2c9030f9b46
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 070538e60b384d17e17ba3544881ef642c3f33ba
Original-Change-Id: I8ec1f94c9aec5b4895a01cdfd3b86f88cd6bb877
Original-Signed-off-by: Ben Chan <benchan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214020
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9002
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use the bus number enumerations from funit to make the
pad names and bus numbers consistent and clearer.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: If84ed825537f598c033dcacbcba759e0fe4e90ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4375a8e47f572d618044f65603fb9288832f936
Original-Change-Id: I817a56e879ecc96474128d624dc46c12ebc5c7a8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213492
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8997
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=none
BRANCH=none
TEST=built ryu, booted to recovery mode OK
Ran TegraShell and could r/w I2C6 regs OK
Change-Id: I7dca131ab5bd4dac50891937f792ac70b1bb532f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 29591a97fbb8fc42143ff6c7838c9935834ca516
Original-Change-Id: Ic74e3518ab69ec7b1bc3bc4f637b7b38b85734c9
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212926
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8993
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This memory is also x16 and needs slight tweak to tRFCmin
in order to be functional.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on EVT unit with this config
Original-Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 6c4bf71c8c8e1e46ce290441c2e21bc7b2839760)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I389936d85e61a0a939cd4485fcc0723d2a0aa4d6
Reviewed-on: http://review.coreboot.org/8972
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Samus has a PD MCU, and should handle PD MCU host events.
BUG=chrome-os-partner:31361
TEST=Manual on Samus. Verify that ACPI Notify routine is called when
host event is sent from EC.
BRANCH=None.
Original-Change-Id: Id40ebd438b3dd60cefc7650f2edc695c589343e9
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214860
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Alec Berg <alecaberg@chromium.org>
(cherry picked from commit d0752be013f66313d4218338e62372d0f5975097)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I08eb51eceeb7d2835d55e7e861126b137de72bf6
Reviewed-on: http://review.coreboot.org/8969
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
I was using the wrong datasheet for these parts. Revert
to the previous geometry settings so they work again.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: Ibc4a864d458e5ee5ef69aa4f1db5efe14076422a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211610
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f8591e1579d205609a959082d8047d407b4f6a5a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I52ed3609c9686fef13711578597065ca4e907df4
Reviewed-on: http://review.coreboot.org/8951
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Workaround for auto shutdown issue on broadwell SKU.
Now we can see C7 transition, and MRC fastboot
BUG=chrome-os-partner:29787,chrome-os-partner:29117
BRANCH=None
TEST=build ok and boot on samus
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f
Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e
Original-Reviewed-on: https://chromium-review.googlesource.com/210870
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a
Reviewed-on: http://review.coreboot.org/8950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
- geometry was incorrect for 8GB modules, should be x32,
so refactor the rest of the geometry to match
- some of the timing values were off, calcualte new values
from the datasheet
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: I645f354ef21c5032ab73c66e1ad843136ec93eff
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210660
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 8b2ce5c58442e039f5f6e0e053c0072fdec76e9c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29daa9e0ad1bf32be914c0d998f188b9827344a1
Reviewed-on: http://review.coreboot.org/8948
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
We don't set these by default in upstream.
Change-Id: Ida7aa498e0fe291c6cf3cf31d6516530a9d136d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Able to get sporadic USB communication in depthcharge on ryu.
Change-Id: I6bf6559d167a6ea94523d2500b54c1c7854330f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e5412cfc149902298f2ebeb3030d8f09f27e5ee8
Original-Change-Id: Ic5402d18943c3cc8fb4556c47e587134633fbf72
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212333
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With non-cacheable memory region and dma range addition, booting from usb
reaches the same point as mmc.
Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd
Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211039
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8937
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use the new funit API to do all the dirty work.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through depthcharge and into recovery just like
before.
Change-Id: I8625a06dd847bd3dcfc3ce5a50a31d6aff0b860f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebc04a174269ae072eda804e172fd24362f417d2
Original-Change-Id: Ief2d81c5569c33a90fc9458d741edef1dcbd8239
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212152
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently rush needs a DMA region in order to communicate with
USB devices. Therefore, add that region to the memory map.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With the changes for adding non-cacheable memory range and adding DMA
region, booting from USB reaches same point as MMC.
Change-Id: I82d97840fad8cc96bf958c6efa13d2fdc1233d79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b182651a1b6db1a7adbf315b6865467590a0785c
Original-Change-Id: I6a465eaa77e0d5ab4d5fb22161e88e7a5fd9c4a8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212193
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Julius Werner