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36272 Commits

Author SHA1 Message Date
Raul E Rangel b3d7ced512 mb/google/zork/.../sleep.asl: Remove unnecessary variable 
There is no reason to create a named variable. We can just return the
package.

BUG=b:153001807, b:154756391
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-07-15 08:37:42 +00:00
Tim Wawrzynczak 0c0bcd4072 PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device 
This PCI ID is required in order for JSL devices to perform SSDT
generation for DPTF.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:34:29 +00:00
Evgeny Zinoviev 7c1fe4bd12 util/intelmetool: Fix error message 
Add a missing space to the message.

Change-Id: I7d4042ebb587af8558294fb4961100b43910fd4a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-15 08:33:55 +00:00
Angel Pons 380789a6ee mainboard: Drop optional and empty ACPI \_BFS methods 
The ACPI specification, version 2.0 says:

    _BFS is an optional control method.

So, remove them. They have been copy-pasted around quite a bit, and do
not do anything useful. Plus, it's deprecated in later ACPI versions.

Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:33:43 +00:00
Felix Held f06d7d7003 amd/picasso: rework DXIO and DDI UPD handling 
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct
into arrays allows to properly iterate over the fields.

BUG=b:158695393
TEST=Mandolin still boots.

Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:32:47 +00:00
Felix Held 692dde599f vc/amd/fsp/picasso: replace #pragma pack(1) with __packed attribute 
Forgetting to add the #pragma pack() at the end of the header file can
lead to hard to debug breakage, so get rid of the #pragma pack usage and
add a __packed to the structs that need to be packed which has less
possibly unwanted side effects.

Since commit d44221f9c8 coreboot always
includes commonlib/compiler.h which provides __packed.

TEST=Timeless build results in identical binary.

Change-Id: Icc53168f4fbc3a63a859f686b18e7023d225f8d2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-07-15 08:32:18 +00:00
Angel Pons de3fe84ca9 mb/lippert/frontrunner-af: Drop commented-out Kconfig symbol 
Drop it before it grows moss.

Change-Id: I0b4f5487cca3c864ba531cc6c78a20c2682fc43d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43287
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:31:21 +00:00
Rob Barnes 13ec6a03ab mb/google/zork: Change SPI fast speed to 66mhz 
Morphius cannot support 100Mhz fast SPI causing it to not boot.
Downgrade all zork boards to fast=66mhz and normal=33mhz to be safe.

BUG=b:161233767
TEST=Boot morphius

Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43459
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 03:41:18 +00:00
wuxy 288646744f mb/google/oak: Add new DRAM modules for oak 
Add DRAM support for oak:
Samsung  K4E6E304ED-4GB        # 1001
Nanya    NT6CL512T32AM-H0-4GB  # 1010

BUG=b:157702981
BRANCH=oak
TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge,
update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours.

Signed-off-by: Xingyu Wu <wuxy@bitland.corp-partner.google.com>
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-07-15 01:55:03 +00:00
Edward O'Callaghan 0f72ddfd20 mb/hatch: Fix Puff baseboard missing mainboard symbols 
Fix a missing CONFIG_ prefix in Makefile.

BUG=b:161154280
BRANCH=puff
TEST=builds

Change-Id: I177fcd830a8a03a8db1910bfbfd784a60dc08e11
Spotted-by: Ryan Lin.
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43438
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 22:45:36 +00:00
Angel Pons c3c7ef3ec2 soc/intel/skylake: Move `acpi_fill_fadt` to fadt.c 
Intel southbridges do this.

Change-Id: I8ecf3c0b0c822185ca66bae1bd65b0cf24512a49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:34:03 +00:00
Angel Pons 6ee77517c0 soc/intel/braswell: Move `acpi_fill_fadt` to fadt.c 
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.

Change-Id: I2fd2ec5a3029dc1bd1fa65dc3d1af5505f1f1dad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:33:56 +00:00
Angel Pons 91ca2ddde1 soc/intel/baytrail: Move `acpi_fill_fadt` to fadt.c 
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.

Change-Id: I702988493e3b29d807a75c70485baaa2ff6d1aa2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:33:50 +00:00
Angel Pons 34e417316a soc/intel/broadwell: Move `acpi_fill_fadt` to fadt.c 
Intel southbridges do this.

Change-Id: Id120e4a6b42168de58c396439593900a00d7e757
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:33:13 +00:00
Angel Pons 2bd25bfb7f sb/intel/lynxpoint: Move `acpi_fill_fadt` to fadt.c 
Other Intel southbridges do this.

Change-Id: I9b0c8be34e01b617352da4ff8ff37f4b44a4b334
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:33:06 +00:00
Angel Pons 530cde8a9e sb/intel/bd82x6x: Move `acpi_fill_fadt` to fadt.c 
Other Intel southbridges do this.

Change-Id: I6ae78696b0fa2d91dd2c6de0a3ef28e08d85e93b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:32:59 +00:00
Angel Pons cee5ff0629 sb/intel/ibexpeak: Move `acpi_fill_fadt` to fadt.c 
Other Intel southbridges do this.

Change-Id: I8306295fb87776aab5ed0e56e1a9c480c65fe3c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:32:50 +00:00
Elyes HAOUAS e3ee36498e soc/amd/common/block/include/amdblocks/acpi.h: Add missing <types.h> 
BIT(x) needs <types.h>

Change-Id: I5dc0d45567ae9879a7e12f2ccc48929d2abc9456
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-07-14 16:15:55 +00:00
Elyes HAOUAS a0545e6e15 arch/x86/postcar_loader: Remove unused 'include <cpu/cpu.h>' 
Change-Id: I5a36f5729a1a5ad5819ebb3c46b775ba52237d65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:15:28 +00:00
Elyes HAOUAS 3992698388 cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include 
Found using:
diff <(git grep -l 'include <cpu/x86/mp.h>' -- src) <(git grep -l 'CACHELINE_SIZE\|cpu_info\|mfence\|mfence\|mp_ops\|mp_init_with_smm\|MP_RUN_ON_ALL_CPUS\|mp_run_on_aps\|mp_run_on_all_cpus\|mp_park_aps\|smm_initiate_relocation_parallel\|smm_initiate_relocation' -- src/) |grep '<'

Change-Id: Ib721e667144d6803261f3761a077570e0e27391d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-07-14 16:15:09 +00:00
Elyes HAOUAS 06a5e854e1 src: Drop unused <cpu/x86/tsc.h> include 
Found using:
diff <(git grep -l '#include <cpu/x86/tsc.h>' -- src/) <(git grep -l 'TSC_SYNC\|tsc_struct\|rdtsc\|tsc_t\|multiply_to_tsc\|rdtscll\|tsc_to_uint64\|tsc_freq_mhz\|tsc_constant_rate' -- src/)|grep '<'

Change-Id: Id090e232a96323adb8d9a24b81f7ae5669248f57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42393
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:14:33 +00:00
Elyes HAOUAS 14aff23b92 src: Remove unused 'include <cpu/x86/msr.h>' 
Found using:
diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<'

Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:14:09 +00:00
Elyes HAOUAS d970e39eae src/drivers/usb/gadget.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: I1ca111a30153526c3915bf393208fb2b4c569c01
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43347
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:12:53 +00:00
Elyes HAOUAS eb7e166ea1 soc/intel/baytrail/northcluster.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: I85745c331c81a419cef4547fc1c67bde1e202e8f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43346
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:12:39 +00:00
Elyes HAOUAS bd42b06495 soc/intel/baytrail/romstage/pmc.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: If8384f4fea66e26d7377311e7bd8379c7848a26f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43345
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:12:25 +00:00
Elyes HAOUAS 8ebad6d78d soc/intel/baytrail/romstage/raminit.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: I659a067e3b737dc7efe5bdadfd88207cd4d7175d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43344
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:12:12 +00:00
Elyes HAOUAS 3ea5b2d2e6 soc/intel/braswell/romstage/romstage.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: I43b8ba5849de30e2ee253382ef85b17f2d0ae589
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43343
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:11:59 +00:00
Elyes HAOUAS 0badea85a7 soc/rockchip/rk3399/display.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: Ibdde8fb5ec5bf7d25facd78064a7837d24fa2c8a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43342
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:11:42 +00:00
Elyes HAOUAS ad619a2473 src/drivers/usb/ehci_debug.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>. This is needed for 'u64'.

Change-Id: Ie99c27bd6a7d982bba9a93342f3e3b83a1c09e8d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-07-14 16:11:27 +00:00
Elyes HAOUAS 854782330c src: Remove unused 'include <stdint.h> 
Found using:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<'

Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:11:10 +00:00
Elyes HAOUAS 5320f5387e src/acpi/soundwire.c: Add missing <stddef.h> 
size_t needs <stddef.h>. Replace unused <stdint.h> with <stddef.h>.

Change-Id: Ib9ab5555adeeddd9eea7a93dbb166d8479eca42e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43340
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:10:43 +00:00
Elyes HAOUAS 225be5f7ee src: Remove unused 'include <types.h>' 
Files found using:
diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<'

Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:10:17 +00:00
Elyes HAOUAS 5a8e072020 src: Remove unused 'include <string.h>' 
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/) |grep -v vendorcode |grep '<'

Change-Id: I12802d0a6254b2fa39d59f485008bb2012f7b32d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:09:44 +00:00
Rob Barnes f0d1c9a423 mb/google/zork: Add USB to baseboard devicetree 
Add USB ports, USB user-facing camera and USB bluetooth to devicetree.
USB ports 4 and 5 are duplicated for picasso and dali.

BUG=b:158096224
TEST=Boot Trembyle and Dalboz, Dump acpi tables

Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-07-14 16:09:01 +00:00
Rob Barnes ddeba9f196 mb/google/zork: Split devicetree between baseboards 
Split zork baseboard devicetree between dalboz and trembyle.
The devicetree is simply duplicated, no other changes in this commit.

BUG=b:158096224
TEST=Build coreboot for zork

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-07-14 16:08:43 +00:00
Wisley Chen 51c6d4429c mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratini 
Screen flickered on VT2 on some devices  after idle a period of time.

Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking
issue disappeared, and didn't affect acoustic noise much.

Because CB:38212 (commit eae254e) caused this issue.

BUG=b:160754994
TEST=build dratini, observe that screen flick issue disapppered

Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:08:06 +00:00
Shreesh Chhabbi 370868766b mainboard/volteer: Enable SaGv for volteer2, delbin & voxel 
SaGv needs to be enabled for only QS. On ES2, we are seeing system
instability.

BUG=b:159198381
TEST=Tested for boot. Power and performance tests were run with
volteer2 with qs setup. System showed stability.
Tested for boot stability on on delbin.

Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2020-07-14 16:07:25 +00:00
xuxinxiong 8cf43f6c98 mb/google/kukui: Add new configs 'Cerise' and 'Stern' 
New boards introduced to Kukui family.

BUG=b:160854400
TEST=make # select Cerise and Stern
BRANCH=kukui

Change-Id: I5841d57c0891d5191dd96097b90da889855b56c8
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43320
Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:05:49 +00:00
Angel Pons 30392ae396 sb/intel/lynxpoint: Define SerialIO devfns 
This reduces differences with Broadwell.

Tested with BUILD_TIMELESS=1, Google Panther remains identical.

Change-Id: I81c34fd03a176d0575f2fbd254052d90f2b38487
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2020-07-14 16:04:56 +00:00
Nick Vaccaro 20cf396c96 mb/google/volteer: config QS silicon devices for CSE LITE 
Configure volteer2 and delbin, the two variants currently using
preQS or QS silicon, to use CSE Lite.

BUG=b:158140797
TEST=cd to volteer's asset_generation folder, execute
"./gen_all_variant_images.sh" and verify that all variant
images are produced.

Change-Id: I5e444529b090d82094b9da0df2648ea4cdb2888e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2020-07-14 04:52:51 +00:00
Rob Barnes 009a23d5c8 soc/amd/picasso: supply SMBIOS type 17 
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in
cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects
from cbmem to build SMBIOS type 17 tables.

BUG=b:148277751,b:160947978
TEST=dmidecode -t 17
BRANCH=none

Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2020-07-13 21:39:05 +00:00
Furquan Shaikh 33d9eeae5f mb/google/zork: Fix check for variant_uses_v3_schematics() 
CB:43224 ("mb/google/zork: Add helpers for v3 schematics and wifi
power enable") added helper functions for determining if a board uses
v3 schematics. However, it introduced a regression by adding a wrong
check for variant_uses_v3_schematics() in variant_audio_update(). This
change fixes the check to ensure that dmic_gpio is updated when
variant is not using v3 schematics.

BUG=b:161141258,b:161128964
TEST=Verified on trembyle that trackpad works again (it was broken
because of the regression).

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0e6ad844f68cface7b545f1547bd94470c30dde4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43415
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-13 21:23:50 +00:00
Kane Chen 411a6ab703 mb/google/zork: Create Woomax variant 
Create the woomax variant of the zork reference board by copying
the template(coreboot-zork/util/mainboard/google/trembyle)
files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-07-13 19:08:51 +00:00
Angel Pons 26f25d7105 mb/google/beltino/bootblock.c: Drop unused include 
Change-Id: I2994b8bf5521b539a9f3585a3221452b1807837a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-07-12 23:21:57 +00:00
Martin Roth 637f941f66 mb/google/zork: Update SPI mode to 100MHz, 1-2-2 
Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2.

“1-2-2" means command, address and data are transmitted
through 1 wire, 2 wire and 2 wire, respectively.

BUG=b:160603142
TEST=Boot on trembyle, verify register settings.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-12 19:44:26 +00:00
Mate Kukri 45b51e0180 soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controller 
- Correctly detect device 17h as the MMC 4.5 controller
- Support detection of the "old" MMC controller at device 10h

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-07-12 19:44:02 +00:00
Maxim Polyakov 355d1c9870 soc/intel/gpio: Convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() 
As with other macros, convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() to
make the code in gpio_defs.h cleaner.

Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.

Change-Id: Iadc9c4b3c96ae04c56d060cb060737a8eba7f165
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41034
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-12 19:43:38 +00:00
Maxim Polyakov c0dfa7596b soc/intel/gpio: Convert PAD_CFG0_RX_POL_* to PAD_RX_POL() 
Converts PAD_CFG0_RX_POL_* macros to PAD_RX_POL() to make the code
cleaner and reduce the length of the macro.

Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.

Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41033
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-12 19:43:23 +00:00
Maxim Polyakov 3787b67d41 intel/gpio: Convert PAD_CFG0_TRIG_* to PAD_TRIG() 
Converts PAD_CFG0_TRIG_ * macros to PAD_TRIG() to make the code cleaner
and reduce the length of the macro, which is often used.

Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 & T10-TNI carrierboard
does not change.

Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41032
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-12 19:43:00 +00:00
John Zhao 025af31423 mb/intel/tglrvp: Add SMI handler for tglrvp 
This change adds SMI handler for SCI, S3/S5 wake up and LID closed
events on tglrvp platform.

TEST=Built image and booted to kernel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0bc72f164e86f1921e0cad39f9749e8e3be0778f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-07-12 19:41:47 +00:00