Commit Graph

44508 Commits

Author SHA1 Message Date
Sugnan Prabhu S 1de90868b7 mb/google/brya: Disable unused i2s pins for BT offload
BT offload hardware design is using only i2s0 pins. Need to disable
i2s2 pins which are not used. As per the hardware spec there is an OR
operation between vgpio and physical gpio pins related to i2s2. During
BT offload configuring the i2s2 pins to its native function is causing
offload issue on proto 2 boards.

BUG=b:201736222
TEST=Verified BT offload on brya on proto 1 and proto 2.

Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-10-07 18:52:28 +00:00
Seunghwan Kim bd4487c869 mb/google/dedede/var/bugzzy: Update GPP_D5 configuration
As we checked the panel doesn't display firmware screen if we hold
GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy
uses the built-in touch screen on the panel, the panel seems like
under reset state by the TOUCHSCREEN_RESET signal.
This change sets default GPP_D5 level to high for bugzzy.

BUG=b:None
BRANCH=dedede
TEST=built and verified bugzzy showed firmware screen

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Doan <edoan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-07 18:22:00 +00:00
Ryan Lin a45377e83e mb/google/brya: Add PsysPmax setting to 145W
This patch adds the setting of PsysPmax to 145W according to
the brya board design.

BUG=b:195615830
TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS

Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-07 14:53:47 +00:00
Yu-Ping Wu e5824ff2a9 libpayload: cbgfx: Clear screen by memcpy
Instead of setting each pixel in the framebuffer, use memcpy() to clear
screen faster. As this method should be fast enough, remove the fast
path using memset().

The speed of clear_screen() on brya (x_resolution = 1920,
bytes_per_line = 7680):

- Using memset(): 15ms
- Setting each pixel: 25ms
- Using memcpy(): 14ms

Also remove set_pixel_raw() since it's now used in only one place.

BUG=none
TEST=emerge-brya libpayload
TEST=Saw developer screen on brya
BRANCH=none

Change-Id: I5f08fb50faab48d3db6b61ae022af3226914f72b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-10-07 14:11:56 +00:00
Tim Crawford 1724b57729 soc/intel/tigerlake: Hook up GMA ACPI brightness controls
Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.

Tested by adding gfx register on system76/gaze16 and booting Windows.
Display settings has a brightness setting, and can change the brightness
level.

Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-07 11:04:48 +00:00
Ravi Kumar Bokka 5afeba30a3 sc7280: Add SHRM firmware support
SHRM is a system hardware resource manager. It is used to manage run time
DDRSS activities. DDRSS stands for DDR subsystem.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
by trying DDR clocks which through SHRM RSI command.

Change-Id: I44484573a829eaefbd34907c6fe78d427506a762
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-07 09:03:05 +00:00
Patrick Rudolph 4dc9e5b3c7 soc/intel/cannonlake: Enable x86_64 support
Select HAVE_EXP_X86_64_SUPPORT.

Tested on prodrive/hermes: Boots into Linux.

Change-Id: I033ccd5dc793b637a2ac4271b450335464564885
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-07 05:27:43 +00:00
Yu-Ping Wu 2a634ab560 security/vboot: Remove vb2ex_hwcrypto stubs
Now that the vb2ex_hwcrypto_* stub functions are included in vboot fwlib
(CL:2353775), we can remove the same stubs from coreboot.

BUG=none
TEST=emerge-brya coreboot
TEST=emerge-cherry coreboot
BRANCH=none

Change-Id: I62bdc647eb3e34c581cc1b8d15e7f271211e6156
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-07 05:26:19 +00:00
Michael Niewöhner a78ab4b0af soc/intel/dnv_ns: correct size of GPE0 registers in FADT
There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC
code sets a GPE0 block size of 4 byte length instead of 32 byte.
The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit
instead of 256 bit).

Drop the overrides and let common ACPI code set the correct values based
on `GPE0_REG_MAX`.

Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-07 04:46:48 +00:00
Dmitry Ponamorev fba1475f25 soc/intel/denverton_ns: Always enable SpeedStep
When "SpeedStep" is disabled on an Intel Atom C3538,
the maximum CPU clock speed is always 800 MHz(min CPU clock).
Оperating system cannot change the frequency.
Avoid this issue allow "Intel Speed step" technology
for processors that do not have "Intel Turbo Boost".

Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com>
Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
2021-10-07 04:40:31 +00:00
Rajesh Patil c003ea6d2b sc7280: Enable UART driver
Enable common Uart driver on sc7280

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I015e21081391bfe85edf667685bf117401a9ec00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-06 23:59:16 +00:00
Roja Rani Yarubandi acd2218bc3 libpayload: Enable UART driver for sc7280
Add Qualcomm's QUPV3 serial driver for herobrine board

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.

Change-Id: I3a745afd7bbabdd29f1f369612c990526e5a2335
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-06 23:57:20 +00:00
Ravi Kumar Bokka 86b0609c28 sc7280: Enable bootblock compression
This patch enables bootblock compression on SC7280. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).

Ref link: https://review.coreboot.org/c/coreboot/+/45855

BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.

Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-06 23:48:35 +00:00
Derek Huang 1a368769b9 ec/google/chromeec: Register USB-C mux operations
Register USB-C mux operations to the generic interface.

BUG=b:192947843

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: I576c9e4c6c82d6b4055b0a0a9a75c677d4b05220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06 22:20:32 +00:00
Derek Huang 796ea820f2 ec/google/chromeec: Update google_chromeec_usb_pd_get_info()
google_chromeec_usb_pd_get_info() is used in ec.c only. Make it
static and drop from ec.h.

BUG=b:192947843

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06 22:20:11 +00:00
Derek Huang 63ffc1adc0 ec/google/chromeec: Add new API for USB-C mux handling
Add google_chromeec_get_usbc_mux_info() to obtain USB-C mux
related information.

BUG=b:192947843

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06 22:19:29 +00:00
Derek Huang c0bd123408 ec/google/chromeec: Add APIs for USB-C DP ALT mode
Add API to allow AP to send the command to EC to enter DP ALT mode
and API to wait for DP HPD event.

BUG=b:192947843
TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build
coreboot and update your system. Boot the system you will find below
message in the coreboot log with or without USB-C display connected:
'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'.

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06 22:19:00 +00:00
Derek Huang c0f005a5d6 ec/google/chromeec: Update some PD and DisplayPort APIs
1. Update google_chromeec_pd_get_amode() to return bitmask.
2. Update google_chromeec_wait_for_displayport() to handle the
   updated return value of google_chromeec_pd_get_amode().
3. Drop google_chromeec_pd_get_amode() from ec.h and make it static
   because it's not used outside of ec.c.

BUG=b:192947843

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06 22:17:42 +00:00
Derek Huang f1f9b3d5f5 ec/google/chromeec: Update google_chromeec_usb_pd_control()
Add parameter `active_cable` to obtain the cable type
(active or passive) which is needed for USB-C configuration for
some SoCs (at least Intel TGL and ADL), change the function name to
google_chromeec_usb_pd_get_info() for better understanding.

BUG=b:192947843

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06 22:17:05 +00:00
Derek Huang 89d8260e3f include/device: Generic interface for USB-C mux operations
Create a generic interface to allow any of the EC or other drivers
to provide set of USB-C mux operations.

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-06 22:16:48 +00:00
Subrata Banik d6da4ef69e soc/intel/alderlake: Skip setting D0I3 bit for HECI devices
This patch skips setting D0I3 bit for all HECI devices by FSP.

BUG=b:200644229
TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is
set to `1`.

Change-Id: I86d61c49b8f187611efd495712ad901184665f31
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-06 19:35:41 +00:00
Subrata Banik 78e66ad63b soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS
`heci_finalize` ensures to put all heci devices to D3 by setting the
D0i3 bit prior to booting to the OS.

BUG=b:200644229
TEST=Verified D0i3 bit is set for all HECI devices prior to booting
to OS.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06 19:04:56 +00:00
Subrata Banik 3710e9972b soc/intel/common: Helper function to check CSE device `devfn` status
This patch creates a helper function in cse common code block to check
the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and
CSE_4.

Currently cse common code is only able to read the device state of
`PCH_DEVFN_CSE` CSE device alone.

Additionally, print `slot` and 'func' number of CSE devices in case
the device is either disable or hidden.

BUG=b:200644229
TEST=Able to build and boot ADLRVP-P with this patch where the serial
message listed the CSE devices that are disabled in the device tree
as below:

HECI: CSE device 16.01 is disabled
HECI: CSE device 16.04 is disabled
HECI: CSE device 16.05 is disabled

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06 19:03:55 +00:00
Subrata Banik c6e2552ce6 soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices
This patch ensures to pass cse device function number as argument for
`set_cse_device_state()` to allow coreboot to perform enable/disable of
D0i3 bit for all CSE devices to put the CSE device to Idle state or
Active state.

BUG=b:200644229
TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is
able to put the CSE device toidle state or active state based on `devfn`
as argument.

Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06 19:03:31 +00:00
Raul E Rangel db16ac9578 lib/thread: Remove thread stack alignment requirement
CPU_INFO_V2 now encapsulates the cpu_info requirements. They no longer
need to leak through to thread.c. This allows us to remove the alignment
requirement.

BUG=b:179699789
TEST=Reboot stress test guybrush 50 times.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05 22:40:25 +00:00
Raul E Rangel 968f140ecb Revert "soc/amd/cezanne: Disable Co-op multitasking"
This reverts commit 5f80e7c764.

The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2
into this patch to satisfy the dependency.

BUG=b:194391185, b:179699789
TEST=reboot stress test guybrush for 50 iterations.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05 22:39:38 +00:00
Raul E Rangel c842c59b3e lib/thread: Switch to using CPU_INFO_V2
CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1
cpu_info struct per cpu. This means that we no longer need to allocate
it at the top of each threads stack.

We can now in theory remove the CONFIG_STACK_SIZE alignment on the
thread stack sizes. We can also in theory use threads in SMM if you are
feeling venturesome.

BUG=b:194391185, b:179699789
TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING
enabled.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05 22:39:16 +00:00
Raul E Rangel b2346a56f1 arch/x86,cpu/x86: Introduce new method for accessing cpu_info
There is currently a fundamental flaw in the current cpu_info()
implementation. It assumes that current stack is CONFIG_STACK_SIZE
aligned. This assumption breaks down when performing SMM relocation.

The first step in performing SMM relocation is changing the SMBASE. This
is accomplished by installing the smmstub at 0x00038000, which is the
default SMM entry point. The stub is configured to set up a new stack
with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point
of smm_do_relocation located in RAMSTAGE RAM.

This means that when smm_do_relocation is executed, it is running in SMM
with a different sized stack. When cpu_info() gets called it will be
using CONFIG_STACK_SIZE to calculate the location of the cpu_info
struct. This results in reading random memory. Since cpu_info() has to
run in multiple environments, we can't use a compile time constant to
locate the cpu_info struct.

This CL introduces a new way of locating cpu_info. It uses a per-cpu
segment descriptor that points to a per-cpu segment that is allocated on
the stack. By using a segment descriptor to point to the per-cpu data,
we no longer need to calculate the location of the cpu_info struct. This
has the following advantages:
* Stacks no longer need to be CONFIG_STACK_SIZE aligned.
* Accessing an unconfigured segment will result in an exception. This
  ensures no one can call cpu_info() from an unsupported environment.
* Segment selectors are cleared when entering SMM and restored when
  leaving SMM.
* There is a 1:1 mapping between cpu and cpu_info. When using
  COOP_MULTITASKING, a new cpu_info is currently allocated at the top of
  each thread's stack. This no longer needs to happen.

This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so
reviewers can feel more comfortable knowing most of the CL is a no-op. I
would eventually like to remove most of the guards though.

This CL does not touch the LEGACY_SMP_INIT code path. I don't have any
way of testing it.

The %gs segment was chosen over the %fs segment because it's what the
linux kernel uses for per-cpu data in x86_64 mode.

BUG=b:194391185, b:179699789
TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct
%gs segment. Verify cpu_info looks sane. Verify booting to the OS
works correctly with COOP_MULTITASKING enabled.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05 22:38:45 +00:00
Michael Niewöhner 9990866fcf drivers/intel/fsp2_0: don't force-use `python2`
Some distributions (e.g. NixOS, Debian) are actively working on getting
rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and
Python 3 as of upstream commit 0bc2b07, use whatever version is present
by utilizing `python`.

Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-10-05 20:33:18 +00:00
Martin Roth 26f97f9532 src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05 18:07:08 +00:00
Martin Roth 50863daef8 src/mainboard to src/security: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-05 18:06:52 +00:00
Martin Roth 0949e73906 src/acpi to src/lib: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05 18:06:39 +00:00
Martin Roth 6c3ece9c9e Documentation: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05 18:06:24 +00:00
Nick Vaccaro d4c55353e0 driver/intel/pmc_mux/conn: Add type-c port info to cbmem
This change adds type-c port information for USB type-c ports to cbmem.

BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer2 to kernel, log in and check cbmem for type-c info exported to
the payload:
  localhost ~ # cbmem -c | grep type-c
  added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
  added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0

Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-05 03:44:37 +00:00
Sheng-Liang Pan 2970f45fe6 mb/google/trogdor: Add new vaviant quackingstick
New boards introduced to trogdor family.

BUG=b:201263032
BRANCH=none
TEST=make

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I8299ddda14eb82103f17f8464a14992aa757afa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-04 22:40:03 +00:00
Meera Ravindranath 1399442289 soc/intel/adl: Drop SGPM, RGPM and EGPM methods
These methods can now be dropped as Dynamic GPIO PM is enabled.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0c7b67b5414d8c80775ab7678ce7b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 19:51:07 +00:00
Meera Ravindranath a7c333362c mb/*/brya/variants/brask: Enable dynamic GPIO PM
GPIO PM was disabled for brask to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. This change drops the GPIO PM override and
re-enables dynamic GPIO PM.

TEST=Boot brask to OS, ensure no TPM errors.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-10-04 19:50:43 +00:00
Meera Ravindranath 94a03fff07 mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM
GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. This change drops the GPIO PM override and
re-enables dynamic GPIO PM.

TEST=Boot adlrvp to OS, ensure no TPM timeout errors.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-04 19:49:38 +00:00
David Wu 126162c38f mb/google/brya: Enable DDR4 SODIMM for brask
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in
brask device tree and add SPD addressese for the two DIMMs.

Separate the Kconfig items of brya and brask. Move
HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya
and add config SPD_CACHE_IN_FMAP to brask.

Add a new section RW_SPD_CACHE to fmd for caching SPD data.

The renamed romstage.c is used by both brya and brask and a new
function variant_get_spd_info is provided to support the different
SPD source types.

BUG=b:194055762
BRANCH=None
TEST=build pass

Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 18:41:03 +00:00
Ryan Lin 4a48dbe60b src/soc/intel/alderlake: Add PsysPmax setting
This patch feeds PsysPmax setting to FSP through UPD and adds a
PsysPmax member in chip information so that we can set PsysPmax
through devicetree. The PsysPmax needs to be set correctly mapping
to maximum system power. Otherwise, system performance would be limited
due to the default PsysPmax setting in FSP is only 21W.

BUG=b:193864533, b:195615830
TEST=Set PsysPmax to an example value eg 145 in devicetree &&
put debug code in FSP to print the PsysPmax value before sending
to Pcode, ensure the setting is correctly programmed.

Change-Id: Ia07aa815f90739240f110cab984068237c02d896
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 17:45:38 +00:00
Nick Vaccaro 15066ba8d4 driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h
Move the locally declared typec_orientation enum from chip.h to
coreboot_tables.h.

Change enum typec_orientation name to type_c_orientation for consistency
with contents of coreboot_tables.h.

Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE.

BUG=b:149830546
TEST="emerge-volteer coreboot" and make sure it compiles successfully.

Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-04 17:15:47 +00:00
Nick Vaccaro a62b41819c coreboot tables: Add type-c port info to coreboot table
This change adds type-c port information for USB Type-C ports to the
coreboot table.  This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.

BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds
successfully.  Cherry-pick CL to enable this feature for volteer,
flash and boot volteer2 to kernel, log in and check cbmem for type-c
info exported to the payload:
  localhost ~ # cbmem -c | grep type-c
  added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
  added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0

Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 17:12:48 +00:00
Felix Held 56da0b79ad lib/hardwaremain: change type of "complete" element in boot_state struct
A signed bitfield with a length of 1 bit can only have the values 0 and
-1. Assigning a 1 ends up behaving as expected, but it's not the
semantically correct thing to do there. Changing the type of the element
to an unsigned bitfield with a length of 1 would fix that, but since
this is used as a boolean value, just change it to bool type.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-04 15:58:32 +00:00
Felix Held f10776781d lib/hardwaremain: add missing types.h include
The u8 type is used in the file, but neither stdint.h not types.h was
included in the file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd67aff9eba01f9618004c869f1473217b3aeae4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-04 15:58:10 +00:00
Lai, Jim ae9a84478f mb/google/brya/variants/kano: Correct MIPI camera info
Correct OVTI2740 information for Kano:
MIPI camera CIO port, HID and Link Freq

BUG=b:200974074
TEST=Build and boot on Kano
     camera driver is not probed before,
     and it can now be probed properly
     after this change.

Signed-off-by: Lai, Jim <jim.lai@intel.com>
Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 07:59:31 +00:00
Rex-BC Chen 5020fe3449 util/cbfstool: Add support for ARM64 UefiPayload
UEFI payload is supported on some ARM64 platforms, for example MT8195.
As a result, add MACHINE_TYPE_ARM64 to support ARM SystemReady.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4c0c6e263bd2f518a62ff9db44d72dd31086756a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-10-04 02:31:01 +00:00
Michael Niewöhner 880acbe2f4 soc/intel/common: round PM Timer emulation frequency multiplier
Round the PM Timer emulation frequency multiplier to the closest value
to increase precision.

Test: compared hexdumps of CML binaries for the expected result:
      before: 0x262E8B51, after: 0x262E8B52

Change-Id: Iafd645c248fc17943ea4be558ed7d01a301ba809
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57943
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-02 21:00:42 +00:00
Rex-BC Chen f4d6e9085d soc/mediatek: add debug dump for ltiming and clock_div
ltiming and clock_div are not support for MT8173, so we separate them
to weak function: mtk_i2c_dump_more_info()

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I3228c6953be5fac18a76029702b878a34c7563f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58074
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-02 11:50:22 +00:00
Daolong Zhu f4b71734b2 soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed
1. The original algorithm for I2C speed cannot always make the
   timing meet I2C specification so a new algorithm is introduced
   to calculate the timing parameters more correctly.
2. Some I2C buses should be initialized in a different speed while
   the original implementation was fixed at fast mode (400Khz).
   So the mtk_i2c_bus_init is now also taking an extra speed
   parameter.

There is an equivalent change in kernel side:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1

BUG=b:189899864
TEST=Test on Tomato, boot pass and timing pass
     at 100/300/400/500/800/1000Khz.

Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com>
Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-02 11:48:34 +00:00
Subrata Banik 38abbdab71 soc/intel/common/../cse: Avoid caching of CSE BAR
This patch ensures all attempts to read CSE BAR is performing PCI config
space read and returning the BAR value rather than using cached value.

This refactoring is useful to read BAR of all CSE devices rather than
just HECI 1 alone.

Additionally, change the return type of get_cse_bar() from `uintptr_t`
to `void *` to avoid typecasting while calling read32/write32 functions.

BUG=b:200644229
TEST=Able to build and boot ADLRVP where CSE is able to perform PCI
enumeration and send the EOP message at post.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-02 08:44:42 +00:00