Commit Graph

19 Commits

Author SHA1 Message Date
Elyes HAOUAS c8d24dd150 SPD: fix and add DDR2 SDRAM memory module types
Correct the definitions and add 72b-SO-CDIMM and 72b-SO-RDIMM

Change-Id: I33532e30f45f6c8c0eb6d47b0bea87689d2d9a1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15204
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24 18:09:18 +02:00
Elyes HAOUAS 46bfce3353 spd: Add module voltage for 1.8V
Add SSTL 1.8 V Interface Level as specified in
JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10.

Change-Id: I0112a85f557826b629109e212dbbc752aeda305d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15202
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24 18:08:04 +02:00
Elyes HAOUAS d450609145 Added CL7 support
according to "JEDEC_DDR2_SPD_Specification_Rev1.3.pdf"
Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)
page 16 and page 60, CL7 support added

Change-Id: I22aaf064ab8767755f74dfdb44e32d13fc61b2c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/14976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-14 23:54:51 +02:00
Patrick Georgi a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Patrick Georgi b890a1228d Remove address from GPLv2 headers
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.

However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.

util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.

$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
	-a \! -name \*.patch \
	-a \! -name \*_shipped \
	-a \! -name LICENSE_GPL \
	-a \! -name LGPL.txt \
	-a \! -name COPYING \
	-a \! -name DISCLAIMER \
	-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +

Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-21 20:50:25 +02:00
Kane Chen 33faac643d smbios: add funtion for smbios type17
Add smbios type 17 which can optionally be implemented
at the platform or mainboard level
In order to create SMBIOS type17, you will need to fill
memory_info data

BUG=None
BRANCH=None
TEST=Compile successfully on rambi and samus
     Boot to chromeOS on samus and rambi

Original-Change-Id: Ie4da89135c879d7a687305d423103fcfcbb96e3f
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210005
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 634b899ba41242caa800d7b570f3a339c738db77)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I61d1e8b1d32d43f0011b0f93966d57646ea0eb63
Reviewed-on: http://review.coreboot.org/8955
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-27 09:55:21 +01:00
Alexandru Gagniuc 32610462d1 spd.h: Add all known SPD_MEMORY_TYPE definitions.
This file was missing some definitions, so add them. Also turn the defines
into an enum. The reason for doing this is that functions can now
explicitly take an spd_memory_type as a parameter:

> int do_something_with_dram(enum spd_memory_type type, ...)

Which is a lot more explicit and readable than:

> int do_something_with_dram(u8 type, ...)

These are used in the VX900 branch.

Change-Id: Ic7871e82c2523a94eac8e07979a8e34e0b459b46
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3266
Tested-by: build bot (Jenkins)
2013-06-03 22:35:21 +02:00
Paul Menzel a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Uwe Hermann d773fd370a Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.

 - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
   romstage.c files and lots of spd_addr.h files. Don't even bother for
   those spd_addr.h which aren't even actually used, drop them right away.

 - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
   and 0xa0 with (DIMM0 << 1) where appropriate.

 - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
   SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.

 - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.

 - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
   Then, replace 0xa0 (which now becomes 0x50) with DIMM0.

 - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.

 - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20 20:23:08 +00:00
Patrick Georgi 9bd9a90d6a Unify DIMM SPD addressing. For Geode, change the
addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).

abuild tested.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20 10:31:00 +00:00
Ed Swierk d39aad9323 Add definitions for DDR2 SPD registers.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 18:23:58 +00:00
Stefan Reinauer 951c62f074 add some SPD values from specs. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:40:16 +00:00
Stefan Reinauer 7e61e45402 Please bear with me - another rename checkin. This qualifies as trivial, no
code is changed.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 10:35:56 +00:00
Corey Osgood 02b2365f02 This patch is some small changes to the vt8237r to prepare it for
the Jetway J7F2 patch that should be coming soon, and also moves most
defines into vt8237r.h. I've changed some of the values from u32 to u8,
because that's all they should ever need to be. Also includes
doxygenized comments!

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-03 18:45:42 +00:00
Marc Jones bc8176c552 This patch adds support for the AMD Geode LX CPU. (rediffed)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 18:24:55 +00:00
Uwe Hermann 998a57c477 Update of the src/include/spd.h file with the following improvements:
* Added information on the relevant datasheet(s) and where to get them.
 * Added missing #defines for some other config bytes.
 * Documented all config bytes a bit better.
 * Renamed some #defines to hopefully make their names clearer. 

(closes #38)

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-22 11:41:32 +00:00
Stefan Reinauer eca92fb371 Uwe Hermann:
here's a patch which replaces all DOS newlines with Unix newlines, and
removes some useless $Rev$, $Id$, and $Header$ tags.
(part 1)



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-23 14:28:37 +00:00
Stefan Reinauer 6ab43fcc48 Updating FSF address in the code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-05 18:17:45 +00:00
Steven J. Magnani 61764f45dc Initial revision.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-13 14:54:25 +00:00