Commit Graph

4613 Commits

Author SHA1 Message Date
Felix Singer 2060bff9c0 utils/cbfstool: Fix building with `make test-tools`
The variable `RM` is empty and thus set it to `rm`. While
executing the `clean` rule, run each `rm` command with the -f flag
to ignore non-existing files.

Also, disable the objutil feature locally fixing another build issue.

Change-Id: Icb17e2c924ef480f8ac6195f96cf495709a0a023
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62415
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-27 18:29:24 +00:00
Martin Roth e61e7789c2 util/testing: Add cbfstool tools to tested utils
Previously, cbfstool was tested as part of the coreboot build, but not
tested individually. This let a change that broke elogtool slip through.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9e7b7a01d4a77ffdac932ba5af12cbd1ba96628b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-27 02:21:23 +00:00
Martin Roth e3e965b13d Revert "util/cbfstool: Port elogtool to libflashrom"
This reverts commit d74b8d9c99.

This change breaks the 'make all' build of the cbfstool tools
from the util/cbfstool directory unless libflashrom-dev is
installed, complaining that flashrom is not installed.

Even with libflashrom-dev installed, it breaks building
elogtool with the public version of libflashrom-dev.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I572daa0c0f3998e20a8ed76df21228fdbb384baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62404
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 01:24:17 +00:00
Elyes HAOUAS a0b8032279 crossgcc: Upgrade LLVM/clang from 12.0.0 to 13.0.1
Build/run not tested on board.

Change-Id: I8c550d3528a5b1c891b318c08ecfba3a9255e69c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59400
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 00:44:10 +00:00
Zheng Bao fdb0294846 amdfwtool: Check the real length of PMU string
The length should be checked before the PMU_STR_INS_INDEX(th) character
is accessed, otherwise it is going to an access violation.

Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-24 00:41:45 +00:00
Felix Singer 88ccd4863c util/nixshell: Add a Nix shell for building documentation
Add a Nix shell config allowing to build the coreboot documentation.

Change-Id: I1c9715c677342241b78fbdef0afeb4536f48d50f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-22 10:31:41 +00:00
Zheng Bao e220faa18a amdfwtool: Add entries for PMUI & PMUD with instance 2
Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21 23:48:57 +00:00
Zheng Bao 990d154898 amdfwtool: Add support for AMD's BIOS A/B recovery feature
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
              0x4A -> PSP L2 B -> BIOS L2 B

The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.

To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.

TEST=Majolica(Cezanne)

Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 23:47:20 +00:00
Zheng Bao 1a9e54302b soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.

Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 21:29:50 +00:00
Felix Singer 3a5e6f529c util/liveiso: Use programs.flashrom.enable
NixOS 21.11 introduced the option `programs.flashrom.enable`. The option
allows installing flashrom and hooking up its udev rules. Thus, set it
to `true` and add the user `user` to the `flashrom` group allowing it to
use the programmers.

Change-Id: I017ddb4314702a5252dfc0d05cd1e4961043d23b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-21 15:25:18 +00:00
Elyes HAOUAS e854b0b5e7 crossgcc: Upgrade CMake to 3.22.2 version
Change-Id: I4272f72dd6ed686dbad5615a0ab44c8c632b5930
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-21 08:05:48 +00:00
Karthikeyan Ramasubramanian e1d6f5b80d util/spd_tools/spd_gen/lp5: Encode Bank Architecture
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or
16B Bank Architectures depending on the speed. This influences SDRAM
Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the
individual SoC advisories.

BUG=b:211510456
TEST=Generate SPDs for Sabrina.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17 21:43:29 +00:00
Karthikeyan Ramasubramanian 3248db0e5a util/spd_tools/spd_gen/lp5: Encode Optional SDRAM features
ADL and Sabrina provide different advisories to encode Optional SDRAM
features (byte indices 7 & 9). Encode those bytes as per the respective
advisories.

BUG=b:211510456
TEST=Generate the SPD binaries for Sabrina.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17 21:43:10 +00:00
Matt DeVillier 1dc1a56a5d util/chromeos/crosfirmware: format with shfmt
Clean up formatting using shfmt

Change-Id: I46ce84668bfb4ea3df179317e2848b6bb75d8d5c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-02-15 23:43:55 +00:00
Felix Held 72236b475f util/amdtools/README,description.md: add update_efs_spi_speed docs
This change is mostly from CB:56644 patchset 3.

Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idece950bab260a099c9790485805cbe8ea641666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-15 23:32:52 +00:00
Felix Held f57bf3f994 util/amdtools/description.md: add description for the different tools
This change is mostly from CB:56644 patchset 3.

Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4cb9bbb3d7fd5d7c9e33fbf656301c0beb2f1b47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-15 23:32:37 +00:00
Felix Held 6198a8213a util/amdtools/README: convert to markdown
This change is mostly from CB:56644 patchset 3.

Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idcee9de9bc409a4dfe7d2f8c18ec5132f2747c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-15 23:32:09 +00:00
Michał Żygowski 8ac40f3ea7 util/inteltool: Add support for Tiger Lake chips detection and GPIOs
Add PCI IDs for Tiger Lake LP and Tiger Lake H devices and their GPIO
tables.

TEST: dump GPIOs on i5-1135G7, Tiger Lake H untested

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6071a999be9e8a372997db0369218f297e579d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-15 19:44:08 +00:00
Zheng Bao 6c5ec8e31c amdfwtool: Add options to support mainboard specific SPL table
For the generic board which uses Cezanne, we use the generic SPL
table. For the Guybrush Chromebook, we need to use a customized SPL
file.

BUG=b:216096562

Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12 16:36:07 +00:00
Benjamin Doron 39cf79900f util/inteltool: Actually read SATA init data from SIRD
Fix issue where registers always seem to contain their own offset.

After writing the desired register into SIRI, the requested data is
returned in SIRD. This register is 4 bytes after SIRI, commonly 0xA4.

Tested on TGL-H (SATA SIR registers are common), genuine data is
returned.

Change-Id: I322b11d53178e5b64e353c1b4e576548592c16c3
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-12 11:29:33 +00:00
Matt DeVillier b0844490db util/chromeos/crosfirmware: Handle "broken" recovery images
Several recovery images for newer ChromeOS boards fail in
extract_partition() due to parted detecting that there are overlapping
partitions, and therefore failing to print the partition layout
(this is potentially a parted bug; requries further investigation).

To work around this, fall back to using fdisk, making the assumption
that ROOT-A is always partition #3, and calculate the partition
start and size using the sector size.

Test: successfully extract coreboot firmware images from recovery
images which previously failed to extract (fizz, octopus, volteer).

Change-Id: I03234170ba0544af9eb0879253f0a8e0e7bf33f5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-11 23:57:03 +00:00
Matt DeVillier e42731603e util/chromeos/crosfirmware: Fix handling of newer boards
Wile historically there was a unique recovery image for each Chrome OS
board/HWID (with matching names), this is no longer the case. Now,
multiple boards share a single recovery image, so adjust how the proper
recovery image is determined, and how the coreboot image is extracted from it.

Test: successfully extract coreboot images for older 1:1 boards (e.g. CAVE)
and newer 1:N boards (e.g. DROBIT)

Change-Id: If478aa6eadea3acf3ee9d4c5fa266acd72c99b7a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-11 23:56:47 +00:00
Julius Werner b8258bd2b9 util/cbmem: Add --loglevel option to restrict console printing by level
This patch adds a new --loglevel option to the CBMEM utility which can
be used either numerically (e.g. `cbmem -1 --loglevel 6`) or by name
(e.g. `cbmem -c --loglevel INFO`) to restrict the lines that will be
printed from the CBMEM console log to a maximum loglevel. By default,
using this option means that lines without a loglevel (which usually
happens when payloads or other non-coreboot components add their own
logs to the CBMEM console) will not be printed. Prefixing a `+`
character to the option value (e.g. `--loglevel +6` or
`--loglevel +INFO`) can be used to change that behavior.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8458027083246df5637dffd3ebfeb4d0a78deadf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 23:56:13 +00:00
Wonkyu Kim 3922aa5c2c util/ifdtool: add generic `PLATFORM_IFD2` for early SoC development
`PLATFORM_IFD2` macro is more generic tag that can be associated with
early next SoC platform development which using IFDv2.

The current assumption is that newer SoC platform still uses the same
SPI/eSPI frequency definition being used for latest platform(TGL, ADL)
and if the frequency definition is updated later, `PLATFORM_IFD2' will
use latest frequency definition for early next SoC development.
And once upstream is allowed for new platform, platform name will be
added in tool later.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09 14:19:47 +00:00
Karthikeyan Ramasubramanian 55ba8df28c util/spd_tools/spd_gen/lp5: Update BusWidth Encoding
ADL and Sabrina have different advisory regarding encoding the bus
width. Encode the bus width as per the respective advisories.

BUG=b:211510456
TEST=Build spd_gen and ensure that the bus width is encoded as expected.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia12a5bd8f70a70ca8a510ecf00f6268c6904ec25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-08 17:37:18 +00:00
Julius Werner 984d03c492 console: Add loglevel marker codes to stored consoles
In order to provide the same loglevel prefixes and highlighting that
were recently introduced for "interactive" consoles (e.g. UART) to
"stored" consoles (e.g. CBMEM) but minimize the amont of extra storage
space wasted on this info, this patch will write a 1-byte control
character marker indicating the loglevel to the start of every line
logged in those consoles. The `cbmem` utility will then interpret those
markers and translate them back into loglevel prefixes and escape
sequences as needed.

Since coreboot and userspace log readers aren't always in sync,
occasionally an older reader may come across these markers and not know
how to interpret them... but that should usually be fine, as the range
chosen contains non-printable ASCII characters that normally have no
effect on the terminal. At worst the outdated reader would display one
garbled character at the start of every line which isn't that bad.
(Older versions of the `cbmem` utility will translate non-printable
characters into `?` question marks.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I86073f48aaf1e0a58e97676fb80e2475ec418ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07 23:28:37 +00:00
Zheng Bao ab84fd7605 amdfwtool: Add SPL support
SPL: Security Patch Level
The data in SPL is used for FW anti-rollback, preventing rollback of
platform level firmware to older version that are deemed vulnerable
from a security point of view.

BUG=b:216096562

Change-Id: I4665f2372ccd599ab835c8784da08cde5558a795
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07 18:38:40 +00:00
Karthikeyan Ramasubramanian d5ae3f908a util/spd_tools/spd_gen: Add support for Sabrina SoC
Add support to generate SPD binary for Sabrina SoC. Mainboards using
Sabrina SoC are planning to use LP5 memory technology. Some of the SPD
bytes expected by Sabrina differ from the existing ADL. To start with,
memory training code for Sabrina expects SPD Revision 1.1. More patches
will follow to accommodate additional differences.

BUG=b:211510456
TEST=make -C util/spd_tools.
Generate SPD binaries for the existing memory parts in
lp5/memory_parts.json and observe that SPDs for Sabrina is generated as
a separate set without impacting the ADL mainboards.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-07 14:09:52 +00:00
Jeff Daly 3623eca525 util/ifdtool: Add additional regions for platforms that support them
Some Intel SoCs such as Denverton support additional SPI regions for
things like Innovation Engine firmware or 10GbE LAN firmwares

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ia5a450e5002e9f8edee76ca7c2eede9906df36c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-04 20:11:10 +00:00
Martin Roth 1039d27856 util/crossgcc: Update this for normailze_dirs()
Currently, the function normalize_dirs() fails if the directories lib32
and lib64 don't exist.  That can be fixed by using an rm -rf on it
instead of rmdir.

The cmake build doesn't create those directories, so was showing a
failure message after the build was already completed.  That's fixed by
removing normailze_dirs() from the build_CMAKE() function.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iea6e3ca57fb91ff1234be875861b27a78972d9ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-03 13:50:16 +00:00
Elyes HAOUAS f2a9c8d57c util/lint/checkpatch.pl: Use "git_command"
This is to reduce difference with linux v5.16.

Change-Id: I7abd4d8eed856eee841422515db2ff7f50ecd0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01 17:34:28 +00:00
Elyes HAOUAS 18ef52083d util/lint/checkpatch.pl: Use "gitroot"
This is to reduce difference with linux v5.16.

Change-Id: I3bdf880c8b6068467665865b7cf1249d1047e833
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:49 +00:00
Elyes HAOUAS 249c4044c2 util/lint/checkpatch: Update "check for missing blank lines after declarations"
This is to reduce difference with linux v5.16.

Change-Id: I1b7bc2b4ec832f0abeda215c381856a5ec153883
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:40 +00:00
Elyes HAOUAS ac69049030 util/lint/checkpatch.pl: Update 'commit message line length limit'
Also add "coreboot" comment on our modification.

Change-Id: Ida58a92457e25bac7fb89bb5882e7647f388ec01
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:31 +00:00
Elyes HAOUAS 919b0c7d4d util/lint/checkpatch.pl: Remove unneeded whitespaces and fix some typos
This is to reduce difference with linux v5.16.

Change-Id: I4aa7abce83b41ccd5129717cd3bf85be19ec4807
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:22 +00:00
Elyes HAOUAS 48cb78b6d9 util/lint/checkpatch.pl: Use "perl_version_ok"
Also use '$minimum_perl_version'.
This is to reduce difference with linux v5.16.

Change-Id: I7c2f5d5c9853dc8ddc8f89a5e2edd6c8613ba790
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:13 +00:00
Elyes HAOUAS 96771bf92c util/lint/checkpatch.pl: Use "tabsize"
This is to reduce difference with linux v5.16.

Change-Id: Ifeb9c4406737fa24f9bd803af48d8b8d17654940
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:45:44 +00:00
Martin Roth 38c7314137 util/lint: Remove SuperIO from checkpatch spellcheck
Patch 423e9e0fc0: Documentation/lint: Use Super I/O instead of SuperIO
added the word SuperIO to the checkpatch spelling list.

There were unfortunately some issues with this.

1) This introduced a problem because the comparison is used in different
cases in different places.  The misspelled word is compared ignoring
the case, but when looking for the correct word, it looks through the
list for the misspelling in all lowercase.  When it couldn't find the
word "superio" in the list, the variable came back uninitialized.

2) The spellcheck feature isn't enabled in checkpatch unless the option
--strict is enabled, so this wasn't getting reported anyway.

3) SuperIO (or superio) will match the KCONFIG options such as
CONFIG_SUPERIO_NUVOTON_NCT5104D, and suggest "Super I/O" which doesn't
make any sense.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I464305af539926ac8a45c9c0d59eeb2c78dea17a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-31 03:34:30 +00:00
Fred Reitberger bfdc132436 util/lint/lint-stable-003-whitespace: add exception for gif files
Adding gif files to the whitespace exclude list, to prevent issue where
commits were failing due to binary files.

Change-Id: I56679780348579d01c81c6f1677e4ea456315c9e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61460
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-28 20:36:38 +00:00
Elyes HAOUAS ad3828e3ce crossgcc: Update acpica from 20210331 to 20211217
Changes:
 Version 20211217: https://acpica.org/node/197
 Version 20210930: https://acpica.org/node/196
 Version 20210730: https://acpica.org/node/195
 Version 20210604: https://acpica.org/node/193

Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-28 16:35:13 +00:00
Matt DeVillier 648a44acbc util/chromeos: Update extract_blobs script
- Handle older CrOS firmware which lacks a COREBOOT FMAP region
- Add support for all blobs used in CrOS firmware 2013 to current
- Put extracted blobs in their own directory

Change-Id: Idaa39eca3be68a9327cead9b21c35a6c7a3a8166
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-27 22:06:10 +00:00
Sean Rhodes 0015df5927 util/coreboot-configurator: Add contrib files
Add contrib files for:
* debian (Tested on Ubuntu 20.04, 21.10, MX Linux 21 and Debian)
* PKGBUILD (Tested on Manjaro 21)
* flatpak (Untested)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie9f0193ed28c0842661426204fc88ec00091fbae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-27 16:17:42 +00:00
Sean Rhodes 9c89e3ada2 util: Add coreboot-configurator
A simple GUI to change settings in coreboot's CBFS, via the nvramtool utility.

Test on the StarBook Mk IV running coreboot 4.15 with:
* Ubuntu 20.04
* Ubuntu 21.10
* MX Linux 21
* elementary OS 6
* Manjaro 21

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I491922bf55ed87c2339897099634a38f8d055876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-27 16:16:23 +00:00
Zhuohao Lee d9e50b1343 util/mb/google: add support for brask
Add the file templates for creating a new variant of Brask.

BUG=b:215091592
TEST=new_variant.py and build coreboot pass for the new variant.

Change-Id: I67e4ed450d6033fed7419bd7c76c127ecd942fe8
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-26 19:51:03 +00:00
Bora Guvendik e383b3dcc4 util/cbmem: Rebase to handle negative timestamps
Rebase all of the timestamps to the lowest (potentially negative) value
in the list when displaying them. Also drop the extra
`timestamp_print_*_entry` calls for time 0 and instead inserted a
"dummy" timestamp entry of time 0 into the table.

TEST=Boot to OS after adding negative timestamps, cbmem -t

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I7eb519c360e066d48dde205401e4ccd3b0b3d8a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-21 22:43:03 +00:00
Edward O'Callaghan d74b8d9c99 util/cbfstool: Port elogtool to libflashrom
This also uncouples cbfstool from being overly Chromium
specific. However the main objective is to not subprocess
flashrom any more and instead use the programmatic API.

BUG=b:207808292
TEST=built and ran `elogtool (list|clear|add 0x16 C0FFEE)`.

Change-Id: I79df2934b9b0492a554a4fecdd533a0abe1df231
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
2022-01-14 23:10:55 +00:00
Alex James b3398ba562 util/cbfstool: Do minor fixes
- Fix truncation of stage->loadaddr by replacing be32toh with be64toh
- Remove some redundant htobe32 calls
- Address checkpatch lints

Change-Id: I81b8cfd9eb0b2feffefaa9338bac9ae209e39a3c
Signed-off-by: Alex James <theracermaster@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-12 16:15:09 +00:00
Alex James 02001a38be util/cbfstool: Replace swab.h with commonlib/bsd/sysincludes.h
Instead of maintaining another set of byteswapping functions in
cbfstool, this change removes swab.h and replaces it with
bsd/sysincludes.h from commonlib. Callers have been updated to use
be32toh/be64toh/htobe32/htobe64 instead of ntohl/ntohll/htonl/htonll
respectively.

Change-Id: I54195865ab4042fcf83609fcf67ef8f33994d68e
Signed-off-by: Alex James <theracermaster@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-10 21:32:34 +00:00
Rob Barnes f26ce9f00e util/apcb: Add apcb_v3_edit tool
apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
up to 16 SPDs into an existing APCB. The APCB must have a magic number
at the top of each SPD slot.

BUG=b:209486191
BRANCH=None
TEST=Inject 4 SPDs into magic APCB, boot guybrush with modified APCB

Change-Id: I9148977c415df41210a3a13a1cd9b3bc1504a480
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-10 14:25:32 +00:00
Hsuan Ting Chen bdad283237 docker/Makefile: Use all instead of all_without_gdb
After removing GDB from crossgcc in commit f32eed16 (buildgcc: Remove
GDB from crossgcc), there is no target named all_without_gdb anymore
and we should always build crossgcc with target all.

But in util/docker/Makefile, we still try to build crossgcc with
target all_without_gdb as default and will cause a build failure.

Set CROSSGCC_PARAM from all_without_gdb to all to fix this issue.

Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I06c6d8e36dfd4e6a00ddec8b640b608ab1ba614c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-04 21:08:43 +00:00
Alex James 2219d89d9d cbfstool: Avoid defining _XOPEN_SOURCE
This restricts availability of non-standard functions (such as memmem)
on FreeBSD and macOS. It also isn't necessary on glibc.

Change-Id: Iaee1ce7304c89f128a35a385032fce16a2772b13
Signed-off-by: Alex James <theracermaster@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-04 11:51:06 +00:00
Alex James 8a44eb9a5b util/cbfstool: Remove redundant endian.h include
flashmap/fmap.c includes commonlib/bsd/sysincludes.h, which already
includes the necessary header for endian(3) functions (endian.h on
Linux and sys/endian.h on FreeBSD). This also resolves a compilation
error on macOS (tested on 10.5.7), as macOS does not provide endian.h.

Change-Id: I0cb17eacd253605b75db8cf734e71ca3fe24ad6c
Signed-off-by: Alex James <theracermaster@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-04 11:50:11 +00:00
Elyes HAOUAS ce134ababd crossgcc/buildgcc: Remove unused GCC_AUTOCONF_VERSION
Clean up leftovers from commit d0f83723 and drop unused
GCC_AUTOCONF_VERSION.

Change-Id: I7d293ae2c8663efdc9ad4146ff32671ffd3e176a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-29 20:45:32 +00:00
Elyes HAOUAS 52607fd91e crossgcc/Makefile: Remove obsolete target build_make
coreboot does not build gnumake anymore since commit 91fb1399

Change-Id: I0f159fc912d09ebde6ac7ba5be83933aa251f1d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-29 20:45:13 +00:00
Felix Singer 9758ef9c84 util/liveiso: Install mtdutils
Change-Id: I1416d8f783518eca0606efef4314a3d86837b016
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-12-26 12:07:16 +00:00
Felix Singer eb4edc3ef1 util/liveiso: Disable write protection of the intel-spi driver
The intel-spi driver maps the BIOS region of the flash as an mtd device
at /dev/mtdX. Since this system is intended for development purposes,
disable its write protection.

Change-Id: Ib73d14eb4e7df6e29433b8dfbeb77dbab4a85f08
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-12-26 12:06:53 +00:00
Felix Singer edb4f759ea util/liveiso: Ensure compatible NixOS channel is used
Config options and package names might change from channel to channel.
Thus, don't let nix-build depend on the locally configured NixOS
channel, but instead let `nixpkgs` point to a specific channel to ensure
that always a compatible channel is used.

For now, let `nixpkgs` point to NixOS 21.11, which is currently the
latest stable release. This needs to be updated after a new release.

Change-Id: Ia77c34f93f0e2c3d351ae229830adfce75a56ae4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-12-26 12:06:37 +00:00
Felix Singer 5e4232d389 util/liveiso: Merge build scripts
Merge build scripts to `build.sh`. The new one takes the desired NixOS
config as an argument.

Example:
$ build.sh console.nix

Change-Id: I49360a5c57954a205c697a4ae07361779db2aa83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60372
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-26 12:05:23 +00:00
Edward O'Callaghan e146196030 util/futility: Ensure futility checks for flashrom as a dep
futility actually depends on flashrom. Previously it
was of the form of subprocess and now uses the libflashrom
API directly. Due to the previous subprocess decoupling it
was not obvious that the dependency existed however not
the runtime requirement is also a strict buildtime requirement.
Therefore update the Makefile accordingly.

BUG=b:203715651,b:209702505
TEST=builds

Change-Id: Id9744424f75299eb8335c1c0c2aca2808bde829d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
2021-12-25 10:12:23 +00:00
Zheng Bao 6fff2497b1 amdfwtool: Upgrade "relative address" to four address modes
Address Mode 0: Physical Address, bit 63~56: 0x00
Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40
Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80
Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0

It is the expanding mode for simple relative address mode, for which
address_mode equals 1.

Only mode 2 is added. We need to record current table base address and
calculate the offset. The ctx.current_table is zero outside the
table. When it goes into the function to integrate the table, it
should backup the old value and get current table base. Before it goes
out the function, it should restore the value.

If the table address mode is 2, the address in each entry should be
also add address mode information. If not, the address mode in entry
is meanless.

The old mode 0,1 should be back compatible.

Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-16 14:35:52 +00:00
Paul Menzel 7f5a1eeb24 Spell *Boot Guard* with a space for official spelling
See for example Intel document *Secure the Network Infrastructure –
Secure Boot Methodologies* [1].

Change all occurrences with the command below:

    $ git grep -l BootGuard | xargs sed -i 's/BootGuard/Boot Guard/g'

[1]: https://builders.intel.com/docs/networkbuilders/secure-the-network-infrastructure-secure-boot-methodologies.pdf

Change-Id: I69fb64b525fb4799bcb9d75624003c0d59b885b5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-16 14:17:36 +00:00
Julius Werner 0fd072d3f2 cbfstool: Clean up remnants of locate action
`cbfstool locate` and the associated -T switch were removed a looong
time ago (2015 in CB:11671). However, getopt and the help text weren't
cleaned up correctly. Fix that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib098278d68df65d348528fbfd2496b5737ca6246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-14 21:45:32 +00:00
Julius Werner 772714d3b3 cbfstool: Use converted buffer size for do_cbfs_locate()
The whole point of moving do_cbfs_locate() later (CB:59877) was that it
could use the file size that is actually going to be inserted into CBFS,
rather than the on-disk file size. Unfortunately, after all that work I
forgot to actually make it do that. This patch fixes that.

Since there is no more use case for do_cbfs_locate() having to figure
out the file size on its own, and that generally seems to be a bad idea
(as the original issue shows), also remove that part of it completely
and make the data_size parameter mandatory.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1af35e8e388f78aae3593c029afcfb4e510d2b8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-14 21:45:27 +00:00
Zheng Bao da83d2c97f amdfwtool: Use relative address for EFS gen2
The second generation EFS (offset 0x24[0]=0) uses "binary relative"
offsets and not "x86 physical MMIO address" like gen1.

The field additional_info in table header can tell if the absolute or
relative address is used.

Chips like Cezanne can run in both cases, so no problem
comes up so far.

The related change in psp_verstage has been uploaded.
https://review.coreboot.org/c/coreboot/+/58316

The relative mode is the mode 1 of four address modes. The absolute
mode is the mode 0. Later we will implement mode 2. Not sure if mode 3
is needed.

It needs to be simple to work with psp_verstage change to make SOC
Cezanne work quickly. This patch is defacto a subset of
    https://review.coreboot.org/c/coreboot/+/59308
which implements the framework of address mode and covers mode
0,1,2. Some hardcode value like 29 can be removed in 59308.

BUG=b:188754219
Test=Majolica (Cezanne)

Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-14 16:15:52 +00:00
Julius Werner 20ad36547e cbfstool: Do host space address conversion earlier when adding files
In cbfs_add_component(), the |offset| variable confusingly jumps back
and forth between host address space and flash address space in some
cases. This patch tries to clean that logic up a bit by converting it
to flash address space very early in the function, and then keeping it
that way afterwards. convert() implementations that need the host
address space value should store it in a different variable to reduce
the risk of confusion. This should also fix a tiny issue where
--gen-attribute might have previously encoded the base address as given
in CBFS -- it probably makes more sense to always have it store a
consistent format (i.e. always flash address).

Also revert the unnecessary check for --base-address in
add_topswap_bootblock() that was added in CB:59877. On closer
inspection, the function actually doesn't use the passed in *offset at
all and uses it purely as an out-parameter. So while our current
Makefile does pass --base-address when adding the bootblock, it actually
has no effect and is redundant for the topswap case.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Idf4721c5b0700789ddb81c1618d740b3e7f486cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-13 14:11:53 +00:00
Paul Menzel dd1ee27503 util/lint/checkpatch: Decrease commit message line length limit to 72
Currently, `checkpatch.pl`, imported from the Linux project, checks for
75 characters per line [2]:

> Suggest line wrapping at 75 columns so the default git commit log
> indentation of 4 plus the commit message text still fits on an 80
> column screen.

But Gerrit’s Web interface and its commit hooks use with 72 characters
per line [2]:

    remote: commit 35bb56d: warning: too many message lines longer than 72 characters; manually wrap lines
    remote:
    remote: SUCCESS
    remote:
    remote:   https://review.coreboot.org/c/coreboot/+/60004 [DO NOT SUBMIT] Gerrit commit msg line length test [NEW]

So, decrease the suggested length from 75 to 72 characters per line.

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2a076f40d8c9be95bee7bcf18436655e1140447f
[2]: https://review.coreboot.org/60004

Change-Id: Ic9c686cb1a902259b18377b76b5c999e94660fed
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-12-10 20:54:56 +00:00
Paul Fagerburg 18dd6b8a9a util/testing: combine code coverage data
As part of the `what-jenkins-does` target, combine the code coverage
data from all unit tests (currently just coreboot and libpayload).

BUG=b:203800199
TEST=`make what-jenkins-does && ls -l coreboot-builds/coverage.info`

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Id99615ca8279f80a402d5371221b8fd36fb91d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-12-08 20:29:55 +00:00
Julius Werner 6ddacd6f5b cbfstool: Fix offset calculation for aligned files
The placement calculation logic in cbfs_add_component() has become quite
a mess, and this patch can only fix that to a limited degree. The
interaction between all the different pathways of how the `offset`
variable can be set and at what point exactly the final placement offset
is decided can get quite convoluted. In particular, one existing problem
is that the offset for a file added with the --align flag is decided
before the convert() function is called, which may change the form (and
thereby the size) of the file again after its location was found --
resulting in a location that ends up being too small, or being unable to
find a location for a file that should fit. This used to be okay under
the assumption that forced alignment should really only be necessary for
use cases like XIP where the file is directly "used" straight from its
location on flash in some way, and those cases can never be compressed
-- however, recent AMD platforms have started using the --align flag to
meet the requirements of their SPI DMA controller and broken this
assumption.

This patch fixes that particular problem and hopefully eliminates a bit
of the convolution by moving the offset decision point in the --align
case after the convert() step. This is safe when the steps in-between
(add_topswap_bootblock() and convert() itself) do not rely on the
location having already been decided by --align before that point. For
the topswap case this is easy, because in practice we always call it
with --base-address (and as far as I can tell that's the only way it was
ever meant to work?) -- so codify that assumption in the function. For
convert() this mostly means that the implementations that do touch the
offset variable (mkstage and FSP) need to ensure they take care of the
alignment themselves. The FSP case is particularly complex so I tried to
rewrite the code in a slightly more straight-forward way and clearly
document the supported cases, which should hopefully make it easier to
see that the offset variable is handled correctly in all of them. For
mkstage the best solution seems to be to only have it touch the offset
variable in the XIP case (where we know compression must be disabled, so
we can rely on it not changing the file size later), and have the extra
space for the stage header directly taken care of by do_cbfs_locate() so
that can happen after convert().

NOTE: This is changing the behavior of `cbfstool add -t fsp` when
neither --base-address nor --xip are passed (e.g.  FSP-S). Previously,
cbfstool would implicitly force an alignment of 4K. As far as I can tell
from the comments, this is unnecessary because this binary is loaded
into RAM and CBFS placement does not matter, so I assume this is an
oversight caused by accidentally reusing code that was only meant for
the XIP case.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia49a585988f7a74944a6630b77b3ebd79b3a9897
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-07 16:59:33 +00:00
Felix Singer ad31061e66 util/liveiso: Update to NixOS 21.11
Update configs so that they work with NixOS 21.11. Drop `iasl` package
since it was replaced with `acpica-tools`.

Change-Id: Icb9a382b83b3b3e55126bb0bb508659d11497a05
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-12-06 22:37:08 +00:00
Patrick Georgi 987e3dc80b util/cbfstool: Ensure that htole32 et al are visible when building
endian.h wasn't included (although it probably came in as an indirect
include) but in some header sets _XOPEN_SOURCE overrides _DEFAULT_SOURCE
whereas the latter is a super set of the former:

We should get the same things as with _XOPEN_SOURCE (such as memccpy for
which it has been defined) but also extra features like htole32.

Change-Id: Iaee7495b2ae64fdc719ae0879ea95fe7df286212
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-06 19:40:53 +00:00
Jakub Czapiga ea619425ee commonlib: Move commonlib/cbmem_id.h to commonlib/bsd/
Libpayload requires cbmem_id.h file to support extracting values from
CBMEM IMD entries of coreboot tables. Libpayload use BSD-3-Clause
license, and all of its files used to compile a static library have to
use it too.

Change-Id: I97c080e34ebdbcdf14fe3a3c9515b1dea8ede179
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-11-30 17:23:37 +00:00
Angel Pons 1186265898 util/cbfstool/.gitignore: Add CSE tool executables
Commit 796aeeba96 (util/cse_fpt: Add a new tool for managing Intel CSE
FPT binaries) and commit d7fb6a90e1 (util/cse_serger: Add a new tool
for stitching CSE components) add two utilities, and building cbfstool
also generates executables for them. When building cbfstool standalone,
these executables are placed in `util/cbfstool/`, and Git should never
track them.

Specify these executables' file names in .gitignore in order to prevent
unintentional inclusion of these files in commits, which is very likely
to happen when using `git add` on directories.

Change-Id: I285a4d7aeee642822eaae2eb69e5d52efb4bc8c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59670
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-29 18:44:34 +00:00
Patrick Georgi 8422740933 util/ifdtool/Makefile: Derive from Makefile.inc
Instead of maintaining two complete Makefiles, reuse the coreboot
build system rules in the stand-alone Makefile.

Change-Id: I5d894a1f079799478bce0bd200ac735097f3806b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-26 11:26:19 +00:00
Patrick Georgi 19072dcd6f util/testing: Add ifdtool to tools to be tested
Ensure that the separate Makefile doesn't break.

Change-Id: I0fbe37dc01e46022c5e6de5629eb99f6b86b0b14
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-26 10:20:37 +00:00
Angel Pons 1a55dbf7e9 util/ifdtool/Makefile: Fix building as standalone tool
Commit f1e401c6cb (util/cbfstool/flashmap/fmap.c: fix fmaptool
endianness bugs on BE) makes use of endianness conversion macros
in cbfstool's FMAP code, which is also used by ifdtool. At least
on Linux, the <endian.h> header provides these helpers, but only
when `__USE_MISC` is defined, which is defined in the <ctypes.h>
header when `_DEFAULT_SOURCE` is defined. This was accounted for
in `Makefile.inc`, but not in `Makefile`. As a result, trying to
build ifdtool as a standalone tool (i.e. not as part of building
a coreboot image) results in build errors because the endianness
conversion macros are not defined.

Define `_DEFAULT_SOURCE` in `Makefile` to fix the build errors.

Change-Id: I8c2bbc07ddd87d885e2d6f5c7f2bd501e5c4e3b0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59663
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-26 10:20:24 +00:00
Patrick Georgi 673716dedd util/testing: Give meaningful error if intel-sec-tools aren't around
Without manual handling, when 3rdparty/intel-sec-tools isn't around,
`make what-jenkins-does` reports only

    go: go.mod file not found in current directory or any parent directory; see 'go help modules'

which isn't meaningful or actionable. Instead check that the go.mod file
exists and bail out with a better error message before trying to run
`go mod vendor`.

Change-Id: I035747746ca5fd54841bd67352044dde12a28185
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-24 20:16:48 +00:00
Marek Kasiewicz f1e401c6cb util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE
This patch makes all accesses to the FMAP fields explicitly little endian.
It fixes issue where build on BE host produced different binary image than
on LE.

Signed-off-by: Marek Kasiewicz <marek.kasiewicz@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: Ia88c0625cefa1e594ac1849271a71c3aacc8ce78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-22 15:01:30 +00:00
Hsuan Ting Chen a5cbe27148 eventlog: Add a log type for Chrome OS diagnostics
Add events for Chrome OS diagnostics in eventlog tool:
* ELOG_TYPE_CROS_DIAGNOSTICS(0xb6): diagnostics-related events
* ELOG_CROS_LAUNCH_DIAGNOSTICS(0x01): sub-type for diagnostics boot

These events are not added anywhere currently. They will be added in
another separate commit.

Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I1b67fdb46f64db33f581cfb5635103c9f5bbb302
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-22 14:59:37 +00:00
Angel Pons ada539ee50 util/inteltool/gpio.c: Correct register name
Document 319973-003 (ICH10 datasheet) and document 324645-006 (6-series
PCH datasheet) indicate that the name of this register is `GP_LVL3`,
not `GPIO_LVL3`. Correct the name.

Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-19 15:10:20 +00:00
Patrick Georgi 423e9e0fc0 Documentation/lint: Use Super I/O instead of SuperIO
Change-Id: Idb16092b687ebffb319bc1908f08f350d612d36a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-19 14:47:20 +00:00
Angel Pons 65adc70165 util/inteltool: Add ICH10D PCI ID
Add the PCI device ID for the ICH10D southbridge. While we're at it,
also fix up whitespace in inteltool.h of an adjacent definition.

Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-19 13:54:48 +00:00
Sean Rhodes c9bc7a7591 util/lint: Fix linters to work with coreboot-configurator
* Exclude .gif files from newline checking
* Exclude coreboot-configurator from checkpatch checking

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1b07b7b05340409e5c1695cc7bbdea68f8190097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-11-19 13:34:55 +00:00
Zheng Bao 570645dc2a amdfwtool: Call the set_efs_table for Stoneyridge
Related to https://review.coreboot.org/c/coreboot/+/58555
commit-id: 35b7e0a2d82ac
In 58555, we added the SOC ID for Stoneyridge in amdfwtool
command line. But it raised building error because it then called
"set_efs_table" without setting SPI mode. So we skipped calling that.

But in set_efs_table, it has case for Stoneyridge. The boards also
need to have this setting. So we remove the skipping and give the
proper SPI mode in mainboard Kconfig.

Change-Id: I24499ff6daf7878b12b6044496f53379116c598f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:29:48 +00:00
Zheng Bao 6e2c5a3d18 amdfwtool: Set flag comboable as bool type
Fix the CL:
https://review.coreboot.org/c/coreboot/+/58942
The type comboable was int but set as true.

Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:28:59 +00:00
Zheng Bao b749d3f0d2 amdfwtool: Add a union for combo and psp directory
For combo layout, this is for combo header.
For non-combo layout, this is for PSP directory.

Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:28:47 +00:00
Reka Norman 86a9cdd589 util/mb/google: Change comments in memory Makefile.inc templates
Begin comments with # instead of ## to match the Makefile.inc generated
by spd_tools.

BUG=None
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: If2d716a7338fd5af8216b2bcd894fc88a9df137e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 00:35:36 +00:00
Zheng Bao 6bc300d8d5 amdfwtool: Set soc name for Stoneyridge
For the stoneyridge, soc_name is not set in Makefile, so set_efs_table
is not called. Keep it unchanged.

Change-Id: I0e82188ce64733420a578446e22a077ef789be92
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 10:06:39 +00:00
Martin Roth 93e6bbad3c util/docker/coreboot-sdk: Add bsdextrautils & lcov
Add lcov for coverage calculations.
Add bsdextrautils for hexdump.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I421c59ce2d0d08bf5142dbc378eeea45b8b1d5b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-11-14 04:21:10 +00:00
Zheng Bao 5164e4b03f amdfwtool: Pack out-of-bounds check into a function and move
Need to check the FWs number limit several times. So pack the
duplicated steps into a function. And do it before access the new
entry.

Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-11 14:40:45 +00:00
Reka Norman e6a1ebe55b util/spd_tools: Document adding support for a new memory technology
Add documentation describing how to add support for a new memory
technology to spd_tools:
- Add a section to the README.
- Document the memTech interface in spd_gen.go.

BUG=b:191776301
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59005
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-09 23:45:26 +00:00
Martin Roth a7648f2b27 util/lint/kconfig_lint: Fix off by one error that missed last line
This error prevented the last line of the Kconfig tree from being
printed or added to the output file.  This is a significant problem if
you try to use the generated file as the kconfig source, because it
changes CONFIG_HAVE_RAMSTAGE from defaulting to yes to defaulting to
NO.  This causes the build to stop working.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3ec11f1ac59533a078fd3bd4d0dbee9df825a97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-11-09 14:14:46 +00:00
Zheng Bao ba3af5e2ff amdfwtool: Change the flag value to type bool
Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:56:19 +00:00
Zheng Bao edd1e360f4 amdfwtool: Fix the parameter point to NULL instead of integer
Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:55:35 +00:00
Zheng Bao 33351336f8 amdfwtool: Change the definition of level to a bitwise form
Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:55:29 +00:00
Paul Fagerburg 5d4f0838d6 util/testing: add code coverage to jenkins
Add COV=1 and the `coverage-report` target to unit test build rules
in `what-jenkins-does` so that we get code coverage data from the
coreboot and libpayload unit tests.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I96669c47d1a48e9ab678a4b9cb1d0c8032d727f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-04 20:34:53 +00:00
Reka Norman 2c439adb51 util/spd_tools: Add LP5 support for ADL
Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is
supported.

The SPDs are generated based on a combination of:
- The LPDDR5 spec JESD209-5B.
- The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has
  not released an SPD spec for LPDDR5).
- Intel recommendations in advisory #616599.

BUG=b:201234943, b:198704251
TEST=Generate the SPD and manifests for a test part, and check that the
SPD matches Intel's expectation. More details in CB:58680.

Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-04 10:46:07 +00:00
Angel Pons 437da71d0a SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries
Introduce the `smbios_dev_info` devicetree keyword to specify the
instance ID and RefDes (Reference Designation) of onboard devices.

Example syntax:

 device pci 1c.0 on	# PCIe Port #1
 	device pci 00.0 on
 		smbios_dev_info 6
 	end
 end
 device pci 1c.1 on	# PCIe Port #2
 	device pci 00.0 on
 		smbios_dev_info 42 "PCIe-PCI Time Machine"
 	end
 end

The `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` Kconfig option enables using
this syntax to control the generated Type 41 entries. When this option
is enabled, Type 41 entries are only autogenerated for devices with a
defined instance ID. This avoids having to keep track of which instance
IDs have been used for every device class.

Using `smbios_dev_info` when `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` is not
enabled will result in a build-time error, as the syntax is meaningless
in this case. This is done with preprocessor guards around the Type 41
members in `struct device` and the code which uses the guarded members.
Although the preprocessor usage isn't particularly elegant, adjusting
the devicetree syntax and/or grammar depending on a Kconfig option is
probably even worse.

Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-11-04 10:25:09 +00:00
Patrick Georgi 6dad77d64a util/crossgcc/Makefile: Clean up .PHONY definitions
Order functionally:
 * first "all" and build-$tools
 * followed by clean
 * followed by the architecture targets

The order was chosen this way because the architecture targets are
the mostly likely to continue to grow.

While at it, also fix the build_nasm mention (it was build-nasm)
and add build_make.

Change-Id: Id58338a512d44111b41503d4c14c08be50d51cde
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58796
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02 17:36:23 +00:00
Patrick Georgi dba7736104 util/kconfig: Uprev to Linux 5.15's kconfig
Upstream's changes only affect a script that we don't use.
Still, this keeps us in sync with the official version.

Change-Id: I39cbbfb8dc816b4f36f92e6bd53f40c733691242
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-02 08:10:47 +00:00
Patrick Georgi 9f7c78b5ec util/kconfig: Uprev to Linux 5.14's kconfig
Upstream's changes have been minimal, to the perl script that we
don't use and a constness change, so I expect no harm. Still, this
keeps us in sync with the official version.

Change-Id: I5e5a2400bc3323938da4b946930e2ec119819672
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-02 08:10:41 +00:00
Patrick Georgi c710ee7319 util/kconfig: Rewrite patch in quilt's normal form
This is what quilt writes on `quilt refresh` and what it can apply and
unapply cleanly.

Change-Id: I8c8586da384b65fd5c21c1c1a093642534f83283
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-02 06:40:41 +00:00
Patrick Georgi f32eed1695 buildgcc: Remove GDB from crossgcc
It was added for a specific defunct project by a specific defunct
company.

Change-Id: Ib56ae0fdc1a50d24ff44c7879c43f8e94a5bfa95
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-01 16:26:50 +00:00
Zheng Bao eb0404e8bf amdfwtool: Add PSP ID for combo and ISH header for A/B recovery
Nobody calls the function until combo or A/B is added, so suppress the
warning for now.

Test=Majolica (Cezanne)

Change-Id: I3082b850fb3fd2d7ae83a1c4dfd89eb7e1bd0f97
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-29 14:26:22 +00:00
Ricardo Quesada e1f392ea34 elogtool: add pytest for elogtool
This CL adds a python test for elogtool.
It tests the basic functionality of elogtool: list, clear and add.
A future CL will include more complex tests.

BUG=b:172210863
TEST=pytest elogtool_test.py

Change-Id: If1241ad070d1c690c84f5ca61c0487ba27c2a287
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-10-25 08:08:41 +00:00
Timofey Komarov 6c8008283c util/inteltool: Add PCH IDs for 200 series chipsets
Signed-off-by: Timofey Komarov <happycorsair@yandex.ru>
Change-Id: Iadad5e79aef9da3fac627adc135525a5001a72b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-24 16:04:49 +00:00
Felix Singer ff6416f737 util/release/build-release: Create cross-toolchain version file
Add cross-toolchain version file to the release tarball, which can be
used for pre-setting the variables used in buildgcc.

Change-Id: Iad1e0adaa95b71f161caf978276bfb0a63eac8f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21 14:15:57 +00:00
Felix Singer 02750d0400 util/crossgcc/buildgcc: Use pre-set CROSSGCC_VERSION if possible
For reproducibility, a version string is appended to the version of the
tools used in the cross-toolchain. Currently, git is used to determine
that version string at runtime of this script. There are cases, where
it's not possible to determine that version string, e.g. when a release
tarball is used, and if so, the version string is just `v_`.

Thus, allow pre-setting the variable `CROSSGCC_VERSION`.

Change-Id: I888ccd877c93436b5e033528c43bd8667b8d2f10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21 14:15:29 +00:00
Felix Singer 60c56be85f util/crossgcc/buildgcc: Allow printing only the version
In preperation to CB:58396, add the parameter `-W|--print-version`,
which allows printing the content of `CROSSGCC_VERSION`. In
combination with CB:58396, this can be used to pre-set the variable
in case of the git history is not accessible.

Change-Id: I9a205ca0ecb0ece47eb5d8fa73706478354512ff
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-20 20:12:43 +00:00
Felix Singer 62fcffb247 util/crossgcc/buildgcc: Remove CROSSGCC_COMMIT
For reproducibility, the buildgcc script is copied to the destination
folder of the toolchain. `CROSSGCC_COMMIT` is used as a file name
extension for the script and was introduced when `CROSSGCC_VERSION`
didn't contain the commit yet. Since this is not the case anymore,
remove it.

Change-Id: Id0a0b657eb828b2728ff787228eaa38be83d9517
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58450
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20 20:12:19 +00:00
Raul E Rangel 41ba01bb95 util/cbfstool/rmodule: Omit undefined extern symbols from reloc table
When using `DECLARE_OPTIONAL_REGION`, it is assumed that
REGION_SIZE(name) == 0 if the region was not defined in the memlayout.
When using non-rmodule stages (i.e., bootblock, romstage, etc), this
assumption holds true, but breaks down in rmodule (i.e., ramstage)
stages.

The rmodule tool is not currently omitting undefined externals from the
relocation table. e.g.,

    extern u8 _##name##_size[];

This means that when the rmodule loader runs, it will rewrite the symbol
from 0 (which is the default the linker assumed) to 0 + offset. This is
wrong since the symbol doesn't actually exist. Instead we need to omit
the relocation so it continues to keep the default value of 0.

BUG=b:179699789
TEST=Print out REGION_SIZE(cbfs_cache) in ramstage and verify it is set
to 0.
I also see the following printed by the rmodtool now:

DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone_size
DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone
DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone
DEBUG: Omitting relocation for absolute symbol: _stack_size
DEBUG: Omitting relocation for absolute symbol: _program_size
DEBUG: Omitting relocation for absolute symbol: _cbmem_init_hooks_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache
DEBUG: Omitting relocation for undefined extern: _cbfs_cache
DEBUG: Omitting relocation for undefined extern: _cbfs_cache_size

As you can see the _watchdog_tombstone will also be fixed by this CL.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib57e263fa9014da4f6854637000c1c8ad8eb351a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20 15:56:28 +00:00
Michael Niewöhner 4396358fd3 kconfig_lint: use just one variable for keeping track of choices
Instead of using two variables, one for the boolean value and one for
the path, use just one with the path. Since an empty string evalutes to
false, this simplification does not change behaviour.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I2f1171789af6815094446f107f3c634332a3427e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20 15:52:16 +00:00
Michael Niewöhner 70fb5cb514 kconfig_lint: put $inside_choice together right in the first place
Instead of substituting the delimiter later, put $inside_choice together
right in the first place.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia713510a683101c48c86a1c3722ebb1607a29288
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20 15:51:36 +00:00
Furquan Shaikh bf848ad4b2 util/cse_serger: Add command `create-cse-region`
This change adds a new command `create-cse-region` to cse_serger tool
which takes as inputs offset:size and file for different CSE
partitions and generates the entire CSE region image.

BUG=b:189177186

Change-Id: Ib087f5516e5beb6390831ef4e34b0b067d3fbc8b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:32:24 +00:00
Furquan Shaikh 8b4ca15d7e util/cse_serger: Replace cse_layout_regions with array of regions
This change replaces `struct cse_layout_regions` with an array of
`struct region` and introduces enums for DP and BP[1-4]. This makes it
easier to loop over the different regions in following changes.

BUG=b:189177186

Change-Id: If3cced4506d26dc534047cb9c385aaa9418d8522
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:10:12 +00:00
Furquan Shaikh 555f040772 util/cse*: Add cse_helpers.{c,h}
This change moves `read_member` and `write_member` helper functions
out of cse_fpt.c and cse_serger.c into cse_helpers.c to avoid
duplication.

BUG=b:189177186,b:189167923

Change-Id: I7b646b29c9058d892bb0fc9824ef1b4340d2510c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:45 +00:00
Furquan Shaikh d7fb6a90e1 util/cse_serger: Add a new tool for stitching CSE components
This change adds a new tool `cse_serger` which can be used to print,
dump and stitch together different components for the CSE region.

BUG=b:189177186

Change-Id: I90dd809b47fd16afdc80e66431312721082496aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:24 +00:00
Furquan Shaikh 796aeeba96 util/cse_fpt: Add a new tool for managing Intel CSE FPT binaries
This change adds a new tool `cse_fpt` which can be used to print and
dump CSE partitions in Flash Partition Table (FPT) format.

BUG=b:189167923

Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:03 +00:00
Felix Held ad68b07d45 util/amdfwtool: rename PSP related embedded_firmware struct elements
The element at offset 0x14 in the embedded_firmware struct is the
pointer to the combo PSP directory header, so rename it from comboable
to combo_psp_directory to clarify that this is not a flag, but a pointer
to a data structure. Also rename psp_entry to psp_directory since it
points to the PSP directory table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19 12:35:08 +00:00
Furquan Shaikh 2bfef8d856 cbfstool: Add helper function `buffer_from_file_aligned_size`
This change adds a helper function `buffer_from_file_aligned_size`
that loads a file into memory buffer by creating a memory buffer of
size rounded up to the provided `size_granularity` parameter.

BUG=b:189177186,b:189167923

Change-Id: Iad3430d476abcdad850505ac50e36cd5d5deecb4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-18 21:15:41 +00:00
Nico Huber 967730f565 kconfig_lint: Drop overly restrictive rule about choice configs
This rule was creating trouble:
* A symbol may only be declared inside or outside a choice.

The linter treats every occurence of a `config` entry as a symbol
declaration, even when it's just setting a default or adding selects.
This is not easy to fix as the symbol objects are not created first
and then added to the $symbols array when we know what kind of decla-
ration we have, but are created incrementally inside this global
list.

Change-Id: I48a17f6403470251be6b6d44bb82a8bdcbefe9f6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56410
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18 19:33:57 +00:00
Jakub Czapiga 12ae850dfc libpayload: Add unit-tests framework and first test case
This commit adds a unit-tests framework ported from coreboot, and test
for drivers/speaker. Usage of the unit-tests framework is same as for
the coreboot one.

Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-18 12:33:49 +00:00
Angel Pons 05ae8f2ff3 mainboard: Drop invalid `VGA_BIOS_FILE` defaults
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig
does not exist in the coreboot tree (including submodules), drop it.
These files should be stored in the `site-local` subdirectory and the
paths specified for each board in `site-local/Kconfig`. For example:

config VGA_BIOS_FILE
	default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200

Note that this is just an example. There are better ways to structure
one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option
would be one of them, though variants may still need special handling.

Also, update autoport to not generate `VGA_BIOS_FILE` defaults.

Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-10-15 09:08:35 +00:00
Nicholas Chin 87e0b5b1d7 util/autoport/bd82x6x.go: Fix includes
Fix include of nvs.h to reflect commit 661ad4666c (ACPI: Select
ACPI_SOC_NVS only where suitable); and re-add <device/pci_ops.h>,
removed in commit 0aad0531dc (util/autoport/bd82x6x.go: Drop unused
includes), as the generated early_init.c uses pci_write_config16().

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12 17:37:52 +00:00
Rex-BC Chen 5020fe3449 util/cbfstool: Add support for ARM64 UefiPayload
UEFI payload is supported on some ARM64 platforms, for example MT8195.
As a result, add MACHINE_TYPE_ARM64 to support ARM SystemReady.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4c0c6e263bd2f518a62ff9db44d72dd31086756a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-10-04 02:31:01 +00:00
Felix Singer ae90f2ebc5 util/liveiso: Install nvme-cli tool
nvme-cli is used to manage NVMe devices and it supports many vendors.
Also, it seems it's commonly used to do firmware updates.

Change-Id: I26a78867b01d3af0441827c5b25343a46d7ddea1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-01 15:08:07 +00:00
Reka Norman 91feb06ece Revert "Revert "util/abuild: Regenerate xcompile on every abuild run""
This reverts commit d94f8bbe9d.

This is a reland of https://review.coreboot.org/57651. The original
change broke parallel abuild runs since the xcompile file was deleted by
every recursive call to abuild. This issue was fixed by rebasing on top
of a change which only regenerates the xcompile on non-recursive calls.

BUG=None
TEST=Parallel abuild run succeeds.

Change-Id: I086ba7b2ae1b8b14459838bd18ce962a84aa306d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-26 16:08:05 +00:00
Ricardo Quesada 1427f12adf elogtool: Fix off-by-one error in month in timestamp
elogtool was setting the timestamp with the wrong value in the month.
This CL fixes that by incrementing the month by one. This is needed
since gmtime() returns the month value starting at 0.

TEST=pytest elogtool_test.py (see next CL in relation chain)

Change-Id: I00f89ed99b049caafba2e47feae3c068245f9021
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-24 18:08:43 +00:00
Nico Huber e28eeb713d util/abuild: Run `make .xcompile` only once
If abuild called itself recursively, the file already exists and we can
spare us one evaluation of all the makefiles per recursive abuild run.

Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-09-24 14:32:07 +00:00
Michael Niewöhner 90fcffb416 kconfig_lint: restrict definition of defaults for choice elements
Defining defaults for symbols used inside choices is not allowed. Add a
check for this, so we can drop the existent, overly restrictive checks
in the follow-up change.

Change-Id: I45bce2633dbd168fceb81ceae9b68621b28526e8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-23 22:25:53 +00:00
Patrick Georgi b0d87f753c util/crossgcc: Update gcc to 11.2
Various fixes to gnat and the improved nds32 backend have been merged
into gcc by now, so we don't need to carry those patches anymore.

Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23 08:37:39 +00:00
Reka Norman e4cf38ed36 util/spd_tools: Remove old lp4x and ddr4 versions of spd_tools
The migration to the new unified version of spd_tools is complete, so
the old lp4x and ddr4 versions can be removed.

BUG=b:191776301
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I6b1fc297739efc8dc7d7eec64956bf3343984604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23 07:51:38 +00:00
Reka Norman 8f690dd762 util/spd_tools: Sort platforms_manifest entries by set number
Ensure that the order of entries in each platform manifest is consistent
every time spd_gen is run.

BUG=b:191776301
TEST=Run spd_gen for lp4x and ddr4, check that the manifests are
unchanged.

Change-Id: I7bfea65c8fc781df80a8725c0cf20c7547c857e8
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23 07:51:22 +00:00
Reka Norman 0c1f737fea util/mb/google: Update templates to refer to the new spd_tools
Update the new variant templates to refer to the new unified version
of spd_tools:
- Update the comments in mem_parts_used.txt
- Change the placeholder SPD in Makefile.inc to 'placeholder'

BUG=b:191776301
TEST=None

Change-Id: I03265de0d1182da81dd25a2fe6f940a0b82e5fa4
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23 06:52:27 +00:00
Zheng Bao b1fb8cebf8 amdfwtool: Add an optional column of level
The value of level defined in table is the default one. We now give an
extra option in config file to change this value so some FWs can be
dropped in a more optimized way.
For the non A/B recovery mode, The value could be L1, L2, Lb or Lx,
which are level 1, leve 2, level both and using default value. If it
is empty or Lx, left the level in table unchanged.

Give a redundant field [12bxBX] in regular exprssion for A/B recovery
which will be done later.

Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23 06:26:47 +00:00
Reka Norman 293a3e03dc util/spd_tools: Remove PLK platform
Currently spd_tools treats PCO and PLK as separate platforms. This is
unnecessary since they have the same SPD requirements. Remove PLK, and
use PCO as the platform for all zork variants.

BUG=b:191776301
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I7eeeab53fb3e0d92c3675fb80b4747297d4257ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23 06:23:46 +00:00
Reka Norman 7adc2e23b5 util/spd_tools: Add README for unified spd_tools
Combine the existing lp4x and ddr4 READMEs into a single file, and
update it to reflect the new unified version of the tools.

BUG=b:191776301
TEST=None

Change-Id: I866932a1d0b5b6b47b0daff893b37de7a302b4e6
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23 06:21:31 +00:00
Reka Norman f4be6f6d85 util/spd_tools: Add 'Generated by' string to part_id_gen output files
Add a 'Generated by' string to the generated Makefile.inc and
dram_id.generated.txt, showing the command used to generate the files.

BUG=b:191776301
TEST=Run part_id_gen, check that the generated files contain the string

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ic9a7826212a732288f36f111b7bc20365a1f702d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21 17:21:49 +00:00
Reka Norman 4e4e2d7ab1 util/spd_tools: Automatically determine the SPD dir in part_id_gen
Currently, one of the arguments to part_id_gen is the directory
containing the SPD files, e.g. spd/lp4x/set-0. This requires the user of
the tool to understand the spd/ directory structure, and manually look
up the set number corresponding to their platform.

Change part_id_gen to take the platform and memory technology as
arguments instead of the SPD directory, and automatically determine the
SPD directory by reading the platforms manifest file generated by
spd_gen.go.

BUG=b:191776301
TEST=Run part_id_gen and check that the generated Makefile.inc and
dram_id.generated.txt are the same as before. Example:
util/spd_tools/bin/part_id_gen \
  ADL \
  lp4x \
  src/mainboard/google/brya/variants/kano/memory \
  src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt

Change-Id: I7cd7243d76b5769e8a15daa56b8438274bdd8e96
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21 17:21:39 +00:00
Reka Norman 780b04e639 util/spd_tools: Add max ID check for auto-generated IDs to part_id_gen
Currently, the maximum part ID of 15 is enforced only for manually
assigned IDs. Also enforce it for automatically assigned IDs.

BUG=b:191776301
TEST=part_id_gen fails when the number of part IDs which would be
assigned is greater than MaxMemoryId.

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I802190a13b68439ccbcdb28300ccc5fd1b38a9c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21 17:21:23 +00:00
Frank Wu f894fcc031 util: Add DDR4 generic SPD for 4JQA-0622AD
Add SPD support for DDR4 memory part

BUG=b:199469240
TEST=none

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ie67cf6b90304f0bcf80838866c7461c0cea86dc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21 15:19:10 +00:00
Reka Norman d94f8bbe9d Revert "util/abuild: Regenerate xcompile on every abuild run"
This reverts commit a2c009bd94.

Reason for revert: Breaks parallel abuilds.

Change-Id: I368b189050d519769f4852fea8e255e9b31b27b6
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21 10:56:37 +00:00
Ricardo Quesada e48043b095 elogtool: compile in 32-bit platforms
This CL fixes a compilation error that happens in 32-bit platforms.
This error happens because printf() was using %ld instead of %zu to
print size_t variables.

This CL fixes it.

BUG=b:200608182
TEST=emerge-kevin (ARM 32-bit)
TEST=emerge-eve (Intel 64-bit)

Change-Id: I340e108361c052601f2b126db45caf2e35ee7ace
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-09-21 01:02:56 +00:00
Reka Norman b05edb1fea util/spd_tools: Implement a unified version of the part_id_gen tool
Currently there are two versions of gen_part_id.go, one for LP4x and one
DDR4. This change implements a unified version of this tool.

The new part_id_gen.go is almost identical to the existing
ddr4/gen_part_id.go. The new version was based on the ddr4 version and
not the lp4x version, since the ddr4 version contains extra logic to
support fixed IDs in the mem_parts_used files.

The only non-trivial change from ddr4/gen_part_id.go is to include the
full paths of SPD files in the generated Makefile.inc. E.g. instead of

  SPD_SOURCES += lp4x-spd-1.hex

the full path relative to the coreboot root directory is included:

  SPD_SOURCES += spd/lp4x/set-0/spd-1.hex

BUG=b:191776301
TEST=For each variant of brya/volteer/dedede/guybrush/zork, run
part_id_gen and verify that the generated Makefile.inc and
dram_id.generated.txt are identical to those currently in the src tree,
except for the modified SPD file paths in Makefile.inc.
Example:
util/spd_tools/bin/part_id_gen \
  spd/lp4x/set-0 \
  src/mainboard/google/brya/variants/kano/memory \
  src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt

Change-Id: Ib33d09076f340f688519dae7956a2b27af090c0b
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20 23:51:07 +00:00
Reka Norman a2c009bd94 util/abuild: Regenerate xcompile on every abuild run
Currently, running abuild in a fresh checkout without having built the
toolchain results in the following confusing behaviour:
1. Run abuild. It fails due to the missing coreboot toolchain, and the
   error message suggests running `make crossgcc`.
2. Run `make crossgcc`. It succeeds.
3. Re-run abuild. It still fails due to a missing coreboot toolchain.

This happens because the first abuild run generates an xcompile file
which uses the system toolchain. The second abuild run doesn't
regenerate the xcompile, so it still fails due to the non-coreboot
toolchain.

To avoid this confusing behaviour, regenerate the xcompile file every
time abuild is run.

BUG=None
TEST=Perform the steps above in a clean checkout. The second abuild run
now succeeds.

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I78a7702c45cecbfe8460ec55df03741e5ced94b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-20 12:21:05 +00:00
Furquan Shaikh 0df32c85ad sconfig: Emit device structure pointers if alias names are provided
This change uses _dev_${ALIAS_NAME} as the name for `struct device` if
the device has an alias. In addition to that, it emits
_dev_${ALIAS_NAME}_ptr which points to the device structure. This
allows developers to directly reference a particular device in the tree
using alias name without having to walk the entire path. In later CLs,
mainboards are transitioned to use this newly emitted device structure
pointers.

Change-Id: I8306d9efba8e5ca5c0bda41baac9c90ad8b73ece
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20 12:17:13 +00:00
Patrick Georgi f28e368d58 util/crossgcc: Update binutils to 2.37
Change-Id: Ia68d4d9f836ad23fb8f6a7203a78b4ea40c7c43b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-19 18:51:52 +00:00
Reka Norman 0e79274d33 util/spd_tools: Implement a unified version of the spd_gen tool
Currently there are two versions of spd_tools: one for LP4x and one for
DDR4. This change is the first step in unifying these into a single
tool.

This change implements a unified version of the spd_gen tool, by
combining the functionality currently in lp4x/gen_spd.go and
ddr4/gen_spd.go. The unified version takes the memory technology as an
argument, and generates SPD files for all platforms supporting that
technology.

BUG=b:191776301
TEST=Compare the SPDs generated by the old and new versions of the tool
for all supported platforms. For reference, the test script used is
here: https://review.coreboot.org/c/coreboot/+/57511

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I7fc036996dbafbb54e075da0c3ac2ea0886a6db2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-17 14:49:22 +00:00
Zheng Bao 2079589999 amdfwtool: Detect the flag multilevel to decide the actual value
To save the space for FW, some of the FWs are going to be defined as
LVL2 entries. To be compatible to "flattened" layout, we still drop
the LVL2 entry to level1 if there is only one level.

Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-17 14:48:30 +00:00
Felix Singer 7a474a5bb7 util/liveiso: Make neovim the default editor
Make neovim the default editor and create an alias for vim.

The NixOS module for neovim is currently broken. Thus, add a note to
`description.md` to switch to that later.

Change-Id: I9345a6e32f3035565e55e50579c97121b4987d83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57393
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16 22:55:50 +00:00
Felix Singer 821311e23e util/nixshell: Add Nix shell for toolchain compilation
Add a Nix shell file which provides an environment for compilation of
the coreboot toolchain. The Nix shell can be used by running the
following command:

  $ nix-shell --pure util/nixshell/toolchain.nix

The `--pure` parameter is optional, but it makes sure that the
environment is as minimal as possible and does not contain any unrelated
or unneeded software or configuration.

Once compiled, the coreboot toolchain can be used without loading the
shell environment.

If `--pure` is used, SSL connections won't work since the
`SSL_CERT_FILE` environment variable is not configured, which makes the
build tool unable to download the source files. Thus, let it point to
the system certificate store.

Change-Id: I341ee28c5451d2c6cb4ff22de67161d99f4ca77a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-16 22:55:02 +00:00
Ricardo Quesada 683b294d3f elogtool: add "add" command
Adds "add" command to elogtool. This command allows adding elog events
manually. It supports event type and, optionally, event data.

If the free buffer space is < 1/4 of the total space, it shrinks the
buffer, making sure that ~1/4 of the free space is available.

BUG=b:172210863
TEST=./elogtool add 0x17 0101
     ./elogtool add 0x18
     Repeated the same tests on buffers that needed to be shrunk.

Change-Id: Ia6fdf4f951565f842d1bff52173811b52f617f66
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16 17:28:16 +00:00
Ricardo Quesada a2bf94d4c1 elogtool: add next_available_event_offset function
This function is "extracted" from cmd_clear().
This new function will be called from cmd_add(), and new command that
will be added in a future CL (see CL chain).

Additional minor fixes:
 - calls usage() if no valid commands are passed.
 - Slightly improves usage() output. Needed for cmd_clear()

BUG=b:172210863
TEST=elogtool clear

Change-Id: I0d8ecc893675758d7f90845282a588d367b55567
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16 13:52:37 +00:00
Tim Wawrzynczak 5cd979efb5 util/sconfig: Update static.c to include boot/coreboot_tables.h
This allows the devicetree to directly access names defined in the
coreboot tables API.

BUG=b:194967458
BRANCH=dedede

Change-Id: Ieb2d00095f54b2363a21f9c5ef8205110a36f746
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16 00:12:28 +00:00
Zheng Bao 535ec536ea amdfwtool: Add new SOC mendocino
Change-Id: I54492600dd954a5585ce3b1d842d264a4a50907a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-15 16:50:44 +00:00
Felix Singer 5e44322532 util/liveiso: Install UEFITool packages
Install both versions of UEFITool, the one with the old engine and the
new one.

It's not possible to use both packages in the same environment, since
there is a collision between the names of the binary files. To make sure
a specific package is used, a new environment needs to be spawned with
the following command:

  $ nix-shell -p <package_name>

The UEFITool binaries can be executed from the shell then.

Change-Id: Ia5d679c6e7cd01c2ab819bd6c085596a926c494d
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-15 11:42:59 +00:00
Patrick Georgi 615cdfcdb9 util/kconfig: Add pre-built parser
It avoids the dependency on bison/flex, minimally speeds up the build
and also works around weird race conditions in some versions of bison
that need more investigation.

The issue this avoids manifests as a build error when creating
parser.tab.c:

    input in flex scanner failed
    make: *** [util/kconfig/Makefile.inc:66: build/util/kconfig/parser.tab.c] Error 2

Since the error happens within bison the alternative would be to make
bison part of our crossgcc environment to ensure that no broken OS
build is used.

BUG=b:197515860
TEST=things build with bison not installed

Change-Id: Ib35dfb7beafc0a09dc333e962b1e3f33df46a854
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-13 15:35:03 +00:00
Patrick Georgi 116b144930 util/kconfig: Simplify dependencies for parser.tab.*
With parser.tab.h depending on parser.tab.c it's possible for make
to initiate the creation of parser.tab.c, then try to compile it,
even though parser.tab.h is still missing.

This isn't normally an issue yet because bison creates them both at
a time but with pre-compiled files this will become a problem.

Pattern rules support (until recently as a special case that no other
type of rule could implement) multiple targets that are actually
treated as "one command creates multiple output files" so use that
to state the relationship properly.

Change-Id: I4aa7eca9d3123808e0665a15a99c04fac7384940
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-13 14:49:15 +00:00
Angel Pons d56d2a86ed util/sconfig: Extract handling of SMBIOS data
Move the code that handles devices' SMBIOS data into a helper function.

Change-Id: I4f36d6c6f26e79558d360d319d09b0b8426def0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57369
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13 13:58:20 +00:00
Angel Pons 39e029768b util/sconfig: Always generate SMBIOS CPP guards
Manually maintaining a list of fields just to avoid printing some
unnecessary CPP guards isn't worth the maintenance burden. Instead,
always generate these guards, even if they guard nothing.

Change-Id: I6c84180d83ac39a895e02d196acb7074eb052d7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57459
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13 13:55:59 +00:00
Ricardo Quesada 49a96a9463 elogtool: add "clear" command
Adds "clear" command to cbfsutil/elogtool tool.
"clear" clears the RW_ELOG region by using either:
 * flashrom if no file is provided
 * or using file write if an input file is provided.

The region is filled with ELOG_TYPE_EOL. And a
ELOG_TYPE_LOG_CLEAR event is inserted.

Additionally, it does a minor cleanup to command "list", like:
 * use buffer_end()
 * add "list" to the cmds struct
 * and make elog_read() very similar to elog_write()

Usage:
$ elogtool clear

BUG=b:172210863
TEST=elogtool clear && elogtool list
     elogtool clear -f invalid.raw
     elogtool clear -f valid.raw

Change-Id: Ia28a6eb34c82103ab078a0841b022e2e5e430585
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2021-09-10 22:53:05 +00:00
Felix Singer 593941b600 util/liveiso/console.nix: Remove unneeded argument body
Change-Id: Iebd994a46e870e42431d0fc71dd14b1c2b01f9aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57536
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 20:09:08 +00:00
Felix Singer 46e109f274 util/liveiso: Disable strict checking of access to MMIO memory
Change-Id: Ie859490d3cb3b8c56437cbd6c3e46525c580d3f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57535
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 20:09:02 +00:00
Julius Werner 8202fc42d4 util/cbmem: Add -2/--2ndtolast option to print second-to-last boot log
On some platforms, runtime firmware crashes write logs to the CBMEM
console. For those, since a crash reboots the system, by the time we
have a chance to run `cbmem` again the boot where the crash happened
will be the one before the "last" (current) boot. So cbmem -1 doesn't
show the interesting part, and cbmem -c potentially shows a lot that is
cumbersome to dig through. This patch introduces a new option cbmem -2
to explicitly show only the boot cycle before the last one.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6725698f4c9ae07011cbacf0928544cebb4ad6f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-09-09 23:05:03 +00:00
Martin Roth a95cd265bd util/amdtools: Add script to update the SPI speed in the EFS header
The update_efs_spi_speed allows changing the SPI speed manually in a
binary that has already been built.  This will allow binaries not built
for the EM100 SPI ROM emulator to be updated so that they will work.
There is a corresponding change that will check to see if the EFS value
has been modified from the original speed and will prevent coreboot from
updating the SPI speed and mode.

BUG=b:177233017
TEST=Update SPI speed in existing binary.  See that SPI speed has
changed.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I905a9fd8bd93a28aab927dffecbbcf24934b9e03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56644
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08 19:41:31 +00:00
Nico Huber 859ecdf517 sconfig: Ensure at least one `device` node below each `chip`
Even though `device` entries are children of `chip` entries in the
devicetree source format, the chips in the translated C structures
are only hooked up to device nodes. Hence, any chip with all its
settings will be silently dropped by sconfig if there is no device
node below it.

Let's adapt the parser to ensure that there is at least one `device`
entry. The intermediate `chipchildren_dev` rule applies until the
first `device` entry is found, then everything continues as before
with the `chipchildren` rule.

Change-Id: I54830bc1fc7d00a0605f3fe4d36a83ef57ef3312
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51119
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08 19:03:20 +00:00
Iru Cai 112e9baddf autoport: search for the HDA device on PCH
Haswell has its Mini-HD device and is at card0, so we need to search
for the PCH HD Audio device instead of using card0.

Change-Id: I2bc420fdbe9731ae835f63add85db79f04201da4
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34357
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06 19:35:26 +00:00
Iru Cai ab5cac2c79 inteltool: Support dumping IOBP register values
This patch also adds LynxPoint and WildcatPoint-LP IOBP registers,
which is used to get the USB and SATA configuration values for
autoport.

Change-Id: I1f11640fdff59a5317f19057476f7e48c2956ab9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41473
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06 19:35:08 +00:00
Felix Held a6274992ff utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES
Like USE_AMD_BLOBS and USE_QC_BLOBS in the case of the AMD and Qualcomm
repos, FSP_USE_REPO controls if the Intel FSP repo will get checked out
and will be available during the Jenkins runs. ADD_FSP_BINARIES will get
selected in drivers/intel/fsp2_0/Kconfig when FSP_USE_REPO is selected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72faa6f9e5f2b06ab7cd43595ae0b49bf4d39630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05 17:52:38 +00:00
Felix Singer f9948a4d39 util/liveiso: Add NixOS configs for bootable live systems
Add NixOS configurations for bootable live systems containing a set of
tools which might be useful for firmware development in general and for
working on coreboot.

There are two configurations provided. One for console-only and a
graphical one, which is mostly the same as the console image but it
comes with Gnome Shell as window manager and some graphical tools in
addition.

An image can be built using `build-console.sh`, respectively
`build-graphical.sh`. The resulting iso image can be found in
`result/iso/`.

The console image results in ~700MB, while the graphical one results in
~2GB.

Change-Id: Iaf49d198e99781434bd89d2a8a125a4988b77e1c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-03 19:38:15 +00:00
Dun Tan 4a35940137 util/cbftool: Fix the bug in parsing Uefipayload with extended header
The patch is to fix "Not a usable UEFI firmware volume" issue when
creating CBFS/flash image. This issue is caused by adding FvNameGuid
in UefiPayloadEntry.fdf in EDKII. There is an ext header between header
of Fv and header of PayloadEntry in Fv with FvNameGuid. The ext header
causes the UefiPayloadEntry to be found incorrectly when parsing Fv.

Commit in EDKII: 4bac086e8e007c7143e33f87bb96238326d1d6ba
Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=3585

Signed-off-by: Dun Tan <dun.tan@intel.com>
Change-Id: Id063efb1c8e6c7a96ec2182e87b71c7e8b7b6423
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57296
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02 06:07:08 +00:00
Furquan Shaikh b9c22e0965 util/sconfig: Compare probe conditions for override device match
When the override functionality looks for device match, check that
the probe list for both the devices matches exactly if probe list
exists for the base device. This ensures that if there are two devices
with same identity (e.g. I2C address or USB port #) but using
different properties (registers) controlled by different probe
statements, then the two devices are not incorrectly matched as the
same device.

The check for base device having a probe list is performed before
comparing the probe lists because a base device might not really have
any probe requirements at all. So, when overriding such a device,
there is no need to check for the probe list match.

BUG=b:187193527
TEST=Verified by adding two I2C devices in the override tree with the
same I2C address and chip but different probe statements and confirmed
that both the devices are present in generated static.c file.

Change-Id: Ib18868b336cf4ffc9aa38aee7c6f333a35d32fce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-01 19:20:05 +00:00
Ricardo Quesada ff236ef832 cbfstool: add buffer_end() to common.h
Add buffer_end() function to common.h. This function returns a
pointer to the end of the buffer (exclusive).

This is needed by elogtool util. (See the next CL in the chain).

BUG=b:172210863

Change-Id: I380eecbc89c13f5fe5ab4c31d7a4fef97690a791
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-31 21:18:18 +00:00
Zheng Bao 481661e313 amdfwtool: Add flag for multi FW level to the struct amd_cb_config
This change can make the code be more flexible. And later we will use
amd_cb_config to transfer parameters.

Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:06:03 +00:00
Zheng Bao dac446165e amdfwtool: Copy string in a safer way
The issue is reported by Coverity. Using strcpy or strcat copying
string without checking length may cause overflow.

BUG=b:188769921

Reported-by: Coverity (CID:1438964)
Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31 15:05:48 +00:00
Maxim Polyakov d8163ede51 inteltool: Allow to set cores range for MSRs dump
Adds the ability to output MSRs dump for the specified range of CPU
cores. This makes it easier to reverse engineer server multicore
processors using the inteltool utility.

The range is set using --cpu-range <start>[-<end>] command line option:

  $ sudo ./inteltool -M --cpu-range 0-7
  $ sudo ./inteltool -M --cpu-range 7-15
  $ sudo ./inteltool -M --cpu-range 32

  $ sudo ./inteltool -M will print a register dump for all cores, just
as before.

Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35919
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-17 12:20:26 +00:00
Mackenzie May 9bd9362ae6 crossgcc: upgrade Expat from 2.2.9 to 2.4.1
Versions of expat before 2.4.0 have been renamed to prevent their
use, due to some kind of vulnerability. without updating this
dependency it is currently not possible to build crossgcc with GDB.

Change-Id: Iec2cf560902dc556a41206d7dcd65c22cf3e1215
Signed-off-by: Mackenzie May <ky0ko@disroot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56868
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16 10:00:42 +00:00
Bhanu Prakash Maiya adc9e63c59 util/mb/google: add template files for guybrush
Create template for guyrbsuh variant creation.

BRANCH=none
BUG=b:194031783
TEST=n/a

Change-Id: If62c1a63d0890539d4b43f840f75ee9d7ceab4f8
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13 18:03:40 +00:00
Tim Wawrzynczak 0e5b713d32 util/spd_tools/lp4x: Update README
The lp4x spd_tools also support Alder Lake (ADL), so update the the
README to reflect this fact.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iedb1ea1c3558e5f179feac2c725667db5b327b2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56857
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09 18:04:51 +00:00
Jack Rosenthal 09cc8f6677 elogtool: add to gitignore
Add the binary output of the new elogtool to the .gitignore, so that
running "make -C util/cbfstool" keeps the tree clean.

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I806338a4b33abbc3d55e4edef2736c19d56fa005
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09 15:02:36 +00:00
Idwer Vollering d78af11f72 util/kconfig: detect ncurses on FreeBSD
Even though pkg-config might be installed, it might or will not return
true in the checks whether 'PKG' or 'PKG2' is installed.

Extend the script to look in another location for ncurses.h

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-06 15:35:39 +00:00
Ricardo Quesada c2cf3946c9 util/elogtool: add tool to print elog events
Add a new tool that that prints elog events.
The tool, as input, accepts either a file with the RW_ELOG contents, or
if the file is not provided it reads the contents of RW_ELOG by calling
the "flashrom" tool.

The tool is based on "mosys eventlog list"[1]. For the moment it only
supports "list", but future commits will add additional functionality.

This commit also adds missing ELOG defines needed for the tool. These
defines are added with the rest of the ELOG defines, in
include/commonlib/bsd/elog.h

The tool is placed inside util/cbfstool. The rationale behind the
decision, is that this tool shares a lot in common with the other tools
located in cbfstool: vboot dependency, shared files like common.o and
valstr.o, and in spirit is similar to some of the tools located in
cbfstool/.

As an example, you call the tool like the following:

$ elogtool list -f rw_elog_dump.bin

[1]: https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/lib/eventlog/elog.c

BUG=b:172210863

Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ia1fe1c9ed3c4c6bda846055d4b10943b54463935
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2021-08-05 22:00:35 +00:00
Patrick Georgi 4b8b2a0f0b util/kconfig: Provide default for DEFCONFIG
Our documentation claims that the DEFCONFIG make variable, used for
targets such as savedefconfig, defaults to 'defconfig'.
With the update to kconfig 5.13 we lost this default, so bring it back.

Fixes: 53ea1d44f0 ("util/kconfig: Uprev to Linux 5.13's kconfig")
Resolves: https://ticket.coreboot.org/issues/317
Change-Id: Idb88b69ffa855fa97df8c821601308e717575550
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56718
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05 02:48:56 +00:00
Patrick Georgi 719d85bf56 util/xcompile: Allow overriding default compiler path
When looking for C compilers, xcompile uses the "" prefix to "gcc" and
"clang" as a last-resort option. This fails in environments where such
default names are blocked to prevent "unclean" builds - such as Chrome
OS.

Allow overriding this prefix using the GENERIC_COMPILER_PREFIX variable
that is hopefully both descriptive enough to suggest what it is for and
unusual enough to not trigger by chance.

Change-Id: I16239f66730f1dbcb7482f223cea4ee5957af10c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-28 23:01:12 +00:00
David Wu fc009cb31a util/spd_tools/lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for ADL:
1. H54G46CYRBX267
2. H54G56CYRBX247
3. K4U6E3S4AB-MGCL
4. K4UBE3D4AB-MGCL

BUG=b:194686484 b:194765811
TEST=build.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28 22:54:18 +00:00
Arthur Heymans c78521b376 util/cbfstool: Remove unused pagesize parameter
Change-Id: Ib672ba8ed418b1a76e4a48951eabda6923358e7a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55581
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 13:45:45 +00:00
Patrick Georgi 870cbb91ed util/kconfig: Stop trying to make sense of Linux configs
It only leads to missing symbol errors.

Change-Id: Idbce93232ba2b54561abab5b2747c418d6efa92b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-17 13:40:29 +00:00
Subrata Banik 6da003c910 util/ifdtool: Add APL to IFDv2 platforms
Initially APL was considered as IFDv2 platform irrespective being
added into ifd_2_platforms[], hence commit hash 621ed4c had migrated
APL into IFDv1 which break its FLMSTR1/FLMSTR2/FLMSTR3 Read/Write
access. This change adds APL into the list of IFDv2 platforms to fix
booting issue on the LeafHill board.

Change-Id: Ied59ddb2fe05b421266a6b119fd6eab17b8beedc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56300
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rick Lee <rick.lee@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 04:25:27 +00:00
Kangheui Won 275ade9539 Revert "amdfwtool: Use relative address for EFS gen2"
This reverts commit 0fc87e31e0.

Reason for revert: Breaks psp_verstage in guybrush

BUG=b:182477057

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56131
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:45:10 +00:00
Martin Roth 299558874c util/sconfig: Remove unused devicetree keywords ESPI & LPC
The ESPI & LPC keywords were added for the zork program, but it was
found that they weren't needed, so they were never used.

BUG=None
TEST=Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3a78afc55477d62eac8056e2ca4bcdd3ab12ea47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56197
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:24:00 +00:00
Patrick Georgi 53ea1d44f0 util/kconfig: Uprev to Linux 5.13's kconfig
This was originally several commits that had to be squashed into one
because the intermediate states weren't able to build coreboot:

 - one to remove everything that wasn't our own code, leaving only
   regex.[ch], toada.c, description.md and Makefile.inc.
 - one to copy in Linux 5.13's scripts/kconfig and adapt Makefile.inc
   to make the original Makefile work again.
 - adapt abuild to use olddefconfig, simplifying matters.
 - apply patches in util/kconfig/patches.
 - Some more adaptations to the libpayload build system.

The patches are now in util/kconfig/patches/, reverse applying them
should lead to a util/kconfig/ tree that contains exactly the Linux
version + our own 5 files.

Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-13 20:28:14 +00:00
Arthur Heymans 8585eabc5d util/abuild: Fix overriding results with the default configuration
I a file in configs/* has no suffix, then the default configuration
will override the results of the build generated by the configfile
from configs/*. Fix this by adding a '_' to the buildname.

Change-Id: Ic47105fafca41f1905a6569943079623bec5405a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-13 20:20:15 +00:00
Zheng Bao ec5a5d7abf amdfwtool: Fix the NULL pointer in parameters
Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08 18:52:00 +00:00
Zheng Bao 0fc87e31e0 amdfwtool: Use relative address for EFS gen2
The second generation EFS (offset 0x24[0]=0) uses
"binary relative" offsets and not "x86 physical
MMIO address" like gen1.

Chips like Cezanne can run in both cases, so no problem
comes up so far.

BUG=b:188754219
Test=Majolica (Cezanne)

Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-08 16:04:09 +00:00
Jan Tatje b7eec4a844 util/ifdtool: Add sklkbl to IFDv2 platforms
Currently ifdtool breaks the descriptor because it treats it as IFDv1.
This change adds it to the list of IFDv2 platforms.
Fixes boot for X11SSH-LN4F.

Fixes: 8c082e5fef ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset")
Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56070
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07 14:55:40 +00:00
Paul Menzel adface7ace util/board_status: Do not display grep message
Redirect stdout and stderr from grep to check for unknown timestamps,
when no timestamps are stored, which is already logged earlier.

    Failed to run "/root/coreboot/util/cbmem/cbmem -t", ignoring
    Getting remote dmesg
    grep: /tmp/coreboot_board_status.dXmbUIBP/emulation/qemu-i440fx/4.14-876-gdb28040ee1/2021-07-02T23_14_33Z/coreboot_timestamps.txt: No such file or directory

Change-Id: Ib5400d4bd17e957b4cc1bf75bbd332d60ad226f5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-05 10:51:12 +00:00
Raul E Rangel db28040ee1 util/cbfstool: Allow setting alignment for payload
The -a flag was already implemented, it just wasn't exposed for the
add-payload command.

Setting the alignment of the payload will enable using the SPI DMA
controller to read the payload on AMD devices.

BUG=b:179699789
TEST=cbfstool foo.bin add-payload -a 64 ...

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02 23:14:33 +00:00
Maxim Polyakov 8b35851e4c util/intelp2m: use import once for all included modules
There is no need to repeat "import" for each module in GoLang. Use
this keyword only once in each file for code cleanliness.

Change-Id: Ibb24fafd409b31b174946a39ca1f810d59b87e76
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55985
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02 07:48:58 +00:00
Arthur Heymans 5bb7dc4e05 cbfstool/cbfs-mkstage.c: Change signature of parse_elf_to_xip_stage()
The dereferced parameter is never updated so passing a copy would work
too.

Change-Id: Ie36f64f55d4fc7034780116c28aaed65aa304d5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55792
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01 15:22:08 +00:00
Arthur Heymans c44ffc3084 security/intel/cbnt: Build test CBnT provisioning
This updates the intel-sec-tools submodule pointer to include a fake
acm binary to be included for buildtesting.

Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-28 04:13:54 +00:00
Nico Huber 6cd4d32039 cbfstool: Unset ${DEBUG} when making vboot hostlib
Vboot's Makefile is controlled by a ${DEBUG} environment variable.
As the name is very generic, it may be set by accident without any
intention to change the build. Having it set would break reproduci-
bility at least but it also turns out that the hostlib build would
be incomplete so that linking cbfstool fails due to internal calls
to vb2api_fail() which is not built in.

Change-Id: I2a9eb9a645c70451a320c455b8f24bfed197117c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-26 10:07:34 +00:00