The patch defines acpi_set_cpu_apicid_order() which orders the APIC IDs
based on APIC IDs of Performance cores and Efficient cores, calculates
the total core count and total Performance cores count, populates the
information in the cpu_apicid_order_info struct.
The helper function useful to present the Performance and Efficient
cores in order to OS through MADT table and _CPC object.
TEST=Verify the build for Gimble (Alder Lake board)
Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72131
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to document 640858 MTL EDS Vol2, bit 18 (PWR_PERF_PLATFRM_OVR) of MSR_POWER_CTL must be set.
This patch is backported from
`commit 117770d324 ("soc/intel/
alderlake: Enable Energy/Performance Bias control")`.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74155
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.
This patch is backported from
`commit 0bb2225718 ("soc/intel/alderlake: Add EPP override
support")`.
BUG=b:266522659
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8172276159fe3987dae36ec30ebceb76dd0ef326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74154
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Indent with tabs for the sake of consistency with the rest of the code.
Change-Id: Ibd325a7a8348cc1f9023e54dceab40d02a0df233
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add the 28W TDP version of the ADL-P with MCHID 0x4629.
Verified that all 28W SoCs have the same PL1/PL2 defined
in Intel document #655258 "12th Generation Intel Core
Processors Datasheet, Volume 1 of 2".
Fixes the error seen in coreboot log:
[ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration
Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This patch updates the Rex flash layout to allow CSE Lite FW
update and accommodate multiple ESx SoC stepping blobs.
For default chromeos.fmd
SI_BIOS:
RW_SECTION_A/B: Increased by ~1.9MB.
RW_LEGACY: Reduce to 1MB.
RW_MISC: Reduce to 152KB.
- Drop RW_SPD_CACHE
- Optimize other sections
Additionally, moved RW_LEGACY under extended BIOS region.
For chromeos-debug-fsp.fmd
SI_BIOS:
RW_SECTION_A/B: Increased by ~1.2MB.
RW_LEGACY: Dropped
RW_MISC: Reduce to 152KB.
- Drop RW_SPD_CACHE
- Optimize other sections
BUG=b:262868089
TEST=Able to enable CSE update on google/rex and have free space
to add one more PUNIT FW for support different SoC stepping.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
tsc_freq.c gets built into all stages, but the tsc_freq_mhz function it
implements calls the get_pstate_0_reg function which was only built into
ramstage. Since tsc_freq_mhz was only called in ramstage, commit
2323acab6a ("soc/amd/stoneyridge: implement and use get_pstate_0_reg")
didn't cause the build to fail, but better factor out the P-state-
related utility functions into a separate compilation unit and include
it in all stages that also include tsc_freq.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id3a3ee218f495be5e60a888944487704e7e8a1a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
monotonic_timer.c, tsc_freq.c and uart.c get added to all stage targets,
so just add those to the all stage targets. They still need to be added
to the smm stage target, since the all target doesn't add things to the
smm stage.
TEST=Timeless build results in identical image for Gardenia.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I16c02bc0ff54553f212b94d110abef6a7bdedbb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74144
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Debian removed Python 2 from their Sid repository and so it needs to be
removed from the Dockerfile as well.
Built and tested the Dockerfile with Python 2 removed. Still works.
Change-Id: If4e298dc275c1dfaf57cd4c3f8e5f89410318ec0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests.
The code was written from scratch because there are Xeon-SP specific
implementation especially Integrated Input/Output (IIO).
Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Debug FSP is ~920KiB larger than release FSP and we don't have
sufficient space for rex flash layout.
Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a
room for it.
Note: This fmd will only used for internal testing/debugging and not for
the firmware in released devices.
BUG=b:262868089
TEST=Build google/rex with CONFIG_BUILDING_WITH_DEBUG_FSP.
Change-Id: I58b0af9c43c5d096dc80084497b39f13f67c25cd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Intel FSP has "debug" build which is not public, used for debugging by
approved developers. Add a Kconfig to indicate that coreboot is building
with debug version of FSP so we can adjust few things (i.e. flash
layout) in the case.
BUG=b:262868089
TEST=Able to build and boot google/rex.
Change-Id: I5555a2ab4182ad0036c42be6fea3d934ffd0db8c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
PortUsb30Enable has been overridden unexpectedly, this patch fixed it.
BUG=b:276181378
Test=boot to rex and check USB3 ports are working.
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ic04b9eb236ed28a76ee516c52fc0c983cb8f2c0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The patch enables addition of core_type member to 'struct cpu_info'
for MeteorLake platform.
TEST=Build and verify the code for Rex
Change-Id: I01abed6b87bec2f8eb39bfc941faff070b83abe6
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74130
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Now that only one build target per stage is included in the build
depending on CONFIG_SOC_AMD_COMMON_BLOCK_TSC being set, don't use a
separate ifeq block for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9e551b37707081eb2ea1d682013f57c7ca8aabd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74017
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All AMD SoCs with Zen-based CPU cores are already using timestamps based
on the TSC counter, so use the existing common infrastructure instead of
reimplementing it in a similar way.
The behavior of the code changes slightly, but results in identical
timestamps. The timestamp_get implementation in soc/amd/common/block/cpu
divided the result of rdtscll() in timestamp_get by the result of
tsc_freq_mhz() and didn't override the weak timestamp_tick_freq_mhz
implementation that returns 1. The non AMD specific code returns the
result of rdtscll() in timestamp_get, but returns tsc_freq_mhz() instead
of 1 in timestamp_tick_freq_mhz, so we still get the correct timestamps.
TEST=The raw timestamps printed on the serial console are now multiplied
by the expected factor of the TSC frequency in MHz.
TEST=Normalized timestamps printed on the serial console by the x86 code
don't change significantly on Mandolin when comparing before and after
this patch. A slight variation in the timestamps is expected. An example
would be:
Before: CPU_CLUSTER: 0 init finished in 630 msecs
After: CPU_CLUSTER: 0 init finished in 629 msecs
TEST=The calculations of the time spent in verstage on PSP before
entering the bootblock on Guybrush result in similar times when
multiplying the value before the patch with the TSC frequency in the
case with the patch applied. The raw values printed on the serial
console by the verstage on PSP use the 1us time base, but the timestamp
logs that end up in CBMEM will be fixed up to use the same time base as
the x86 part of coreboot.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I57b732e5c78222d278d3328b26bb8decb8f4783e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Having L1.2 enabled on the SD port increases the kernel resume times by
between 30 & 40ms. This patch disables L1.2 on SD to get that time
back.
As with needing to have hotplug enabled on the SD card, this seems like
a driver issue, so hopefully that will get sorted out and this patch
can be reverted.
BUG=b:274025743
TEST=resume times are decreased.
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2c409fa2cd66c712c5ba7104635499d63fa0d2be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot supports three instances of sending EOP:
1. At CSE `.final' device operation
2. Early as with Alder Lake in chip_operations.init if
`SOC_INTEL_CSE_SEND_EOP_EARLY' is selected
3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if
`SOC_INTEL_CSE_SEND_EOP_LATE' is selected
Currently, Alder Lake uses #3 as it results in better and more stable
boot time. However, what would deliver even better result is to not
actively wait for CSE completion.
This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig
which split the action of sending EOP request and receiving EOP
completion response from the CSE.
This patch used in conjunction with #1 can significantly
improves the overall boot time on a Raptor Lake design. For example
`SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36
ms boot time improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 1 | 1020.052 | 971.272 |
| 2 | 1015.911 | 971.821 |
| 3 | 1038.415 | 1021.841 |
| 4 | 1020.657 | 993.751 |
| 5 | 1065.128 | 1020.951 |
| 6 | 1037.859 | 1023.326 |
| 7 | 1042.010 | 984.412 |
|----------+----------+-----------|
| Mean | 1034.29 | 998.20 |
| Variance | 4.76 % | 5.21 % |
The improvement is not stable but comparing coreboot and FSP
performance timestamps demonstrate that the slowness is caused by a
lower memory frequency (SaGv point) at early boot which is not an
issue addressed by this patch.
We also observe some improvement on an Alder Lake design. For example,
the same configuration on a kano board can deliver up to 10 ms boot time
improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 0 | 1067.719 | 1050.106 |
| 1 | 1058.263 | 1056.836 |
| 2 | 1064.091 | 1056.709 |
| 3 | 1068.614 | 1055.042 |
| 4 | 1065.749 | 1056.732 |
| 5 | 1069.838 | 1057.846 |
| 6 | 1066.897 | 1053.548 |
| 7 | 1060.850 | 1051.911 |
|----------+----------+-----------|
| Mean | 1065.25 | 1054.84 |
The improvement is more limited on kano because a longer PCIe
initialization delays EOP in the Late EOP configuration which make it
faster to complete.
CSME team confirms that:
1. End-Of-Post is a blocking command in the sense that BIOS is
requested to wait for the command completion before loading the OS or
second stage bootloader.
2. The BIOS is not required to actively wait for completion of the
command and can perform other operations in the meantime as long as
they do not involve HECI commands.
On Raptor Lake, coreboot does not send any HECI command after
End-Of-Post. FSP-s code review did not reveal any HECI command being
sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or
`END_OF_FIRMWARE' notifications.
If any HECI send and receive command has been sent the extra code
added in `cse_receive_eop()' should catch it.
According to commit 387ec919d9 ("soc/intel/alderlake: Select
SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first
boot after flashing of a Marasov board for instance) request coreboot
to perform a global request out of AFTER_PCI_ENUM notification. Global
request relies on a HECI command. Even though, we tested that it does
not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not
be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent
potential a global reset command to "conflict" with the EOP command.
BUG=b:276339544
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post sent soon after FSP-s and EOP message receive at
`BS_PAYLOAD_BOOT'. Verify robustness by injecting a
`GET_BOOT_STATE' HECI command with or without `heci_reset'. The
implementation always successfully completed the EOP before
moving to the payload. As expected, the boot time benefit of the
asynchronous solution was under some injection scenario
undermined by this unexpected HECI command.
Change-Id: Ib09dcf9140eb8a00807a09e2af711021df4b416f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73619
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
In order for the code to find the correct VBIOS file in CBFS, remap the
revision ID in the RAVEN2_VBIOS_VID_DID case to the one that matches the
CBFS file name. This will make the code work as expected on devices with
the PCI ID RAVEN2_VBIOS_VID_DID and a revision != RAVEN2_VBIOS_REV.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94412dc2e778e7c4f74e475cd49114a00a81b2ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74045
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a new port for the Intel DQ67SW desktop board. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.
A list of tested working and non-working features is in the
documentation page.
Change-Id: Ifc703f2d0ad45495e71d3f7799347430f5196791
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:275644832
TEST=emerge-dedede coreboot
BRANCH=firmware-dedede-13606.B
Change-Id: I644f3aa3187e08146d78abb70a568833bc9b9211
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Initial hades GPIO config. Combination of original brya basebaord,
Agah and new arbitrage output for hades design.
Also moved GPIO config to the non baseboard variant model as we did on
rex0.
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I2a850240dd7f3ddf137d6a2ebe8a147f8976c16b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The patch enables addition of core_type member to 'struct cpu_info' for
Alderlake platform.
TEST=Build and verify the code for Gimble
Change-Id: Ia065b98c2013e78328fd38bed9c667792d6d1f4d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74089
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The patch adds new member 'core_type' to the 'struct apic_path' and
updates core type information.
TEST=Build the code for MTL
Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Refactor map_oprom_vendev_rev as a preparation to also remap the
revision ID in the RAVEN2_VBIOS_VID_DID case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b81a9464ed49672889fcb767920154fe6efdfcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Add early configuration of the GPIOs that control the M2 SSD resets.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I81439d193bdd7296d8a8fea83c5c6be2c75adbea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73989
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add option decode for USB-C DDI connection type and remove unnecessary
break after return.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If38fa667daeb2dd176ecdf33abaec9b56d633a2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Realtek RTL8111E NIC is currently not defined as a child device,
resulting in the on_board flag not being set to 1. This means that
Linux / udev will call the device enp4s0 rather than eno0, as is
appropriate for on-board ethernet devices.
This patch defines the NIC as a child device of PCIe port 6, so that
it's properly defined as an on-board device.
Change-Id: I2e1b65e4d27852297a739e332c52c15a8c81b858
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74090
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use enum cb_err as return value of fsp_find_range_hob instead of using
the raw -1 and 0 values. Also update the call sites accordingly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6c9f69a886f53868f1ef543c8fa04be95381f53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Since the return value of the fsp_find_range_hob call is only used in
one location, move the call and return value check into the if condition
block to not need the status variable.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b9e9251368b86382dc4e050cf176db79dbfb230
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
To avoid having to calculate the length of a struct separately, rework
the code to give the struct a tag name, so that `sizeof()` can be used
instead. This involves refactoring the `get_emi_eeprom_vpd()` function
to return a struct instead of a union, so callers can no longer access
the EEPROM data as an array of bytes without additional code, but this
array view is only used inside `get_emi_eeprom_vpd()` when reading the
data from EMI.
Change-Id: Id1bc40939631baa131b5f60eadbfe42838294ebe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch avoids the redundant programming of SRAM BAR when
the SRAM PCI device is enabled. Rather read the PCH SRAM Base
Address Register while enabling crashlog feature.
Additionally, this patch relies on PCI enumeration to get the
SRAM BAR rather than hijacking the SPI temporary base address
which might have resulted in problems if SPI is disabled on
some platform with BAR being implemented.
TEST=Able to build and boot google/marasov and crashlog is working.
Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:273791621
TEST=emerge-nissa coreboot
Change-Id: I1a6013e0ad0c430d83bbbad4b92392c8c4815b0d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Use die_no_apcb to cause a build error when the APCB or SPD sources are
not found.
TEST=builds with and without matching APCB and SPD sources
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I62dce2c71061bfc5c01e0344b7dc115a47669140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This sets the location of the skyrim MP2 firmware within the mainboard's
blobs directory, and adds the Kconfig option to the mainboard directory
so that it can be enabled in a saved .config file.
The skyrim MP2 firmware is skyrim specific, so it should not be placed
in the main PSP AMD_BLOBS directory.
We will also only want to enable the MP2 firmware for chromeos builds as
it's not useful for non-chromeos builds.
BUG=b:259554520
TEST=Build MP2 firmware into image, see that it gets loaded
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I04be6f2d0b605d4eca37fd927a70310259dc106c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Instead of using the PSTATE SSDT generated by binaryPI, use the common
AMD code by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE. To
match the SSDT from binaryPI, set ACPI_SSDT_PSD_INDEPENDENT to n. There
are two differences to the binaryPI SSDT: Now coreboot includes the C1
state in the _CST package instead of just having the kernel add this due
to the ACPI_FADT_C1_SUPPORTED bit being set and the address of the
PS_STS_REG P state status MSR is written to the corresponding field of
the _PCT package instead of being 0.
TEST=On Careena the new P and C state ACPI packages are nearly identical
to the ones from the SSDT from binaryPI with the two functional
differences mentioned above.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icdf6bc8f0e0363f185a294ab84edcb51322e7eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Both the algorithm and the registers involved are described in the
public version of BKDG #55072 Rev 3.09 in chapter 2.5.2.1.7.3.2 _PSS
(Performance Supported States).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b2c177d9d80c5c205340f3f428186d6b8eb7e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The help text for VGA_BIOS_SECOND_ID was outdated and from a time before
we found out that just looking at the CPUID doesn't reliably tell us on
which type of silicon we're running and which VBIOS file to pick, so we
had to use a different method. Update the help text to match what the
code does.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia568771ed7dfa0c7bb850b0efcd2959d7ddfd4a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73335
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
On the Zen-based CPUs, the transition and bus master latency are always
written as 0, but on but on Stoneyridge hardware-dependent values are
used. Introduce get_pstate_latency that returns 0 for all non-CAR AMD
CPUs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81086fa64909c7350b3b171ea6ea9b46f1708f67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Introduce get_pstate_0_reg and use it in tsc_freq_mhz to get the P state
register number corresponding to P state 0.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b92a858bf36b04a570d99c656e5ccfc84457724
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Van Chen