Commit Graph

48703 Commits

Author SHA1 Message Date
Joey Peng ad6b27e9ef mb/google/brya/var/taeko: Disable PCH USB2 phy power gating for taeko
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for taeko board. Please refer Intel doc#723158 for
more information.

BUG=b:241965786
TEST=Verify on taeko/tarlo boards.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I03042906d5bea9b9010016adb98fbe68e2dc92f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-12 17:15:43 +00:00
Yidi Lin 8610dd5022 libpayload: usbmsc: Prevent usbdisk_remove() from being called twice
When removing SD card from USB card reader, the USB MSC stack does
not detach the device immediately. Instead, the USB MSC stack calls
usbdisk_remove() and calls usb_msc_destroy() after several pollings.
It results in usbdisk_remove() being called twice.

Since the usbmsc_inst_t instance is freed after first usbdisk_remove()
call, the second call invokes an invalid usbmsc_inst_t instance and
causes exception in CPU.

This patch prevents usbdisk_remove() from being called twice by setting
usbdisk_created to zero.

BUG=b:239492347
TEST=insert an empty SD card into the USB card reader then remove
     the SD card. AP firmware does not crash.

Change-Id: I0675e9fde3e770d63dd0047928356a204245ef18
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66449
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12 17:14:54 +00:00
Allen-KH Cheng a4795c01ed soc/mediatek/mt8186: Enable USB macro control
When powering down SSUSB, the system needs to wait the ACK from SSUSB.
We found that the setting of USB PAD top macro is not correct and
it will cause timeout waiting for the ACK from SSUSB.

To resolve this, we add mt_pll_set_usb_clock() in pll.c to enable usb
macro control for powering down SSUSB.

TEST=timeout of ssusb powerdown ack does not occur.
BUG=b:239634625

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: I58ba86e0467284e9947bfda1005c151a3e0c8881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66600
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-08-12 17:13:08 +00:00
John Su ec37ef2bae mb/google/brya/var/mithrax: Add new memory H9HCNNNCPMMLXR-NEE
Add new ram_id:0001 for memory part H9HCNNNCPMMLXR-NEE.

BUG=b:241494931
TEST=none

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iee9f881d8ab21396d208a6af9f0cec8414cb50a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-08-12 17:12:31 +00:00
Maximilian Brune 667d0f8966 Fix Alder Lake and Raptor Lake Device ID's
- ADP_P_* -> RPP_S_* (got mixed up I guess)
- Remove duplicates of ADP_S_ESPI_*
- Add infix _ESPI_ to all ADP_S device ID's

Document: 619362

Change-Id: Ic18ecbd420fc598f0ef6e3cf38e987ac3ae6067e
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66629
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12 17:12:12 +00:00
Maximilian Brune a0bc90e4ab Add missing ADL-S device identification
R680E, Q670E, H610E are the ADL-S IoT variants

TEST=Boot ADL-S RVP DDR5 and see silicon info is reported
as PCH: AlderLake-S R680E

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I1804994b4b72f0484eabb15323736679d2668078
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-12 17:12:12 +00:00
John Zhao eb80b1efa3 soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS
This change provides access to IOE through P2SB Sideband interface for
Meteor Lake TCSS functions of pad configuration and Thunderbolt
authentication. There is a policy of locking the P2SB access at the end
of platform initialization. The tbt_authentication is read from IOM
register through IOE P2SB at early silicon initialization phase and its
usage is deferred to usb4 driver.

BUG=b:213574324
TEST=Built coreboot and validated booting to OS successfully on MTLRVP
board. No boot hung was observed.

Change-Id: Icd644c945bd293a8b9c4a364aaed99ec4a7c12f9
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12 17:11:22 +00:00
John Zhao 8d37fbdcf9 soc/intel/common: Delete the TBT authenticaton function
Delete the Thunderbolt authentication function ioe_tcss_valid_tbt_auth
from the common block. Meteor Lake Platform will implement it.

BUG=b:213574324
TEST=Built coreboot image successfully.

Change-Id: I97a289faa6351fe562f91d8478b72c9403ce88cb
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12 17:11:22 +00:00
Angel Pons 0e7cf3d81d soc/intel/alderlake: Fix DDR5 channel mapping
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Alder
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.

To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.

Tested on AlderLake-P DDR5 RVP (board ID 0x12), both DIMM slots now
function properly. Without this patch, only the top slot would work.

Change-Id: I5f01cd77388b89ba34d91c2dc5fb843fe9db9826
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66608
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-12 17:10:30 +00:00
Tim Crawford a8cf2f2d73 mb/system76/gaze16: Rename variant dir
Use the actual model name for the variant dir.

Change-Id: I199b8efb5c3cddb8943ba4b761546caa11c67a30
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-08-12 17:09:53 +00:00
Tyler Wang da10c48eb7 mb/google/nissa/var/craask: Enable DDR RFIM Policy for Craask
Enable RFIM Policy, request by RF team.

BUG=b:239657092
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Id0f425d75a1ac9486a9284d4e8320ba4c63b182f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-08-12 17:08:30 +00:00
Altamshali Hirani 8915abe115 amdfwtool/amdfwtool.h: Allow 16 additional PSP entries to be supported
Consolidate MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one
file

Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com>
Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62911
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12 14:16:18 +00:00
Zheng Bao c86c0cdb11 Doc/psp_integration.md: Update infomation with latest document
Update coreboot.org PSP Firmware Documentation with current internal
PSP documentation.

Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-12 14:16:18 +00:00
Jon Murphy 05208b50c5 util/spd_tools: Rename Sabrina to Mendocino
'Mendocino' was an embargoed name and could previously not be used.
Update amdfwtool for consistency with the correct naming convention.

BUG=b:239072117
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I404fcf59e89b75cd2488bcb51981aee2eb4ff0df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12 13:46:48 +00:00
Subrata Banik a920772d29 mb/google/rex: Add ACPI support for Type-C ports
This patch backported from commit ba2e51bd49 (mb/google/brya: brya0:
Add ACPI support for Type-C ports) for google/rex.

BUG=b:224325352
TEST=Able to build Google/Rex and boot on MTLRVP.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If0a9510784e8f62861ae4bc74805b1513a4865cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66538
Reviewed-by: Prashant Malani <pmalani@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-12 08:17:49 +00:00
Subrata Banik 52398d6474 mb/google/rex: Describe USB2/3 ports in devicetree
This patch describes the USB2/3 ports in devicetree to generate ACPI
code at runtime. The ACPI code includes the port definition, location,
type information.

BUG=b:224325352
TEST=Able to build and boot MTLRVP.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7d787a9986099852d6a0d193bbc28487bf430fe4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66542
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12 08:17:32 +00:00
Subrata Banik 50c73b5d46 mb/google/rex: Update mainboard properties for BB retimer
This patch backport commit 9e23d017f5 (mb/google/brya: Update
mainboard properties for BB retimer upgrade) for Google/Rex.

BUG=b:224325352
TEST=Able to build and boot MTLRVP.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I508858683cf3cdb0cab5a564fef4a242f8a6679e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66541
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12 08:17:10 +00:00
Subrata Banik 5be9959e73 mb/google/rex: Describe TCSS USB ports in devicetree
This patch describes the TCSS USB ports in devicetree to generate ACPI
code at runtime. The ACPI code includes the port definition, location,
type information.

BUG=b:224325352
TEST=Able to build and boot MTLRVP.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I08613b31aad47cbf573ed1b5fc68c91cf973e190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66540
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-12 08:16:43 +00:00
Subrata Banik c15281f91d mb/google/rex: Add OC pin programming for USB2 Port 8
This patch adds OC pin programming for USB2 Port 8.

BUG=b:224325352
TEST=Able to build and boot MTLRVP.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic9dcaef5972d6c0e9fe264445ea10fcd9a82619f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66543
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-12 08:16:37 +00:00
Wonkyu Kim a88848907f soc/intel/meteorlake: Have non prefetchable MMIO for IGD BAR0
Enable SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO for MTL to fix guc driver
failure.

BUG=b:241746156
TEST=boot to OS and check guc driver loading successful
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ifc20935bccdda55db3e57eecd37a4260b3f1a2d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66613
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12 07:30:32 +00:00
Wonkyu Kim 91bd6e19c9 soc/intel/common: Ignore prefetch PCI attribute for IGD BAR0
From Meteorlake, IGD BAR0(GTTMMADR) is changed to 64bit prefetchable.
Due to the prefetchable attribute, resource allocation for IGD BAR0 is
assigned WC memory and it causes kernel driver failure.

For avoiding kernel driver failure, ignore prefetch PCI attribute
for IGD BAR0 to assign UC memory.

We're working on publishing below information.
- IGD BAR0(GTTMMADR) is changed to 64bit prefetchable BAR
- GTTMMADDR BAR should be always mapped as UC memory although
  marked Pre-fetchable.

BUG=b:241746156
TEST=boot to OS and check guc driver loading successful
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I76d816d51f32f99c5ebcca54f13ec6d4ba77bba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66403
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12 07:29:14 +00:00
Jon Murphy 9969f4b609 util/amdfwtool: Rename Sabrina to Mendocino
'Mendocino' was an embargoed name and could previously not be used.
Update amdfwtool for consistency with the correct naming convention.

BUG=b:239072117
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I673a9b99d207603b605756fc7d277c54c5d0f311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66467
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-11 19:45:20 +00:00
Jon Murphy 4f73242052 treewide: Rename Sabrina to Mendocino
'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim.  coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".

BUG=b:239072117
TEST=Builds

Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-11 19:15:30 +00:00
Martin Roth 251e26683e util/lint: Add .gitignore files to list that don't need a license
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I568a357b40e8bb69b2b26752d241f06adfbe029e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11 17:53:48 +00:00
Martin Roth fb8876d356 lib: Add SPDX identifiers to files missing them
This adds SPDX identifiers to the remaining source files in the
lib directory that don't already have them.

A note on gcov-iov.h - As machine generated content, this file is
believed to be uncopyrightable, and therefore in the public domain, so
gets the CC-PDDC license even though there is code in the file.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ifcb584d78a55e56c1b5c02d424a7e950a7f115dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11 17:53:29 +00:00
Martin Roth f18034c1b3 include: Add SPDX identifiers to files missing them
This adds SPDX identifiers to the remaining source files in the
include directory that don't already have them.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I0dbf4c839eacf957eb6f272aa8bfa1eeedc0886f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66501
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11 17:53:11 +00:00
Martin Roth eaa21ae171 southbridge: Add SPDX identifiers to files missing them
This adds SPDX identifiers to the remaining source files in the
southbridge directory that don't already have them.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: If74aa82a7c40293198e07e81ceac52bd8ca8ad27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66500
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11 17:52:52 +00:00
Martin Roth f7319225e9 drivers: Add SPDX identifiers to files missing them
This adds SPDX identifiers to the remaining source files in the
drivers directory that don't already have them.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I97f96de857515214069c3b77f3c781f7f0555c6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66499
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11 17:52:38 +00:00
Martin Roth c0f85e7a18 src/mb: Add SPDX identifiers to files missing them
This adds SPDX identifiers to the remaining source files in the
mainboard directory that don't already have them.

Change-Id: I1adc204624f3ab6fcafd8fbb239e6d69e057973a
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66498
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11 17:52:19 +00:00
Srinidhi N Kaushik 9f6e25d6b0 src/soc/intel/mtl: Add VPU support
This change adds support for enabling VPU on MTL SoC.

BUG=b:240665069
TEST=build coreboot mtlrvp

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie79b45f34a669b9ff777599cb85217abac6cb74e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-08-11 07:35:41 +00:00
Mark Hsieh 7a0eff6b8e mb/google/nissa/var/joxer: Add WiFi SAR table
Add WiFi SAR table for joxer.

BUG=b:239788985
TEST=build FW and checked SAR table can load by WiFi driver.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ia8dddf454e441840233fa4405704ee1f0a8ed86c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66522
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-10 19:26:18 +00:00
Lance Zhao 7ef330304b docs/utils/ifdtool: Fix waning of malformed table
Signed-off-by: Lance Zhao <lance.zhao@gmail.com>
Change-Id: Idc90c6e8186320979a72563fb5dcdc8fce760e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66562
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-10 19:24:16 +00:00
Frans Hendriks f4040e63c8 soc/intel/tigerlake: Add USBOTG and CrashLog to irq table
FSP reports missing IRQ for devices.

Add USBOTG (D20:F1) and CrashLog & Telemetry (D10:F0) to irq_constrain.

Bug = N/A
TEST = Build and boot Siemens AS-TGL1

Change-Id: Ic02d33045a07a6888ba97d8f2c6fa71bc7e363e8
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-10 19:21:06 +00:00
Martin Roth f67a1aa76a util/lint & LICENSES: Add PDDC as a "license" for coreboot
The Creative Commons Public Domain Dedication and Certification is not
a license in the common sense in that it's stating that the associated
file is already in the public domain (having no copyright), and is not
actually putting it in the public domain like the CC-C0 license does.

The use for this in coreboot is for unlicensable files - either blank
files or files with no creative content.  This allows these files to
have the SPDX identifier to identify them as having no known copyright
for open source license compliance.

If CC-PDM-1.0 is ever included in the list of SPDX licenses, that would
probably fit better, but because the public domain mark isn't actually
a license, and because "public domain" isn't well defined, CC-PDM was
rejected as a SPDX identifier.

For further information:
https://web.archive.org/web/20201018194411/https://github.com/spdx/license-list-XML/issues/988

Change-Id: Ibb300ecd066cde2a016195c2beca76a460c588e3
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66496
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:07:20 +00:00
Martin Roth afa3e5aa49 util/lint & LICENSES: Add GCC-exception-3.1 to license exceptions
The gcov files in the lib directory are licensed GPL 3.0 with the GCC
runtime library exception.

Add this as a valid license so that the files can get a correct SPDX
identifier.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I1cf9c3125592741923c9b4481038055f24fe6ab1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:07:02 +00:00
Martin Roth 34f0f05158 LICENSES: Add missing licenses and exceptions
These licenses and exceptions are allowed by coreboot's license checker,
but the copies of the licenses were missing from the LICENSES directory.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ic4233e556de08275fe50f1ec83828f9470b4b566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66494
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:06:46 +00:00
Raul E Rangel 30edb46e8c mb/google/zork: Set vw_irq_polarity from low to high
The EC used on zork uses a level high interrupt. This change configures
the polarity correctly.

The eSPI config is baked into RO verstage. The zork ToT build doesn't
use signed verstage since it's incompatible with the ToT version of
vboot. This means we can safely switch the keyboard IRQ polarity.

NOTE: Do not cherry pick this into the Zork firmware branch!

BUG=b:160595155
TEST=On morphius verify keyboard works as correctly and no spurious
interrupts are thrown on S0i3 resume. Also verified keyboard and mouse
work correctly in windows.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d3195522f3bd5e477635494c7156683aae0ff0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-10 17:13:07 +00:00
Raul E Rangel 74bce48f1d mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity
The default state for the IRQ lines when the eSPI controller comes out
of reset is high. This is because the IRQ lines are shared with the
other IRQ sources using AND gates. This means that in order to not cause
any spurious interrupts or miss any interrupts, the IO-APIC must use a
low polarity trigger.

On zork/guybrush/skyrim the eSPI IRQs are currently working as follows:
* On power on/resume the eSPI controller drives IRQ 1 high.
* eSPI controller gets configured to not invert IRQ 1.
* OS configures IO-APIC IRQ 1 as Edge/High.
* EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1
  high.
* eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ
  1 as high. This results in missing the first interrupt.
* When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the
  eSPI controller to set IRQ1 to low. We are now primed to catch the
  next edge high interrupt. This is generally not a problem since the
  linux driver will probe the 8042 with interrupts off.

On S3/S0i3 resume since the eSPI controller comes out of reset driving
the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is
configured to trigger on edge high. This results in the 8042 controller
getting incorrectly marked as a wake trigger.

By configuring the IO-APIC to use low polarity interrupts, we no longer
lose the first interrupt. This also means we can use a level interrupt
to match what the EC actually asserts.

We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI
because the linux kernel will ignore the level/polarity parameters
for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't
have this problem.

The PIC is not currently configured anywhere and it defaults to an
edge/high trigger. We could add some code to configure the PICs trigger
register, but I don't think we need the functionality right now.

For zork and guybrush, this change is a no-op. eSPI is configured in
verstage which is located in RO, and we have already locked RO for
these devices. We will need to figure out how to properly set the
`vw_irq_polarity` for these devices.

BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104
TEST=On zork, guybrush and skyrim
$ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count'
Verify keyboard works as expected and no interrupt storms are observed.

On morphius I verified keyboard and mouse work on windows as well.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-10 16:30:19 +00:00
Kapil Porwal 423bc1a379 MAINTAINERS: Add lists for soc/intel/meteorlake and mb/google/rex
Change-Id: Ia5def4cf86b47ac96ba5fc6ec86a139d5ad2765e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-09 19:24:00 +00:00
Stanley Wu c8ffc82734 mb/google/nissa/var/pujjo: Enable USB3.0 port 3 for WWAN
Pujjo support WWAN device, enable USB3.0 port 3 for WWAN device

BUG=b:241322361
TEST=Build and boot on pujjo

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Iafe2ea18663794138e0a27879fc108d23eb81456
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-09 19:23:02 +00:00
Martin Roth 298b00776a utils: Add initial version of "remove_unused_code" script
This script creates a patch to remove all of the coreboot code that a
platform doesn't use.  This is useful for auditing the codebase for an
individual platform or releasing a platform's code.

Unlike the script that Sage used that did something similar, this keeps
the entire Kconfig tree (Though in a single file), all makefiles that
are required to build, and the standard build tools can still be used.
This will allow for much easier re-integration back into the coreboot
codebase if code is released after running this.

This is just the initial version and more features needed to be added to
make it fully functional.
- It should be able to build multiple configurations to retain the code
for all of those configurations.
- Flag to remove submodules files as well
- Additional variable flags to replace hardcoded values.
- The list of makefiles that need to be kept is pretty long, and could
be updated so that they aren't needed by the top level makefiles.
- Add flag to show changed files
- Show number of files before and after script is run

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iec69db2ad1358846d649db627b6d60ac8c2204e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-09 19:22:31 +00:00
Kevin Chowski a31b7ea7f7 mb/google/brya/var/ghost: update arbitrage gpio.c header
This update follows suggestions from Martin Roth about the contents of
the comment.

Change-Id: Ic296bcd6a0fb250426f5d75aac69a3fa0f2aaf32
Signed-off-by: Kevin Chowski <chowski@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-09 17:03:31 +00:00
Karthikeyan Ramasubramanian e5af14ace6 util/amdfwtool: Fix ISH_B directory offset
On boards which use both PSP recovery A/B layout as well as VBOOT A/B
layout, ISH_B directory entry is pointing directly to PSP Level2
directory. This is not correct and either ISH_B should be marked as not
present or it should point to the ISH_A directory itself which in turn
point to PSP L2 directory. Fix it by choosing the latter option.

BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-09 16:44:47 +00:00
Meera Ravindranath 5e80bcfaea mb/google/brya: Select SOC_INTEL_COMMON_UFS_SUPPORT for Nissa
BUG=b:238262674
TEST=Build and check ufs.c file gets compiled for Nissa boards

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Idc5ad922b97bd1e65e5023f9126c43e42cfc38a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66064
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-08 18:08:16 +00:00
Marshall Dawson 26d7d737c1 soc/amd/sabrina: Rename PSP SPL default
Change the SPL file from the 'cezanne' placeholder to a mendocino
filename.  Also, move the default location to blobs/mainboard since
it's not board-agnostic.

BUG=b:241543152
BUILD=Enable feature and build amd/chausie

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I47647c5d926484e25e3f893e72c671554e277a56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-08 16:59:30 +00:00
Marshall Dawson 84fef892dd soc/amd/sabrina: Rename PSP whitelist default
Change the name of the whitelist file from the 'cezanne' placeholder
to a mendocino path/to/file.  Also, as whitelist files won't be pushed
into a public repo, modify the path to point to site-local.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I49bbf1335606567735e36ed9bda1314bfc6247d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-08 16:59:30 +00:00
Marshall Dawson 336e25a3b7 soc/amd/sabrina: Use new mendocino amd_blobs
Modify sabrina's fw.cfg to point to the proper directory and use the
standard names, as released by AMD.

The name 'sabrina' was an alias used for the Mendocino product.  The
public-facing builds have been using Cezanne blobs, renamed as Sabrina
or SBR, but can now take advantage of the appropriate blobs.

BUG=b:239072117
TEST=Build amd/chausie

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Id646844e41980802be1e39dce96e5adaace4311d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07 19:57:06 +00:00
Marshall Dawson cdaefbbdd9 3rdparty/amd_blobs: Advance submodule pointer
This picks up the following changes
  83c44ad mendocino: Add additional SPI configs
  5141d91 mendocino: Add all blobs from PI 1.0.0.1
  3b29a7d cezanne: Upgrade microcode patch to 00A50F00h

BUG=239072117

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I1060dc7bec8f436dccf270bc3abde75cb09bb591
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07 19:56:38 +00:00
Jon Murphy 156aa9b4c7 mb/google/skyrim: Resolve boot behavior
Move GPIO init for SSD_AUX_RESET_L to ensure that eMMC devices
will be initialized in time for the nominal boot flow.

BUG=b:237701972
TEST=Boots to OS
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I610966fd9d31581f15d8bcd51f8a116c27fd6311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66461
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07 19:55:36 +00:00
Jack Rosenthal ebd5be3f66 mb/google/brya/var/ghost: Pull EN_PP3300_TCHSCR high
This gets the display working.

BUG=b:240884260
BRANCH=firmware-brya-14505.B
TEST=display works in both depthcharge and linux

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I03edac865d68ef48e86d47a04f27ed84894f2f7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66395
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-07 19:55:19 +00:00