Commit Graph

54854 Commits

Author SHA1 Message Date
Subrata Banik 35348fc005 mb/google/rex: Avoid hang for pre-prod SoC by setting SAGV_POINTS_0_1_2
Intel has identified an idle hang issue on pre-prod silicon that will
not be fixed or root-caused. To avoid the issue, this commit sets
SaGvWpMask to SAGV_POINTS_0_1_2 in the devicetree.

Note: This change will affect system power.

BUG=b:287170545
TEST=Able to idle for more than 5+ hours without any hang on
google/screebo.

Change-Id: Id0b8db0076d983d336c3bec6d6c33614c69964d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78794
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01 04:15:45 +00:00
Curtis Chen 08db7cd0d0 soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKU
This commit adds power limit settings for 4+8 28W SOC sku and renames
MTL_P_682_CORE to MTL_P_682_482_CORE since they are sharing same 28W
settings.

BUG=b:306677879
TEST=boot on rex with 4+8 SOC and power limit settings are correct

Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78796
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-01 04:15:27 +00:00
Martin L Roth d599e89d4d Revert "vboot: Add catchall recovery reason for unspecified phase 4 errors"
This reverts commit 7499d96100.

Reason for revert: coreboot build fails

Change-Id: I8ef853d81ee9b1f18d36dfd82cdf687381ece2c6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78845
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-01 01:08:05 +00:00
Martin L Roth f87e766b5a Revert "Update vboot submodule to upstream main"
This reverts commit 6e03007bfa.

Reason for revert: Build fails - Jenkins test escappe.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78844
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-11-01 00:35:13 +00:00
Julius Werner 7499d96100 vboot: Add catchall recovery reason for unspecified phase 4 errors
The code for "phase 4" of firmware verification currently only sets a
recovery reason when there's an actual hash mismatch detected in
vb2api_check_hash_get_digest(). This is the most likely way how this
section of code can fail but not the only one. If any other unexpected
issue occurs, we should still set a recovery reason rather than just
reboot and risk an infinite boot loop.

This patch adds a catchall recovery reason for any error code that falls
out of this block of code. If a more specific recovery reason had
already been set beforehand, we'll continue to use that -- if not, we'll
set VB2_RECOVERY_FW_GET_FW_BODY.

Change-Id: If00f8f8a5d17aa113e0325aad58d367f244aca49
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78821
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31 22:47:41 +00:00
Julius Werner 6e03007bfa Update vboot submodule to upstream main
Updating from commit id 24cb127a:
2023-08-21 Nicholas Bishop sign_uefi_unittest.py: Fix long-line lint

to commit id f2b01bf0:
2023-10-27 Julius Werner   firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY

This brings in 47 new commits:
f2b01bf0 firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY
ef6d02df futility/vb2_helper: Add missing newline for error messages
886d13d7 PRESUBMIT: switch to cros format
ac2e1a75 host/lib: Decouple openssl headers from HOSTLIB
86ec05f7 futility: updater: Add help info for --quirks
2850244e futility: updater: Abort if the unlock_csme_* is used on a locked device
f1b5c88d devkeys: delete old unused firmware_bmpfv.bin
4444c5fe crossystem: Fix tpm_fwver for fwid < 12935
98ef339f 2lib: Prevent overwriting the value of fw_vboot2
c7517eb4 make_dev_ssd: support ChromeOS Kdump
8e3462cc tlcl: Increase the TPM_BUFFER_SIZE
740a2966 vboot_reference: Drop 'host' usage for 'internal' in flashrom.h
57877a44 vboot: Remove comments about physical dev switch
3401d16c 2lib: Fix typos, comments and formats
fdf52d45 scripts/: Drop deprecated {g,s}et_gbb_flags.sh scripts
bf76e9ee 2lib: Output the correct kernel_version
1ac4663e make_dev_firmware.sh: update pattern for matching wp status
c57ab9f7 2lib: Add recovery reason VB2_RECOVERY_WIDEVINE_PREPARE
e094ba31 tlcl: Reduce the variants of TPM2B
b047600d sign_official_build: support key config for pkcs11
f8712b73 vboot: support signing with pkcs11 private key
17fe786f strip_boot_from_image.sh: sfill fast
6c856cd3 futility/updater: Fix EC software write protection logic
1dc5a421 futility: update: Deprecate --unlock_me by --quirk unlock_csme_nissa
f0d88587 futility: update: Refactor the 'unlock ME' quirk(s)
81429ee9 futility: update: Do not update RO when the AP RO is locked
a3beb737 futility: update: Revise the ordering or quirks
2c1844fa futility: update: Remove unused quirk 'unlock_wilco_me_for_update'
75530d32 tests/futility: Test with new signer_config.csv based firmware updater
cba649fa 2lib: Expose 2hmac
ab015448 2lib: Refactor hmac to vb2_hmac_calculate
3545f8b4 Revert "sign_uefi: Remove exception catching"
55f625a9 dump_fmap: Add offset and size to flash_ec format output
a27ee336 keygeneration: add shellcheck source statements to help linting
055f9aa2 keygeneration: replace_recovery_key.sh: make minios key optional
6cb8ab60 scripts: delete unused values kernel command line
1f76c38b vboot: Drop phone recovery support
ccf6b037 scripts: Legacy fix for set_gbb_flags.sh
8f03069e futility: Add basic README.md
88963df8 utility: Query platform wp status with futility
6c3817d2 utility: Drop cros_alias technical debt in dev_debug_vboot
df85f512 scripts: Drop cros_alias technical debt in make_dev_firmware.sh
7395cd68 futility/updater_utils.c: Match on EC path to prepare for split
52518415 crossystem: Recover corrupted RW_NVRAM on flash writes
81f9ddaf futility/cmd_gbb_utility.md: Add basic GBB subcmd doc
c4995268 futility/: Fix define confusion
69dab5a6 crossystem: Avoid writing duplicate entries to RW_NVRAM
6c37b520 Revert "crossystem: stop supporting legacy chromeos_acpi driver"

Change-Id: Ic7ecd1755d26df349b8abf1c5a77c806facfe1d8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78820
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-31 22:47:34 +00:00
Richard Marko c821718ca7 util/kconfig: fix 0009-util-kconfig... patch
This was reverted via commit 9ab3a1fe4a and causes unapply to fail
so we adjust the patch to preserve the original return value.

Change-Id: I5ad2180854e0263d2d097b059cb16ec478b859c5
Signed-off-by: Richard Marko <srk@48.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78442
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31 17:06:38 +00:00
Richard Marko 3743811894 util/kconfig: Fix README.md formatting
Change-Id: I0c47a603cc6e6174cd4895ff9f44b5bc242c653e
Signed-off-by: Richard Marko <srk@48.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78441
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31 17:06:04 +00:00
Richard Marko 6bb4603ed6 util/kconfig: add savedefconfig patch to quilt
Adds commit 48ad5c23680c util/kconfig: chmod +w before savedefconfig
to quilt patch series.

Change-Id: I381dce2fee995227efc60169fd90ab505c99b74b
Signed-off-by: Richard Marko <srk@48.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78440
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31 17:05:40 +00:00
Richard Marko cec3a7bf92 util/kconfig: chmod +w before savedefconfig
This prevents a headscratcher when .config in root doesn't have a write
permission bit set which causes a build failure of savedefconfig
not able to write to copied file, for example

*** Error while saving defconfig to:
  build/mainboard/emulation/qemu-i440fx/cbfs-file.eU5E0t.out.tmp2

Change-Id: I2e7d35c9f6e8add3e7438d163850bc5fda5a99b2
Signed-off-by: Richard Marko <srk@48.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-10-31 17:04:57 +00:00
Matt DeVillier af46b4786f mb/google/brya/var/*: Mark fingerprint reader as hidden
Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.

TEST=build/boot Win11 on google/brya (kano), verify FPR does not show
up as unknown device under Device Manager.

Change-Id: Ie73fd9d448ecca9e9112abc0d92b4ab46ce3618d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-31 16:42:31 +00:00
Matt DeVillier 7065ea3487 mb/google/hatch/var/*: Mark fingerprint reader as hidden
Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.

TEST=build/boot Win11 on google/hatch (jinlon), verify FPR does not
show up as unknown device under Device Manager.

Change-Id: Ia4a908afdabad0ae8db45c4731a00c9cb17b42bb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-31 16:41:57 +00:00
Matt DeVillier b065e811bd soc/intel/cannonlake: Implement SoC sleep state array
Adapted from Alderlake implementation, modified as needed.
Device names missing from soc_acpi_name() were added as well.

TEST=build/boot Win11, Linux on google/hatch (akemi).

Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-31 15:06:27 +00:00
Matt DeVillier 1cbdb205d9 soc/intel/tigerlake: Implement SoC sleep state array
Copied from Alderlake implementation, modified as needed for Tigerlake.
Device names missing from soc_acpi_name() were added as well.

TEST=build/boot Win11, Linux on google/volteer (drobit).

Change-Id: I34999891ea0d386328698109b6315d481de7c43a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78521
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-31 15:03:28 +00:00
Varshit Pandya 6dba745cc8 mb/amd/onyx: Include soc.asl file
This patch includes the soc.asl from Genoa (SoC) folder,
which in-turn includes pci_int_def.asl

Change-Id: Id7a3b9c752546638f7b446510e17c44e9f10106d
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78496
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31 14:40:35 +00:00
Varshit Pandya 5397b4dcf2 soc/amd/genoa: Add PCI interrupt support
This patch adds PCI interrupt details as per the Processor Programming
Reference (PPR) version 0.25 (#55901), table 319.

Change-Id: I81251bd60aac1d7bd3181699d3adca315291f336
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78392
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-31 14:40:22 +00:00
Subrata Banik d581878264 mb/google/rex/var/screebo: Disable FVM
This patch disables FVM for IA and SA VRs as per the OEM requirement.

BUG=b:307237761
TEST=Able to build and boot google/screebo.

Change-Id: Icb0611331ac7090d11d646a5ad5201593a90aacb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-31 05:22:06 +00:00
Subrata Banik e4ac7b16ef mb/google/rex/var/screebo: Set Baseline Power Limit
This patch allows google/rex mainboard to choose between "Performance"
(PL_PERFORMANCE) and "Baseline" (PL_BASELINE) power limits (PLs).

This is important for platform to meet balance between power and
performance.

The OEM design google/screebo selects baseline power limit to maintain
the balance performance in lower power.

BUG=b:307237761
TEST=Able to build and boot google/screebo.

w/o this patch:

screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ]  CPU PL1 = 15 Watts
[INFO ]  CPU PL2 = 57 Watts
[INFO ]  CPU PL4 = 114 Watts

w/ this patch:

screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ]  CPU PL1 = 15 Watts
[INFO ]  CPU PL2 = 40 Watts
[INFO ]  CPU PL4 = 84 Watts

Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-31 05:21:40 +00:00
Jeremy Compostella 56178990be Documentation: Update 4.22 release notes with x86 CBFS cache support
Change-Id: I7c9ecdc3f8316fdec0bc1bc188f1959fb8b5a458
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78655
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 16:52:07 +00:00
Paul Menzel 274d509596 MAINTAINERS: Spell Jérémy’s name with accents
Change-Id: I4c025bbcb205fa5bd3dcb35c685a3db289a3f824
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78803
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 16:38:56 +00:00
Felix Singer 1b102cae36 mb/system76/adl/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I2f641ce1fc44a9d7c9f9c403d255997214021f47
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-10-30 14:01:12 +00:00
Felix Singer 983b169a36 mb/system76/rpl/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I15f326774850b3c9562f7eebb78f29430dec1031
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78667
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 14:00:59 +00:00
Felix Singer ee1fd54aef mb/system76/{tgl,skl}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 14:00:48 +00:00
Felix Singer d163253ba0 mb/system76/cannonlake/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I92414efc9ddb849ceb8b9c4f0bc564bdbd92773b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78638
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 14:00:37 +00:00
Matt DeVillier 1fd4d76043 mb/google/hatch/var/palkia: Use chipset devicetree references
Switch palkia overridetree to use chipset devicetree references.

Change-Id: Ic5fd2d139d22824d3ada09325022c37e69b5e2a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-30 13:48:38 +00:00
Matt DeVillier b0b659adf1 mb/google/hatch/var/nightfury: Use chipset devicetree references
Switch nightfury overridetree to use chipset devicetree references.
Drop USB port overrides which are identical to the baseboard.

Change-Id: I9bb028ad12b97fd4510f6d1026fdc16232c64dba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78570
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 13:44:10 +00:00
Matt DeVillier 690e255731 mb/google/hatch/var/mushu: Use chipset devicetree references
Switch mushu overridetree to use chipset devicetree references.

Change-Id: Iac05b0b2c5785f2cb69a29aa4d4c3088f164385f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-30 13:43:54 +00:00
Matt DeVillier 7f74f9de27 mb/google/hatch/var/kohaku: Use chipset devicetree references
Switch kohaku overridetree to use chipset devicetree references.
Drop USB port overrides which are identical to the baseboard.

Change-Id: Idcfde6882fc433e6a248aff6baf23b1a5bf7d201
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-30 13:43:45 +00:00
wuyang5 b621e08ed4 mb/google/corsola: Add new board 'Chinchou'
Add a new Krabby follower 'Chinchou'.

BUG=b:307161347
TEST=make # select Chinchou

Change-Id: Ic90f85621598ab253d3ec9fe44aa076712248223
Signed-off-by: wuyang5 <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78596
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-30 07:28:07 +00:00
Jeremy Compostella 66df100930 cbfstool: Fix CBFS header buffer overflow
In the unlikely but possible event where the name of the CBFS file is
longer than 232 characters, `cbfs_create_file_header()' would overflow
the buffer it allocated when it copies the CBFS filename.

Change-Id: If1825b5af21f7a20ce2a7ccb2d45b195c2fb67b0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-10-29 14:23:23 +00:00
Sumeet Pawnikar 3e57c57480 mb/google/brya/variants/craask: Enable DDR RFIM Policy for Craask
DDR interfaces emit electromagnetic radiation which can couple
to the antennas of various radios that are integrated in the system,
and cause radio frequency interference (RFI). The DDR Radio Frequency
Interference Mitigation (DDR RFIM) feature is primarily aimed at
resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies
for the Wi-Fi high and ultra-high bands (~5-7 GHz).
This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature
for Craask variant.
Refer to Intel doc:640438 and doc:690608 for more details.

BUG=None
BRANCH=None
TEST=Build and boot Craask.
- Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I5560bbedb26e88edd9d35f16b639fe63ef42c30e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-29 14:21:58 +00:00
Bill XIE c557847a9e mb/lenovo/t430: Disable SuperSpeed capabilities for WWAN USB
Just as in commit 38569d061099: ("mb/lenovo/{x230, x230s}: Disable
SuperSpeed capabilities for WWAN USB")

Although on ThinkPads with Panther Point PCH the usb port inside wwan
socket is usually wired to XHCI, it has actually no SuperSpeed lines,
so maybe it is okay to disable SuperSpeed capabilities, and wire them
to EHCI #2 by making use of XUSB2PRM and USB3PRM.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I61e61283a821686558f7f3fdfac7073bb3557e93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78680
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-29 14:21:02 +00:00
Arthur Heymans a6cfb336f2 payloads/LinuxBoot: Add uImage to clean target
uImages are generated for non-x86 arch.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Icb1184497087d66a7cc6fd27402365a028cc4eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-10-28 21:05:48 +00:00
Marx Wang be0e694fcf soc/intel/meteorlake: Expose In-Band ECC UPD config to mainboard
Meteor Lake has a UPD config called In-Band ECC(IBECC) which uses a part of the system DRAM to store the ECC information. There are a few UPD parameters in FSP-M to configure this feature as needed.

This patch adds code to expose these parameters to the devicetree so
that they can be configured on the mainboard level as needed.

Change-Id: Ice1ede430d36dff4175a92941ee85cc933fa56d5
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28 21:02:09 +00:00
Jeremy Compostella e68650a656 vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header file
Export Power State Current 1, 2 and 3 Threshold configuration entries.

BUG=b:308002192

Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-28 20:57:52 +00:00
Kane Chen 648ed149a1 mb/google/rex: add dptf settings for 2+4 SOC SKU
This patches privides settings based on 2+8 15w.

BUG=b:306543967
TEST=boot on rex with 2+4 SOC and power limit settings are overridden
correctly in variant_update_cpu_power_limits

Change-Id: I0560e44ce8e0d91bb5fb9c7cc9ffe68ab050bf00
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78688
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-28 20:57:09 +00:00
Kane Chen 6feb1de20a soc/intel/meteoerlake: Add power limits for 2+4 15W SOC SKU
This commit adds power limit settings for 2+4 15w SOC sku and renames
MTL_P_282_CORE to MTL_P_282_242_CORE since they are sharing same 15w
settings.

BUG=b:306543967
TEST=boot on rex with 2+4 SOC and power limit settings are correct

Change-Id: Id738303d1652f964142f8f27110426d6b84609bf
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78495
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 20:56:53 +00:00
Jeremy Compostella d4bf7211ca mb/google/rex/var/rex0: Configure EN_WWAN_PWR GPIO based on CBI
GPP_B17 (aka. EN_WWAN_PWR) should be kept low when the device does not
have a WWAN module.

TEST=Power consumption drops to 0 in S0iX

Change-Id: I95150c20c98b037a47827a7b83e4373c6e9070e3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78684
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-28 20:56:11 +00:00
Morris Hsu 0ec65daf7d mb/google/brya/var/dochi: Update overridetree for touchscreen
Update overridetree for ILI2901 and eKTH7B18U touchscreen.

BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot

Change-Id: Ib45f3c7c92ea525ca13a6137dd87eeb318f30384
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
2023-10-28 20:55:45 +00:00
Patrick Georgi 3d295a9afb util/cbfstool: Enable "ms-extensions" compiler flag on mingw only
The flag activates some Win32 compatibility quirks and on
clang/openbsd it enables so many of them that the code doesn't compile
anymore. Therefore move it into the "Win32 area" in that Makefile.

Change-Id: Ic77c04941e40a568f1d74cec09eb3d22a66e69b0
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78724
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 19:57:53 +00:00
Felix Singer 9a1b47e8a0 mb/{sm/x11,razor,libretrend}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.

While on it, remove superfluous comments related to modified lines.

Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28 18:42:46 +00:00
Matt DeVillier d5008a2e82 mb/google/zork: Clean up Kconfig entries
Alphabetize board entries, Kconfig selections, and config options.

Change-Id: I94e6e584809888fc9cab1b4cff6c0368803c1d47
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-10-28 18:30:15 +00:00
Matt DeVillier d59f9f6e69 mb/google/zork/Kconfig.name: Alphabetize board entries
Change-Id: I6843fd2eb752cd35d8c67ad7487f6dbb1c1afc62
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78707
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-10-28 18:29:58 +00:00
Matt DeVillier baa1d82322 mb/google/guybrush: Clean up Kconfig entries
Alphabetize board entries, Kconfig selections, and config options.

Change-Id: I599eda8c136d072471f022be9397faeb0e061472
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78706
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 18:29:33 +00:00
Matt DeVillier a05be2d1fb mb/google/guybrush/Kconfig.name: Alphabetize entries, add names
Alphabetize entries and add consumer product names for boards where
available.

Change-Id: I22a18ba85d6ff203765f984fba51784757a2a4df
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78705
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 18:29:22 +00:00
Matt DeVillier cea9415079 mb/google/skyrim: Clean up Kconfig entries
Alphabetize board entries, Kconfig selections, and config options.
Reverse default logic of PERFORM_SPL_FUSING for simplicity / clarity.

Change-Id: Ib25bb8c7bbf994f2f0675c4599c70a7db5d9f7ef
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-28 18:28:59 +00:00
Matt DeVillier 2a8c71c11b mb/google/skyrim/Kconfig.name: Alphabetize entries, add names
Alphabetize entries and add consumer product names for boards where
available.

Change-Id: I7459ee0a63025c12c7dbe75c578c7496c49fa475
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-28 18:28:41 +00:00
Nicholas Sudsgaard 9f5902f7e9 doc/lib/flashmap: Fix incorrect path to FMD implementation
Change-Id: I6864cd041d7173cd284f47d09f4388341a7ee756
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78690
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28 14:30:46 +00:00
Subrata Banik 8c4674ee37 mb/google/{rex, ovis}: Introduce devicetree.cb for pre-prod SoC
This patch introduces a dedicated devicetree.cb file for platforms
built with pre-production SoC. This will help to keep the SoC
configuration separate for platforms with ESx and QSx silicons.

For example, the SaGv WP configuration is different between
pre-production (aka ESx) and production (aka QSx) silicon.

BUG=b:306267652
TEST=Able to build and boot google/rex4es.

Change-Id: I01b0abeeb25ce5a83882c56b30929228fcc6c95c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
2023-10-28 05:40:52 +00:00
Matt DeVillier 830b0ac4e1 mb/google/hatch/var/*: Disable unused device in SerialIO cfg
For variants without a digitizer, disable I2C2.
For variants without a proximity sensor, disable I2C3.
For variants without a fingerprint reader, disable SPI1.
For all variants, disable I2C5 as it is unused.

Adjust comment blocks as needed.

Change-Id: I27e9eb2b0dcc869d1964c0b17c656d6691c0f05e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78553
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-27 23:38:07 +00:00