Commit Graph

50257 Commits

Author SHA1 Message Date
Arthur Heymans e095c462dc device/Kconfig: Don't allow native mode in x86_64
This option is not working so don't advertise it.

Change-Id: I910162756a567289b2484a5445360a3197ae848c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-14 15:54:09 +00:00
Arthur Heymans 6e85740236 arch/x86/Kconfig: Move AMD stages arch to common code
Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE
needs to be build as x86 stage.

Change-Id: I126801a1f6f523435935bb300f3e2807db347f63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-14 15:54:02 +00:00
Leo Chou 32882c97f9 mb/google/nissa/var/pujjo: Modify touch screen hid to ELAN901C
Modify touch screen hid for Pujjo board.

BUG=b:258586760
TEST=Use the value to boot on Pujjo successfully.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia3b374de8cba2125c478814a1890a4b6831715b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-14 01:37:23 +00:00
Kyösti Mälkki 987f46c276 arch/x86/mpspec.c: Drop weak write_smp_table()
Creating MP table is not useful when it does not include
the interrupt routing entries.

Change-Id: I1f38fb32a9436de64dfaf82e426cbd64b220ffa7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69489
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13 18:49:26 +00:00
Kyösti Mälkki ca5a793ec3 drivers/generic/ioapic: Drop poor implementation
This disables MP table generation for the affected boards
since interrupt routing entries would now be completely missing.

The mechanism itself is flawed and redundant. The mapping
of integrated PCI devices' INTx pins to IOAPIC pins is
dependent of configuration registers and needs not appear
in the devicetree.cb files at all.

The write_smp_table implementation would skip writing
any entry delivering to destination IOAPIC ID 0. This
does not follow MP table specification.

There were duplicate calls to register_new_ioapic_gsi0(),
with another present under southbridge LPC device.

Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13 18:48:52 +00:00
Kyösti Mälkki 9202cab661 mb/gigabyte/ga-945gcm-s2c,skl: Drop HAVE_MP_TABLE
The weak implementation of write_smp_table() is not useful
without DRIVERS_GENERIC_IOAPIC and related entries in
devicetree.cb. No interrupt routing entries are present
in the generated MP table.

Change-Id: I71a209e95ae1fe8c1c90b61c6ac0fb0e7bcc7eca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69490
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13 16:51:00 +00:00
Kyösti Mälkki e975e1bc6c mb/asus/p5gc-mx: Drop HAVE_MP_TABLE
The weak implementation of write_smp_table() is not useful
without DRIVERS_GENERIC_IOAPIC and related entries in
devicetree.cb. No interrupt routing entries are present
in the generated MP table.

Change-Id: Ib50a7656cef40d0d3ffcc408cc0858c1dae7b9e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13 16:50:51 +00:00
Marc Jones efdd3e8c7b acpi: Update default processor string from decimal to hex
Update the default processor sting from decimal to hex to increase
the default number of Processor NamedObjects from 100 to 256
ie: CP00-CP99 is now CP00-CPFF

This fixes MADT table generation for system up to 256 cores.

Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: Id60a39d99fa77d1d89ad655ddecdebcc8a422f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13 15:41:59 +00:00
Tim Chu 804c370d74 inc/dev: Add definitions for Link Capability and Slot Capability
Add definitions for Link Capability and Slot Capability and these
definitions may be used in smbios type 9.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Id66710d5569a7247d998cab20c2e41f2e67712cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13 15:41:21 +00:00
Matt DeVillier bfad0b0651 mb/google/zork: rename baseboard GPIO table getter for clarity
Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since
the GPIO table comes from the baseboard (and is not overridden by any
variant).

Drop the __weak qualifier as this function is not overridden.

This is similar to the change made for skyrim in CB:67809

Change-Id: Idd8ea3446ab7940b21265a3ed8080ba4029c4ff7
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69453
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13 15:38:12 +00:00
Matt DeVillier c3583173ec soc/amd/picasso: add mb_pre_fspm() definition and weak implementation
On newer AMD platforms, mb_pre_fspm() is used to set GPIOs in romstage
for PCIe reset (currently set in bootblock) and touchscreen power
sequencing (not yet implemented, but will be later in the patch train).

Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69452
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13 15:37:46 +00:00
Nicholas Chin 16fd5843a2 util/superiotool: Add SMSC MEC5035
Also comment out the SMSC FDC37M602 which has a conflicting
ID and has never had the LDN/register layout anyway.

Tested on a Dell Latitude E6400

Change-Id: I5b1900e6ef599c422a1d6eca7a2ac4691d56d874
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69481
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13 15:33:41 +00:00
Nicholas Chin 3d2a6f4956 util/superiotool: Add Nuvoton NCT6685D/NCT6686D
There doesn't seem to be a datasheet available for the NCT6685D, but
there is one for the NCT6686D. The 85D seems to return the same ID as
the 86D, and the registers do seem to be returning valid data other than
LDN 0xf which returns all 1s. The LDN and register layout appears to be
identical to the NCT6687D-W.

Tested on a Lenovo ThinkCentre M900 with a NCT6685D.

Change-Id: I4de0e7b86422a14ab9ccb15b7571597611d755d5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13 15:32:26 +00:00
Arthur Heymans 27c94b586c util/xcompile: Fix building for clang + 64bit
-malign-abi does not exist on clang (v15.0.0) and the -ccc-gcc-name
variable is not needed anymore.

TESTED: This also boots on qemu q35

Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-13 15:27:07 +00:00
Martin Roth e13b263ef3 mb/emulation/qemu: Move packed attribute
The jenkins build complains about this now that clang has been added.

src/mainboard/emulation/qemu-q35/cpu.c:37:1: error:
attribute '__packed__' is ignored, place it after "union" to apply
attribute to type declaration [-Werror,-Wignored-attributes]
__packed union save_state {

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id8faa24239505d808d09c00d825344edc7c4b7d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13 13:29:04 +00:00
Arthur Heymans 8855db9542 util/testing: Buildtest with clang
Some platforms correctly build and boot with clang. Add this to our CI.

Change-Id: I82d756e071a0e575db73fbd91167d27cae3ddc18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12 23:23:42 +00:00
Arthur Heymans 852ab75005 drivers/ipmi/ocp: Fix building with clang
Fix the following warning:
error: use of logical '&&' with constant operand
[-Werror,-Wconstant-logical-operand]

Change-Id: I9a2f03a0e05088a780ce1e829859421b461032ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69437
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12 23:23:02 +00:00
Arthur Heymans 9df0fee8fa arch/x86/memmove: Add 64bit version
The 64bit handles 64bit input variables properly.

TESTED: Both qemu and real hardware can use LZ4 properly which use this
code.

Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 23:22:17 +00:00
Mario Scheithauer bf89aaecfa soc/intel/elkhartlake: Enable 'scan_bus' on TSN GbE
For extern ethernet PHY access it is necessary to enable the 'scan_bus'
functionality.

Change-Id: I88050df2059ec7e0b27a132bca626eaef3d5dfb0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69385
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:16:42 +00:00
Sergii Dmytruk 7221a6cfc5 security/tpm: improve tlcl_extend() signature
Until now tcg-2.0/tss.c was just assuming certain buffer size and
hash algorithm. Change it to accept digest type, which the call sites
know.

Also drop `uint8_t *out_digest` parameter which was always `NULL`
and was handled only by tcg-1.2 code.

Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68745
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-11-12 23:16:07 +00:00
Tarun Tuli 3ff77016da mb/google/brya/var/agah: Add RPL Support to Agah
Enable RPL support for Agah.

BUG=b:258432915
TEST=build and boot ADL based Agah. RPL based testing
when hardware becomes available.

Change-Id: I5437dbf9e7812367a280d1ed659f286fb9b62a68
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69398
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:13:57 +00:00
Zheng Bao 5ca1343b5f amdfwtool: Add definition of instance for PSP entry
Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12 23:12:00 +00:00
Ivy Jian 06eb6946d0 mb/google/rex: Add Write Protect GPIO to cros_gpios
This will enable crossystem to access WP GPIO

BUG=b:258048687
TEST= wpsw_cur in crossystem reads the correct gpio

Change-Id: I67f4a57025064dbf8c691255b0abae9d3fa0dbd3
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69468
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:09:44 +00:00
Ren Kuo ea7c727a94 mb/google/brya/variants/volmar: Disable the unused FP pads
Disable the unused fingerprinter(FP) gpio for zavala by fw_config
FPMCU_MASK field.

BUG=b:250807253
TEST=build firmware and veriify the FP function on volmar DUT

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I0af1b7c3e4829ecab98525ead4f078c3eb6485d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69465
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:09:07 +00:00
Subrata Banik 93001ef9b7 mb/google/brya/var/marasov: Enable ISH driver and firmware name
BUG=b:234776154
TEST=Build and boot Marasov UFS, copy ISH firmware to host
file system /lib/firmware/intel/adl_ish_lite.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adl_ish_lite.bin loaded

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic53a3cbdf83825adc27f37877a14f4f405d4a5ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69377
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-12 23:07:38 +00:00
Subrata Banik 6f1a7b6720 mb/google/brya/var/marasov: Select ISH driver
This patch ensures that Marasov selects the ISH driver for
devices with UFS enabled.

BUG=b:256566011
TEST=Able to build Marasov.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I97a0aa3bc6976be32ddbf1fc6b37c16bb62a62e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69379
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-12 23:06:56 +00:00
Macpaul Lin 5d16f8d5b9 soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT
This replaces 'SPDX-License-Identifier' tags in all the files under
soc/mediatek/mt8195 for better code re-use in other open source
software stack.

These files were originally from MediaTek and follow coreboot's main
license: "GPL-2.0-only". Now MediaTek replaces these files to
"GPL-2.0-only OR MIT" license.

Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66625
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12 23:06:19 +00:00
Caveh Jalali 603de3f763 ec/google/chromeec: Deprecate dev_index from google_chromeec_reboot
This removes the dev_index argument from the google_chromeec_reboot
API. It's always set to 0, so don't bother passing it.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:01:47 +00:00
Caveh Jalali 675de7524c ec/google/chromeec: Simplify error handling for GET_VERSION
We don't need to check the lower level error code to determine if an EC
call succeeded. Simply check the return value of the call.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: Iaf0795b0c1a2df0d3f44e6098ad02b82e33c5710
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69372
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12 23:00:38 +00:00
Caveh Jalali 0bab8ed085 ec/google/chromeec: Simplify get_uptime_info error handling
google_chromeec_get_uptime_info() doesn't need to return an error code
from the lower level calls for the caller to interpret. It is more
appropriate to return a success/failure boolean.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: I3e27b8b4eed9d23e6330eda863e43ca78bb174a3
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69371
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12 22:59:28 +00:00
Martin Roth 60293e9b1f lib/ramtest.c: Update ram failure post code
coreboot already has a ram failure post code defined, but the ram test
functions weren't using it, and were using 0xea instead.
This changes those failures to display 0xe3, the value defined in
post_codes.h by POST_RAM_FAILURE.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I21ef196e48ff37ffe320b575d6de66b43997e7eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-11-12 22:53:14 +00:00
Martin Roth 9a8667a841 device & commonlib: Update pci_scan_bus postcodes
The function pci_scan_bus had 3 post codes in it:
0x24 - beginning
0x25 - middle
0x55 - end

I got rid of the middle postcode and used 0x25 for the code signifying
the end of the function.  I don't think all three are needed.

0x24 & 0x25 postcodes are currently also used in intel cache-as-ram
code.  Those postcodes should be adjusted to avoid conflicting.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 22:52:54 +00:00
Elyes Haouas 898176a24c treewide: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
Change-Id: I2a255cdcbcd38406f008a26fc0ed68d532e7a721
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12 18:00:16 +00:00
Elyes Haouas 7d67a19cfa util/amdfwtool/amdfwtool: Don't rewrite macros
Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12 17:59:20 +00:00
Arthur Heymans b291dc8776 nb/intel/ironlake: Work around unused variable warning
It's not clear whether this variable should actually be used or not so
leave it be with a FIXME comment.

Change-Id: I4892600bfec55830acae56d2b293947c2d9ddd07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69237
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 14:45:32 +00:00
Arthur Heymans e55aa0bc8f soc/intel/meteorlake: Fix set but unused variable
Clang complains about this.

Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 14:45:22 +00:00
Arthur Heymans d4dfc21f70 cpu/x86: Set thread local storage in C code
Doing this in C code is way easier to understand. Also the thread local
storage is now in .bss instead of the AP stack. This makes it more
robust against stack overflows, as APs stacks overflow in each other.

TESTED: work on qemu.

Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69435
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 14:23:51 +00:00
Arthur Heymans 407e00dca0 include/cpu/msr.h: transform into an union
This makes it easier to get the content of an msr into a full 64bit
variable.

Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68572
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 14:23:35 +00:00
Arthur Heymans 0c9fa6f2ce mb/emulation/qemu-q35: Fix running qemu-i386 with SMM
Depending on whether qemu emulates an amd64 or i386 machine the SMM
save state will differ. The smbase offsets are incompatible between
those save states.

TESTED: Both qemu-system-i386 and qemu-system-x86_64 (v7.0.50) have a
working smihandler, ASEG and TSEG.

Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 10:27:09 +00:00
Arthur Heymans 4c4bd3cd97 soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree
Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 08:56:18 +00:00
Kyösti Mälkki bd72bfece2 cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement
The disablement of SSE2 was not honoured since there is explicit
select under CPU_INTEL_MODEL_F2X. The removed commentary originates
probably from ROMCC romstage implementation.

Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69443
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 05:09:21 +00:00
Kevin Chiu 8e275af3ee mb/google/brya/var/gladios: Add GL9750 SD card reader support
BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12 03:34:58 +00:00
Kevin Chiu 02d4116fd6 mb/google/brya/var/gladios: Include GL9763E driver for eMMC support
Support GL9763E as a eMMC boot disk.

BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I2b29309615df381f1e24f29fc048c6f9bf216b7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69425
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 03:34:33 +00:00
Elyes Haouas 357c229173 sb/intel/i82801dx: Clean up includes
Change-Id: Ib8bfafe9b359856ccfb11a70ab5a6c1ffd453c54
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-12 03:33:14 +00:00
Michael Niewöhner 3504918b43 mb/clevo/l140mu: make use of the new clevo/it5570e ec driver
Hook up the new EC driver.

Tested:
 - Fn hotkeys work (brightness, display, volume, tp toggle, ...)
 - Display lid
 - Sleep/wake
 - Camera (including Fn toggle)
 - Bluetooth (both CNVi and PCIe card)
 - Wi-Fi (both CNVi and PCIe card)
 - CMOS options

Known issues:
 - Touchpad toggle needs OS setup; see CB:68791
 - UCSI is not implemented; see CB:68791

Change-Id: I6c4637936761cd62571b5d19fe2afd65560f49a0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59850
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 22:43:28 +00:00
Michael Niewöhner dc3e7def5f mb/clevo/l140cu: make use of the new clevo/it5570e ec driver
Hook up the new EC driver.

Tested:
 - Fn hotkeys work (brightness, display, volume, tp toggle, ...)
 - Display lid
 - Sleep/wake
 - Camera (including Fn toggle)
 - Bluetooth (both CNVi and PCIe card)
 - Wi-Fi (both CNVi and PCIe card)
 - CMOS options

Known issues:
 - Touchpad toggle needs OS setup; see CB:68791
 - UCSI is not implemented; see CB:68791

Change-Id: I28ac401ada2945bb58fe862895458b10fed505fe
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68795
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 22:43:14 +00:00
Michael Niewöhner d6ac7a9a3a mb/clevo/l140cu: drop System76 EC
Drop System76 EC, since the ODM board does not use it. Clevo EC FW
support will be added and hooked up cleanly in the follow-up changes.

Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59816
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 22:43:01 +00:00
Michael Niewöhner e1e65cb0f1 ec/clevo/it5570e: add driver for EC used on various Clevo laptops
This adds a driver for the ITE IT5570E EC in combination with Clevo
vendor EC firmware. The interface is mostly identical on various laptop
models. Thus, we have implemented one common driver to support them all.

The following features were implemented:
 - Basics like battery, ac, etc.
 - Suspend/hibernate support: S0ix, S3*, S4/S5
 - Save/restore of keyboard backlight level during S0ix without the need
   for Clevo vendor software (ControlCenter)
 - Flexicharger
 - Fn keys (backlight, volume, airplane etc.)
 - Various configuration options via Kconfig / CMOS options

* Note: S3 support works at least on L140CU (Cometlake), but it's not
        enabled for this board because S0ix is used.

Not implemented, yet:
 - Type-C UCSI: the EC firmware seems to be buggy (with vendor fw, too)
 - dGPU support is WIP

An example of how this driver can be hooked up by a board can be seen in
in change CB:59850, where support for the L140MU is added.

Known issues:

 - Touchpad toggle:
   The touchpad toggle (Fn-F1) has two modes, Ctrl-Alt-F9 mode and
   keycodes 0xf7/0xf8 mode. Ctrl-Alt-F9 is the native touchpad toggle
   shortcut on Windows. On Linux this would switch to virtual console 9,
   if enabled.  Thus, one should use the keycodes mode and add udev
   rules as specified in [1]. If VT9 is disabled, Ctrl-Alt-F9 mode could
   be used to set up a keyboard shortcut command toggling the touchpad.

 - Multi-fan systems
   The Clevo NV41MZ (w/o dGPU) has two fans that should be in-sync.
   However, the second fan does not spin. This needs further
   investigation.

[1] https://docs.dasharo.com/variants/clevo_nv41/post_install/

Testing the various functionalities of this EC driver was done in the
changes hooking up this driver for the boards.

Change-Id: Ic8c0bee9002ad9edcd10c83b775fc723744caaa0
Co-authored-by: Michał Kopeć <michal.kopec@3mdeb.com>
Co-authored-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Co-authored-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-11 22:42:46 +00:00
Sean Rhodes 064c6ced40 ec/starlabs/merlin: Rename the Cezanne EC code
This EC code is for the Byte, a Cezanne Mini PC. The EC is different
to the Cezanne StarBook Mk VI. Rename it to `-desktop`, so the laptop
variant becomes the primary.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I25f812cb1c6cefca1ebbe3bee5d20cf521dd60af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68319
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 18:24:45 +00:00
Felix Held 9405dd066e drivers/intel/fsp2_0/hand_off_block: remove unneeded line breaks
Since the characters per line limit was increased from 80 to 96, some
line breaks can be removed to improve code readability.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I92aa3fec8c8caba143e418efc999ec4a7c5d93c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69461
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-11 18:02:37 +00:00