Add support for UAO AC only mode.
Needs tests on all platforms.
Change-Id: Ib52aab427ff687b00129024cde65b78060d21e32
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The thinkpad-acpi driver uses the UCMS (CMOS) ACPI method to control the
ThinkLight from the Operating System. This patch adds partial support for
that method, enough to enable or disable the ThinkLight:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
With the original BIOS the UCMS method exposes a wide range of values
through a generic /proc/acpi/ibm/cmos interface. With the changes suggested
in this patch that interface is also exposed but only accepts the commands
to enable or disable the ThinkLight; all other commands are ignored.
This change would potentially benefit all currently supported Thinkpad
models, I only have an X201 available for tests though.
Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/19644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The AFC—Additional Flash Control Register is set by
southbridge code.
Remove redundant calls and get rid of it in autoport.
Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19493
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static and empty ASL file.
Delete src/drivers/pc80/tpm/acpi/tpm.asl.
Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.
Change-Id: I88b5ef8e12ac606751952a493f626e1b146e98f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.
Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18274
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This driver to configure the clock generator is not used.
Change-Id: I156a42dfc336ff45acdcb6d8618bbd12671b66a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18104
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17676
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
USB AO is the internal name for the dedicated charging port on
ThinkPads when in S3 or lower.
AOEN (bit 0) is internal name for enabling this feature while AOCF
(bits 2 and 3) is the configuration field. According to Peter Stuge,
AOCF can be configured in this way:
00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off
11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off
10, 01 => equivalent to 00
This commit also adds a new configuration field in the CMOS of the
X220 and the X201 to activate this feature. It probably can be also
added to all the ThinkPads that support this functionality.
With this functionality USB devices are able to negotiate full power
from the dedicated port (usually the yellow one) even in S3.
Tested on a X201 and X220 with an Android smartphone: with this
feature enabled it shows "Charging" when connected during S3, without
it it shows "Charging slowly" (or it doesn't charge at all on the
X201).
For some reasons the "AC only" mode doesn't work, so it has been
disabled.
Change-Id: Ie1269a4357e2fbd608ad8b7b8262275914730f6e
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/17252
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The h8s needs around 3s to respond to ps2 commands
Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16505
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.
To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).
Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Also, fix up the following driver subdirectories by switching
to the src/drivers/[X]/[Y]/ scheme as these are hard requirements
for the main change:
* drivers/intel
* drivers/pc80
* drivers/dec
Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14047
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
power_on_after_fail=Enable in cmos.default leads to wake on AC behaviour
on mobile systems. Therefore set cmos.default entry to "Disable" in order
to improve user experience.
Change-Id: I977a4e6bc028c8c4c7fc1c2f5fdd74a59e951c60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/13884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Use shared gpio code from common folder.
Bd82x6x's gpio.c and gpio.h is used by other southbridges
as well and will be removed once it is unused.
Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The century byte is used by most RTC (default 0x32@nvram).
Even the century byte can disabled via ACPI it's more safe to reserve
it's space. Because some RTC will act with that byte anyhow.
Some OS overwrite it when syncronize the RTC.
Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/11853
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
According to the ACPI Spec for CondRefOf, the result argument is
optional. In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL. Since it's
an optional argument, just remove it.
dsdt.aml 22: if(CondRefOf(\_OSI,Local1))
Warning 3144 - ^
Method Local is set but never used (Local1)
Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If any path in a method returns a value, IASL expects that all paths
within that method will return a value.
Presumably the MKHP method wouldn't get called unless there were a
pending event, but if no event is found, return a zero.
Fixes IASL warning:
dsdt.aml 1785: Method (MHKP, 0, NotSerialized)
Warning 3115 - ^ Not all control paths return a value (MHKP)
This was the only IASL warning in most lenovo mainboards.
Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12517
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We've actually got more warnings now than when I first tested IASL
warnings as errors. Because of this, I'm adding it with the option
to have it disabled, in hopes that things won't get any worse as we
work on fixing the IASL warnings that are currently in the codebase.
- Enable IASL warnings as errors
- Disable warnings as errors in mainboards that currently have warnings.
- Print a really obnoxious message on those platforms when they build.
***** WARNING: IASL warnings as errors is disabled! *****
***** Please fix the ASL for this platform. *****
Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The last_boot NVRAM option was deprecated and removed in
commit 3bfd7cc6. Remove the last_boot option from all
affected mainboards to eliminate user confusion.
Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12316
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.
Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Only one value would work with corresponding gma code currently (which one
depends on board). Going forward, it's possible to compute which number can
be used, so there is no need to keep this info around.
Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11862
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on the info by Felix Held.
Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11857
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
timestamp table.
Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The default route does work for all Chromebooks and is replaced
with platform-specific one in follow-up.
Change-Id: Ia1839ed38dacf44a89dc757394d054e17666f193
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10442
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.
Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9598
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
PS/2 emulation is part of H8, so should be inited in relevant files.
Change-Id: Ie873ea7f6f88f68f622351799462d0b000d17585
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10348
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Old igd.asl had inconsistent addresses (between _DOD and actual device)
and ghost devices. Any of those is enough to make brightness on windows
fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous
copying of the same thing 6 times per chipset. Leave only hooking up and
chipset-specific part in chipset directory. Move NVS handling and ACPI-spec
parts to a common file.
Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7472
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
This allows to deactivate TPM on X201.
Change-Id: Ic085db6cc2c57668e7a4fdbc7440735c806cc256
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10278
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
SLIT and SRAT are created this way only on amdk8 and amdfam10.
This saves the need of having a lot of dummies.
Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7052
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Without this some radios may remain operational. They may consume power but
the immediate demonstrable effect is wireless LED still being on.
Coreboot will reenable radios on resume or poweron.
Change-Id: I9fcb08880964b1594f779a246840bc3013a44afe
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10190
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Move the GPI interrupt routing selection between SMI/SCI from
mainboards to southbridge. There is speculation if this is all
just legacy APM stuff that could be removed with a followup.
Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7967
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb)
programming to use GPI1 between SCI/SMI modes, while
previous programming was for GPI12.
Change-Id: I3ac0feaa1d10c8f0e53a5fa5af72366503bb5d2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To simplify browsing the "Supported hardware" list, I added Release year
for the hardware from asus, asrock, gigabyte, msi, via, tyan, intel,
lenovo, apple, jetway and hp. Still several models and manufacturers to
add information to. This is more of a proof-of-concept.
The "Release year" will be shown in the wiki page.
Change-Id: I6bc14ed06ac7c6b3c9f054b49f08cb9b3dc47947
Signed-off-by: Mathias Friman <mathias@workplays.se>
Reviewed-on: http://review.coreboot.org/9963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This change switches all mainboard vendors and mainboards
to be autoincluded by Kconfig, rather than having to be mentioned
explicitly.
This means, vendor and mainboard directories are becoming more
"drop in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree mainboards / components
to be built with a given coreboot version (given that the API did
not change)
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a
Reviewed-on: http://review.coreboot.org/9295
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
x201 has 2 sata ports. 1 port for hard drive and 1 port for the dock.
Tested on x201 with hdd in port 1 + cdrom in port 2.
Change-Id: I1ee8c547392257d4f2e00a5d48e21447a84f79c0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8657
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
