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Author SHA1 Message Date
Subrata Banik
b4a169a1e1 soc/intel/alderlake: Add option to make MRC log silent 
Typically, FSP-M aka MRC debug log level defaults to `3`
meaning prints all `Load, Error, Warnings & Info` messages.

Sometimes it's too much information to parse even when users
aren't required to have such detailed information hence,
implement `fsp_map_console_log_level()` that maps coreboot console
log level to FSP-M debug log level and suppress verbose MRC debug
messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and
then the user can enable `DEBUG_RAM_SETUP`.

TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP`
and user to select `DEBUG_RAM_SETUP` config to override
`SerialDebugMrcLevel` UPD value to '5' aka verbose.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2022-01-03 15:07:00 +00:00
Subrata Banik
346bb0b010 soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode 
Since TGL `spi_protection_mode` bit replaces the previous
`manufacturing mode` without changing the offset and purpose
of this bit.

This patch renames to `manufacturing mode` aka `mfg_mode` to
maintain the parity with other PCHs as part of IA-common code.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6d00f72ce7b3951120778733066c351986ccf343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2022-01-02 12:29:07 +00:00
Subrata Banik
e065db0dc2 soc/intel/common/blk/crashlog: Drop some new lines 
Remove unnecessary new lines in crashlog code.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0920f563d6fdf9414eab86796cedcac83173dba3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-01-02 12:17:50 +00:00
Felix Singer
f424c8b80f soc/intel/tigerlake/fsp_params.c: Use is_dev_enabled() 
Change-Id: I3e79f637bedec0bdca1312291328b2385bd027a7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
 2022-01-01 22:24:31 +00:00
Elyes HAOUAS
b7ec42d2ff src: Use 'stdint.h' when appropriate 
Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-01-01 14:58:44 +00:00
Elyes HAOUAS
8292f4160a src: Remove duplicated includes 
Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-01-01 14:56:42 +00:00
Elyes HAOUAS
b23571c18e src: Drop duplicated includes 
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>,
<stdbool.h>, <stdint.h> and <stddef.h> headers.

Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-01-01 14:55:51 +00:00
Felix Singer
c104e4cdd7 soc/intel/apollolake/acpi: Replace Decrement() with ASL 2.0 syntax 
Replace `Decrement (a)` with `a--`.

Change-Id: I523c6b14c127ec7c0eb41078fb2eb92f42d74bd5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2022-01-01 14:22:39 +00:00
Simon Yang
355fb2fb98 soc/intel/jasperlake: Add CdClock frequency config 
Add a devicetree setting to configure the CdClock (Core Display Clock)
frequency through a FSP UPD. Because the value for this UPD's default
setting is non-zero and devicetree settings default to 0 if not set,
adapt the devicetree values so that the value for the UPD's default
setting is used when the devicetree setting is zero.

Also update the comment describing the FSP UPD in the header file
FspsUpd.h to match the correct CdClock definition.

BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log

Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-01-01 14:19:53 +00:00
Felix Singer
c8c312c7e8 soc/intel/apollolake/acpi: Replace Increment() with ASL 2.0 syntax 
Replace `Increment(a)` with `a++`.

Change-Id: I40d5df41e2e077cb9d3e7f3945f0dbae18382a28
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2022-01-01 14:09:14 +00:00
Felix Singer
a330382db4 soc/intel/apollolake/acpi: Replace Divide(a,b) with ASL 2.0 syntax 
Replace `Divide (a, b)` with `a / b`.

Change-Id: Ifb377f0abb50a736aa3aa53a11d45bee65488c4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60569
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-01-01 14:01:51 +00:00
Felix Singer
3dc8f56a18 soc/intel/apollolake/acpi: Replace Multiply(a,b) with ASL 2.0 syntax 
Replace `Multiply (a, b)` with `a * b`.

Change-Id: I42076d361045c224b99e111e34de7539420b8a52
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2022-01-01 14:00:25 +00:00
Felix Singer
3d3d498e8f soc/intel/cannonlake/acpi: Replace Multiply(a,b) with ASL 2.0 syntax 
Replace `Multiply (a, b)` with `a * b`.

Change-Id: I6dc9f57773754e89df4b4ffd088a4693af0452e3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2022-01-01 14:00:12 +00:00
Rex-BC Chen
0069f6a18c soc/mediatek/mt8186: Add support for regulator VRF12/VCN33 
To provide power to PS8640, the eDP bridge IC on krabby, add control
of VRF12 and VCN33 to set voltage from MT6366.

TEST=measure 1.2V from VRF12 and 3.3V from VCN33.
BUG=b:210806060

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I55a9ca16e1e335e9355d0a1b30c278a9969db197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2022-01-01 03:29:08 +00:00
Felix Singer
f3c313b47c soc/intel/apollolake/acpi: Replace Add(a,b) with ASL 2.0 syntax 
Replace `Add (a, b)` with `a + b`.

Change-Id: Id465558f054494d3273d5cd6077476d878d7c183
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60504
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-12-31 09:01:42 +00:00
Felix Singer
d190cdd25e soc/intel/cannonlake/acpi: Replace Add(a,b) with ASL 2.0 syntax 
Replace `Add (a, b)` with `a + b`.

Change-Id: I90dc0ecb1e3f16874a72cdf01afb097d4e7b6076
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60503
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-12-31 09:00:52 +00:00
Felix Singer
4fd000193b soc/intel/skylake/acpi: Replace Add(a,b) with ASL 2.0 syntax 
Replace `Add (a, b)` with `a + b`.

Change-Id: Id35c24663f529238fe17721b99ad8e93a4f5433f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2021-12-31 09:00:25 +00:00
Felix Singer
f94ec24eb9 soc/intel/apollolake/acpi: Replace Subtract(a,b) with ASL 2.0 syntax 
Replace `Subtract (a, b)` with `a - b`.

Change-Id: I3b0ee96b5a1e9bf242efc14a24f745fd8ba0cd97
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2021-12-31 08:57:38 +00:00
Felix Singer
1bdac6a8e7 soc/intel/apollolake/acpi: Replace Add(a,b,c) with ASL 2.0 syntax 
Replace `Add (a, b, c)` with `c = a + b`.

Change-Id: I4d6039affd9688a2e795d69f699d5baf688ba2e4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2021-12-31 08:55:43 +00:00
Felix Singer
3a8f0875c0 soc/intel/cannonlake/acpi: Replace Add(a,b,c) with ASL 2.0 syntax 
Replace `Add (a, b, c)` with `c = a + b`.

Change-Id: Ibc5aeb5e8d85556d7564033ec92deb5b2dae093d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2021-12-31 08:50:43 +00:00
Felix Singer
2c670870fd soc/intel/apollolake/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntax 
Replace `Subtract (a, b, c)` with `c = a - b`.

Change-Id: I8c98f4e3c3aed6209fd36398134a36778a560708
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2021-12-31 00:23:36 +00:00
Felix Singer
a6fe3f82a8 soc/intel/cannonlake/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntax 
Replace `Subtract (a, b, c)` with `c = a - b`.

Change-Id: I764bf6c8b068c1b7471a28aa064f7a3a47d7811e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2021-12-30 23:54:40 +00:00
Felix Singer
53b6c206e5 soc/intel/cannonlake/acpi: Replace LAnd() with ASL 2.0 syntax 
Replace `LAnd (a, b)` with `a && b`.

Change-Id: I259bd218ac3f786cef6e05386f6dc55ccaf6b911
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60468
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-12-30 16:27:28 +00:00
Felix Singer
5e0fc511fd soc/intel/apollolake/acpi: Replace LAnd() with ASL 2.0 syntax 
Replace `LAnd (a, b)` with `a && b`.

Change-Id: I4bbbc4888fc134b3862bb956b2ee17a72f282584
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60466
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-12-30 16:24:33 +00:00
Subrata Banik
0cd553b3df soc/intel/alderlake: Fix incorrect comment about debug consent 
This patch makes the debug consent for ADL comment default value
comment proper. Default `Platform Debug Consent` value is
2: Enabled (Al probes and tracehub.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic5eeb4f02d051dc1efba2deaecb51cbc7eac51f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-12-30 15:24:11 +00:00
Felix Singer
da20fa7abc soc/intel/skylake/acpi: Use ASL 2.0 syntax to access arrays 
Replace Index(FOO, 1337) with FOO[1337].

Change-Id: I3bc780a60e34fb72020d8dbba3db0ed096fa930d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2021-12-30 14:30:53 +00:00
Rex-BC Chen
d67de90708 soc/mediatek/mt8186: Add DSI driver 
Enable DSI for display.

BUG=b:209930699
TEST=Firmware display looked good

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-12-29 07:53:12 +00:00
Rex-BC Chen
783e2bff53 soc/mediatek/mt8186: Add DDP driver 
Add DDP (display controller) driver that supports main path to
eDP panel. The output goes to display interface DSI.

BUG=b:209930699
TEST=saw firmware display

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic4fb40832b5dc7a815b37266259b2e3281ee79f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-12-29 07:52:35 +00:00
Ryan Chuang
31531eab35 soc/mediatek/mt8186: Add DRAM full calibration support 
Use common SoC drivers for DRAM calibration support.

TEST=build pass.
BUG=b:202871018

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
 2021-12-29 07:46:00 +00:00
Ryan Chuang
773c007af4 soc/mediatek/mt8186: Add header files to support DRAM calibration 
Remove emi.h because emi.h is defined in common/include/soc.
Add dramc_param.h and dramc_soc.h to prepare for implementation of
DRAM full calibration.

TEST=build pass.
BUG=b:202871018

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If8662ed43088ea5aa1fe6cb5b2c4bda2338c4387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-12-29 07:45:26 +00:00
Yu-Ping Wu
f8f5062430 soc/mediatek: Prevent passing NULL MIPI commands 
Previously (before CB:56965 [1]) mtk_dsi_send_init_command() would
ignore NULL initialization commands passed to it. However, in the
current code mipi_panel_parse_init_commands() doesn't check that (see
CB:57150 [2]), so we should check it on the caller side from
mtk_dsi_init().

[1] b2a1480191 device: Move MIPI panel library from
               mainboard/google/kukui into common
[2] 4757a7ea33 mipi: Make panel init callback work directly on DSI
               transaction types

BUG=b:202871018, b:209930699
TEST=emerge-corsola coreboot
BRANCH=none

Change-Id: I8196e3b135da273325e2e121523abb7fb230a49c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
 2021-12-28 09:36:42 +00:00
Rex-BC Chen
db01d1e2fc soc/mediatek/mt8186: Enable VRF12 software control for MT6366 
PS8640 is a low power MIPI-to-eDP video format converter.

VRF12 does not provide power to PS8640 on krabby.
In original patch, VRF12 is not used, and is set to hardware control
for low power. We change the setting to remove hardware control.
Therefore, if we want to control VRF12 by software, we can control
it directly.

BUG=b:210806060
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-12-28 09:34:34 +00:00
Runyang Chen
a0583a46b9 soc/mediatek/mt8186: Add devapc basic drivers 
Add basic devapc (device access permission control) drivers.

DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.

1. Initialize devapc.
2. Set master domain and secure side band.
3. Set default permission.

BUG=b:202871018
TEST=build pass

Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-12-28 09:34:07 +00:00
Rex-BC Chen
800b24f7f7 soc/mediatek/mt8195: Move some definations of devapc to common folder 
Move some definations of devapc for sharing between MT8195 and MT8186.

BUG=b:202871018
TEST=emerge-cherry coreboot; emerge-corsola coreboot;

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia1769ede790f106a320ead9be7e2a596fe96930a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-12-28 09:33:35 +00:00
Rex-BC Chen
32992f264f soc/mediatek/mt8186: Adjust usage of SRAM L2C 
We use parts of SRAM_L2C as the memory of PRERAM_CBMEM_CONSOLE before
DRAM calibration. When we check cbmem, we found the content of this
memory is unreadable.

The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM
has configured only half of L2/L3 cache as SRAM. Therefore, decrease
the size of each SRAM region to fit into the first half of the cache.

BUG=b:207725851
TEST=Bootblock log looked good in `cbmem -c`

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-12-28 09:32:56 +00:00
Rex-BC Chen
f371a78d90 soc/medaitek/mt8195: adjust USB phy shift value 
There is a design issue of bit shift which will drop a bit for
USB3 phy on MT8195. Therefore, we add this patch to set USB phy
registers from value of efuse.

BUG=b:211528577
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Tested-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-12-26 10:05:22 +00:00
Angel Pons
d45b113fb5 soc/intel/{skl,cnl}: Guard USB macro parameters 
Add parentheses around the parameter of the `USB_PORT_WAKE_ENABLE`
macro to prevent unintentional operator precedence problems.

Change-Id: I61fbacc129cbfb42ade7e64ee40cd07c98d87683
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2021-12-26 10:03:41 +00:00
Sridhar Siricilla
b647e35119 soc/intel/alderlake: Add timestamp for cse_fw_sync 
The patch add timestamp around cse_fw_sync().

TEST=Verified on Brya, cbmem -t:

 948:starting CSE firmware sync		1,381,577 (45,227)
 949:finished CSE firmware sync		1,459,513 (77,936)

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
 2021-12-23 14:42:28 +00:00
Scott Chao
baf027d50c soc/intel/alderlake: remove SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS 
This causes the I2C touchpad device to stop working after warm reboot.

BUG=b:210701402
BRANCH=none
TEST=after warm reboot, the touchpad still works.

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I106ddc96c3185656d3f1fbcd45f198d2d46f3f4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60126
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-12-22 15:40:25 +00:00
Rob Barnes
4454c9af3c soc/amd/cezanne: Correct S0i3 verstage softfuse bit 
PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40.

BUG=b:202397678
BRANCH=None
TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP.

Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
 2021-12-20 17:52:50 +00:00
Curtis Chen
b89c798ddc soc/intel/common: Do not trigger crashlog on all resets by default 
Crashlog has error records and PMC reset records two parts. When we
send ipc cmd "PMC_IPC_CMD_ID_CRASHLOG_ON_RESET", PMC reset record is
enabled. At each warm/cold/global reset, crashlog would be triggered.
The cause of this crash would be "TRIGGER_ON_ALL_RESETS", it is used to
catch unknown reset reason. At the same time, we would see [Hardware
Error] in the kernel log.

If we default enable TRIGGER_ON_ALL_RESETS, we would have too many false
alarm. Now we disable PMC reset records part by default. And we could
enable it when we need it for the debug purpose.

The generated bert dump is under /var/spool/crash/, we could check this
path to verify this CONFIG disable/enable status.

BUG=b:202737385
TEST=No new bert dump after a warm reset.

Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-12-20 17:49:53 +00:00
Felix Held
aed38a94e3 soc/amd/common/lpc/espi_util: use enum cb_err type for return values 
Use enum cb_err as return type of all remaining functions that only
return success or failure.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6cff8480d99641fdfb613bb3e4edc4055ad5efc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-12-20 17:40:52 +00:00
Felix Held
4b4114f709 soc/amd/common/lpc/espi_util: use enum cb_err type for return values 
Use enum cb_err as return type of all functions that aren't exposed
outside of this compilation unit. The checks if a function has returned
a failure are replaced with checks if the return value isn't CB_SUCCESS
which is equivalent if only those two values are used, but also detects
a failure if any unexpected value would be returned.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-12-20 17:40:32 +00:00
Felix Held
9e830540ec soc/amd/common/lpc/espi_util: simplify espi_configure_decodes 
The intermediate ret variable isn't needed. espi_open_generic_io_window
only returns 0 or -1, so if ret is != 0, it has to be -1. This is a
preparation to use the enum cb_err type for the return values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6c7f4cedf8c2defadcf4c4da1697a97c7b401f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-12-20 17:40:07 +00:00
Felix Held
d992aa6111 soc/amd/common/lpc/espi_util: simplify espi_get_general_configuration 
The intermediate ret variable isn't needed.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-12-20 17:39:46 +00:00
Felix Held
bad64c8b9b soc/amd/cezanne/fch: disable 48MHz output in S0i3 
S0i3 is a low power state which reduces the power consumption to about
the level of the S3 suspend state where the DRAM is kept in a self-
refresh state and most of the rest of the system is powered down. So
everything that can be switched off in the S0i3 state should be switched
off in order to maximize the standby time.

BUG=b:210722314

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If445f5825dc7b795c95d73c061156cc485421ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-12-20 17:39:29 +00:00
Felix Held
ea6ee07f43 soc/amd/stoneyridge/fch: add GNVS-related TODOs 
The AOAC device states shouldn't be stored in GNVS, but be read from the
AOAC registers during runtime. Same for the EHCI controller's BAR0. The
location and size of the XHCI firmware can either be statically
determined at build-time or have coreboot generate ACPI objects that
contain the needed addresses. Since I can't easily test changes that
require booting to a desktop on Stoneyridge at the moment, only add
TODOs for now.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I3691b05606b9430cb60923780a6131993a9887d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-12-20 17:38:54 +00:00
Felix Held
2d020e1cc3 soc/amd/stoneyridge: split southbridge code 
Split the southbridge code into a bootblock and a ramstage part to align
it more with Picasso and Cezanne. Also move the implementation of
fch_clk_output_48Mhz to the end of early_fch.c since it's not really
related to the functions that were previously around it.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-12-20 17:38:43 +00:00
Felix Held
25aa5606c2 soc/amd/stoneyridge: factor out AGESA-wrapper related FCH functions 
Split the code that gets called from the AGESA wrapper from the rest of
the FCH/southbridge code that directly interacts with the hardware.
Since the remaining parts of southbridge.c aren't used in romstage,
drop it from the list of build targets for romstage.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6197add0e1396a82545735653110e1e17bf9c303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-12-20 17:38:12 +00:00
Felix Held
fbfb906081 soc/amd/stoneyridge: factor out early AOAC initialization 
Factor out enable_aoac_devices out of southbridge.c to aoac.c to align
Stoneyridge more with Picasso and Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied4d821138507639cad1794f6c5017b5873b761f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-12-20 17:37:59 +00:00