As discused earlier, the callback name 'mb_adjust_cfg' was considered
too generic. The new naming is chosen to be consistent with other
drivers' callback names designed to be used at mainboard level.
Also other functions, namely 'mb_get_edid' and 'mb_select_edid_table'
are renamed accordingly.
BUG=none
TEST=Builds for siemens/mc_apl{1,4,5,7} and siemens/mc_ehl boards
complete successfully.
Change-Id: I4cbec0e72e5f03e94df0faa36765d1a6cd873a7a
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch adds base code for the Protectli VP2420. The GPIO
config has been extracted with inteltool from the stock
firmware and then parsed with intelp2m. As of now, the platform
runs with edk2 with no apparent issues.
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
CXL (Compute Express Link) [1] is a cache-coherent interconnect
standard for processors, memory expansion and accelerators.
CXL memory is provided through CXL device which is connected
through CXL/PCIe link, while regular system memory is provided
through DIMMs plugged into DIMM slots which are connected to
memory controllers of processor.
With CXL memory, the server's memory capacity is increased.
CXL memory is in its own NUMA domain, with longer latency
and added bandwidth, comparing to regular system memory.
Host firmware may present CXL memory as specific purpose memory.
Linux kernel dax driver provides direct access to such differentiated
memory. In particular, hmem dax driver provides direct access to
specific purpose memory.
Specific purpose memory needs to be represented in e820 table as
soft reserved, as described in [2].
Add IORESOURCE_SOFT_RESERVE resource property to indicate (memory)
resource that needs to be soft reserved.
Add soft_reserved_ram_resource macro to allow soc/mb code to add
memory resource as soft reserved.
[1] https://www.computeexpresslink.org/
[2] https://web.archive.org/web/20230130233752/https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.32&id=262b45ae3ab4bf8e2caf1fcfd0d8307897519630
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52585
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
BUG=b:270529665
TEST=Verify the build and boot on Rex board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I0e3d3312c546a2a468fb906a08b8d3ec3e96c46a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
To support 32M flash, the non-vboot also need to split amdfw. Just as
the deleted comment says, we need this feature now.
This is one of series of patches to support 32/64M flash.
BUG=b:255374782
Change-Id: Ic058cfaeebd1a947227cfa9be2db4eb22702aa28
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
To support 32M flash, the non-vboot also need to split amdfw.
The amdfw.rom is the default filename added to CBFS.
Keep the default filename and then we don't have to change all the
CBFS definition.
This is one of series of patches to support 32/64M flash.
BUG=b:255374782
Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Hook up microcode from 3rdparty repo for:
- 06-b7-01 (CPUID signature: 0xb0671)
Verified microcode blob was in CBFS on Clevo PD50SNE (system76/serw13),
which has an i9-13900HX.
Change-Id: If91ff9233a5e1dd1db76edf33a76c55f5dddc9b4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie3493af340a42035ee537d83b1542be1b87d8f9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE.
Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when
body detection changed between lap/desk mode. However, that event is a
wake event, which resulted in spurious AP wake events being triggered
when the EC detected lap/desk mode changes while the AP was suspended.
To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was
added, which will not be a wake event. This CL adds handling for the new
event to acpi/ec.asl to switch DPTC tables when a change is detected.
BRANCH=none
BUG=b:261141172
TEST=bodydetectmode on|off, verify host event is received
Change-Id: Iabeb7891489a209f45504804355f1fa817082976
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
There were two wrong comments in all mc_ehl gpio.c files. This patch
corrects the incorrect comments.
Change-Id: Iea356db177227d89b91be32a4e2367c612b77350
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72458
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard does not use security features like TPM.
Change-Id: Ieebbf12fc844573ffadb089da78062dd2033517a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The upcoming mc_ehl4 variant is the first Siemens Elkhart Lake mainboard
without a TPM. For this reason, the corresponding Kconfig switches must
be moved to variant level. To prevent Jenkins build from complaining,
the TPM is removed in the following patch.
Change-Id: Ic73ccd1b52e57c1cf1dd7337b0e28beaadbece8e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Measurements have shown that the automatic calibrated values for RGMII
output impedances are too low. For this reason, set the PMOS value to 16
and the NMOS to 13.
Change-Id: Ic3382889d3281faccb03819f9680a9763703b2a1
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73019
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the configuration of Marvell PHY 88E1512 is finished, then switch
the page back to 0 only once at the end of the Init function.
Change-Id: I9e516870a7c5928724df2bd3ac9c5c8f3249af2e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73017
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This mainboard is based on mc_ehl1. In a first step, it contains a copy
of mc_ehl1 directory with minimum changes. Special adaptations for
mc_ehl4 mainboard will follow in separate commits.
Change-Id: I3c1f2cf4a3dcae58895f6d14a7fce46b2825e6ba
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72427
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit fcff39f0ea ("vc/siemens/hwilib: Rename 'maxlen' to
'dstsize'") changed the 'dstsize' input parameter type from uint32_t to
size_t.
This patch changes also the return parameter, which is often directly
compared with the aforementioned input parameter value. This should
introduce no change on 32-bit builds and stay consistent across the
project in the case of 64-bit builds and avoid comparisons of integers
of different width here.
BUG=none
TEST=No changes to hwilib behavior on any of the siemens/mc_apl1 or
siemens/mc_ehl variants.
Change-Id: I0a623f55b596297cdb6e17232828b9536c9a43e6
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add a new parameter STT_ALPHA_APU' for each DPTC mode.
BUG=b:257149501
BRANCH=None
TEST=Check if the STT value matches the expected setting.
Change-Id: Ib27572712d57585f66030d9e927896a8249e97a7
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Add a new flag "--utc" to allow the user to choose if
elogtool should print timestamps in Local Time or in UTC.
It is useful for generating automated crash reports
including all system logs when users are located in
various regions (timezones).
Add information about timezone to timestamps printed
on the console.
Signed-off-by: Wojciech Macek <wmacek@google.com>
Change-Id: I30ba0e17c67ab4078e3a7137ece69009a63d68fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
With the latest hardware revision, the two GPIOs GPP_B15 and GPP_E19 are
no longer connected to a native function.
BUG=none
TEST=Checked output verbose GPIO debug messages
Change-Id: I266612f041b749aa83b366497b4211fc075c7bd7
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The Common Clock Configuration (CCC) is a PCIe feature for cases where
the upstream and downstream device of a link share the same reference
clock. After a change in this setting a link re-training is mandatory
to make it effective.
On recent Intel platforms (tested on Elkhart Lake) the FSP code which is
executed before coreboot performs the PCI scan already enumerates all
PCI buses for its internal uses. While this is done, all the PCI express
features of a link are configured, which includes CCC. If the link
supports common clock, FSP performs the link re-training already. When the
execution flow is returned to coreboot, the same link treatment is
applied again (coded in 'pciexp_tune_dev()') and CCC is enabled a second
time, just a few milliseconds after FSP did this already.
Because enabling CCC requires a link re-training, there are two link
re-trainings on the PCIe link within a few milliseconds (one from the FSP
code and one from coreboot) which can lead to issues with a connected
PCIe device on this link. In particular, link issues were discovered
with a Pericom PCIe switch (PI7C9X2G608) on mc_ehl1 where the link has
stalled for a while after the second re-training. This in turn leads to
non-initialized PCI devices on the bus after coreboot has finished.
This patch checks if CCC is already enabled on a link and does not
perform the steps to enable it again in coreboot which safes a link
re-training (and thus execution time) and a potential link stability
issue.
Test=Check log output on mc_ehl1 which shows the following lines:
[DEBUG] PCI: pci_scan_bus for bus 09
[DEBUG] PCI: 09:00.0 [8086/1533] enabled
[INFO ] PCIe: Common Clock Configuration already enabled
Change-Id: I747fa406a120a215de189d7252f160c8ea2e3716
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73310
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The instructions and actual menu got a bit out of sync, or
were just inaccurate. This fixes the notes on the payload.
Change-Id: I22d6588ef3708e98a8fd9b0652b3f827ff9ff698
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Add the support LP5 RAM parts for rex:
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 3 (0011)
BUG=b:270708359
TEST=emerge-rex coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id0925ccec014c9c535178ed3d908e60889df624d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add the support LP5 RAM parts for rex:
DRAM Part Name ID to assign
H58G56BK7BX068 1 (0001)
BUG=b:270708359
TEST=emerge-rex coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9eea7e277628992be9b7768a678a50425444002a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The DRAM scramble feature enhances DRAM data protection. When it's
enabled, the written DRAM data will be scrambled and hence can prevent
the data from being hacked.
This feature would make debugging more difficult (for example ramoops
would be lost after reset). Therefore, add a new config to allow
enabling or disabling the feature from coreboot, without having to
maintain two versions of the DRAM calibration blob.
BUG=b:269049451
TEST=build pass and check scramble enable or disable successfully
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: Ib4279bc1cc960fae9c9f5da39f4448a5627288d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Fast VMode makes the SoC throttle when the current exceeds the I_TRIP
threshold.
TEST=FW_NAME=constitution emerge-brask coreboot
Change-Id: I1e68f708b7740567e24f8a3ddb9832aeec7ee6b5
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73247
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Pablo Ceballos <pceballos@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The DC boost bit was intended to be in the Controller Params word rather
than its own byte. Correct this error.
BUG=b:214581372
TEST=build
Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73216
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Server platform doesn't have S4 state so select DISABLE_ACPI_HIBERNATE
to remove S4 state from available sleepstates.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ie5ddb1a98cd5bbd854b915c93694d1ebcb9bddd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
The currently used panel type could work with 500 ms but increasing
the value to 1 second allows to use a wider range of LVDS LCD panels,
as many of them specify the delay of 1 s as minimum.
BUG=none
TEST=Test link stability using a panel with minimum re-power delay of
1 s.
Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this GPIO to 1 or 0 will not change the HDA
GPIO configuration; it will make the sound work when set to 1,
or not work when set to 0.
Remove the incorrect comment and make the UPD configurable from the
devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with
the D3COLD_SUPPORT symbol, as it allows for more granular control.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This filling does not need to be done separately.
Change-Id: I53051349923dce40f4fc3f747ab41a93a3798823
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
A few references to "--combo-capable" were left after commit 4bfb36ed68
Change-Id: I6f425db2a8b86d7ad928baee6bc7b07e5190ba37
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73281
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the EFS data is being packed, the pointer should be at EFS
header.
After that, it should be at body location.
TEST=binary identical test on amd/birman amd/chausie amd/majolica
amd/gardenia pcengines/apu2 amd/mandolin
Change-Id: Ia81e2bdf9feb02971723f39e7f223b5055807cd8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Instead of adding the P-state number to the PSTATE_0_MSR number to get
the P-state MSR number for the rdmsr call, provide a macro that directly
calculates the MSR number for a given power state. Also drop the unused
PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs
available in the hardware.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The latency values in the _CST package override the values in the
p_lvl2_lat and p_lvl3_lat FADT fields. In Picasso, Cezanne, Mendocino,
Phoenix and Glinda generate_cpu_entries generates the _CST packages for
each CPU device. The coreboot code for Stoneyridge doesn't generate _CST
packages for the CPU objects, but those are provided via the PSTATE SSDT
binaryPI generates and agesa_write_acpi_tables gets and adds to the ACPI
tables. The AGESA reference code also sets those two FADT entries to the
equivalents of ACPI_FADT_C2_NOT_SUPPORTED and ACPI_FADT_C3_NOT_SUPPORTED
so this also matches the AGESA behavior.
From the ACPI 6.4 spec: "Values provided by the _CST object override
P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT."
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1116a3013576b18b6f521604d6b0a9d75b971e0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Use the ACPI_SCI_IRQ definition for both the PIC and APIC IRQ number in
the fch_irq_map table. Before the PIC mapping was set to PIRQ_NC, but
both mb/google/kahlee and the other amd mainboards using newer SoCs set
both the PIC and APCI IRQ number to ACPI_SCI_IRQ, so change this here to
match the other mainboards.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I29dde7ca8d2ecf00d8174c2d793ef1ad55ae3e28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73322
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the ACPI_SCI_IRQ definition instead of a magic value.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia860668b5c93b1b8882459d9f983cf3a23d16392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73321
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IRQ9 is used as ACPI SCI IRQ, so add a define for that and use it in the
code like it is also done in the other SoCs in soc/amd.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddb51d70c15ab1d7088f62b61e22510bd1b30b1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73320
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there's a define for the ACPI_SCI_IRQ 9, use the define instead of
a magic number in the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23c8f62929f3f66192698e10826d10329ef3d8cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73319
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FADT data structure is zero-initialized in acpi_create_fadt which
then calls the SoC-specific acpi_fill_fadt function, therefore it's not
needed to assign 0 to the res2 FADT field in acpi_fill_fadt.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa69ae61bea82acf66e7210c4103ef48e36dbdd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73318
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use enum cb_err to return an error/success state instead of an int in
get_nv_rdev and get_nv_rdev_rw.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I73706a93bc1dbc8556e11885faf7f486c468bea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73317
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The bool type is used although stdbool.h isn't included. Include types.h
which will include both stdint.h and stdbool.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5213ddae3ceb36e0b2e09f8ef3f7f414ebdf187f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73316
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The directory holds boards other than ADL-P, such as ADL-U and ADL-H.
Change-Id: I8e1b67f83d649cd07645a4a519ba1bf2f6f5e7c6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
We need to considering the case the EFS header is given as a relative
address and the other, body location, is given as an absolute one. So
we convert both of them to relative and check the validation.
For relative address case, the location should be between
0 and data size.
Change-Id: I7898bfbca02f5eb1c0fb7c456dc1935bddf685b1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
If ctx.address_mode is "physical", it will keep as "physical".
If ctx.address_mode is "relative to table", it will be changed as
"relative to BIOS".
Because the "current table" is the whole flash, the code worked well.
TEST=Binary identical test on amd/birman amd/chausie amd/majolica
amd/gardenia pcengines/apu2 amd/mandolin
Change-Id: I9acb54cc5de149d8a705bb05bf351c44b7d3ced1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or
overridden by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Port of commit a182faeb88 ("soc/intel/alderlake: Hook up FSP hyper-threading setting to option API")
Change-Id: I0b3e1a4049312c6b1ec950382c92274e0350001f
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Fix typo in the comment for Common Clock Configuration.
Change-Id: Idd01e787458a9090d53b9a57547b8158480dcc16
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Enable HAS_RECOVERY_MRC_CACHE config and add RECOVERY_MRC_CACHE FMAP
section to cache the MRC training data in recovery mode.
BUG=b:270569389
TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS
directory entry is populated with the appropriate MRC_CACHE FMAP
section.
Change-Id: I3f0f41c20b61c96473e887521f84f3ad240adc2b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Jan Samek