CPUs with CPUID level >= 0x80000008 can return
the number of physical address bits.
Change-Id: I1c0523b6a091c476af838d173ed9030280360d7f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/599
Tested-by: build bot (Jenkins)
Moved the conditional compilation out of the source file
Change-Id: Ic4045006f39d70f4a0bc37d1bd5e073ed8477c68
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/578
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There was no good way to extract the build version from an image.
This change will be mostly backward compatible: The only assumption
that could break is that the board name string ends directly before
the 3 dwords that represent .id's "header".
Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/537
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.
Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It's only used in cbfs_and_run.c
Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/273
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
The previous code does a full flush of the uart after every character.
Unfortunately, this can cause transmission delays on some serial
ports.
This patch changes the code so that it does a flush at the end of
every printk instead of at the end of every character. This reduces
the time it takes to transmit serial messages (up to 9% on my Asrock
e350m1 board). It also makes the transmission time more consistent
which is important when performing timing tests via serial
transmissions.
Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-on: http://review.coreboot.org/90
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
example.
This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- shift most (romcc) code out of console.h into arch/x86/lib/romcc_console.c
- rename arch/x86/lib/printk_init.c to .../romstage_console.c
- drop FUNCTIONS_FOR_PRINT since __console_tx_* are already functions, so there
should not be any side effects to eliminating another indirection.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The cmos.default code wasn't actually used so far, due to an oversight
when forward-porting this feature from an old branch.
- Extend walkcbfs' use by factoring out the stage handling into C code.
- New sanitize_cmos() function that looks if CMOS data is invalid and
cmos.default exists and if so overwrites CMOS with cmos.default data.
- Use sanitize_cmos() in both bootblock implementations.
- Drop the need to reboot after writing CMOS: CMOS wasn't used so far,
so we can go on without a reboot.
- Remove the restriction that cmos.default only works on CAR boards.
- Always build in cmos.default support on boards that
USE_OPTION_TABLE.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- actually hook up usbdebug in printk/print_ for romstage
- make usbdebug.c more similar to the Linux kernel version it was
originally derived from.
- increase retries and timing for usbdebug init (at least one chipset
seems to need this)
- src/pc80/usbdebug_serial.c is not needed
- some small console cleanups
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/arch/x86.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
