Commit Graph

5030 Commits

Author SHA1 Message Date
Uwe Hermann 55dc223ccd Factor out common mptable code to mptable_init().
- Drop sig[], oem[], and productid[] fields in all mptable.c files, no
   longer needed. The sig[] is always the same ("PCMP"), the oem[] is
   currently also always the same ("COREBOOT"), and productid is being
   passed into mptable_init() directly as string now.

 - LAPIC_ADDR is passed in as parameter, too. While at the moment it's
   always the same value that is passed in, the LAPIC base address could
   also be relocated theoretically, so keep it as parameter for now.

 - Fix a few productid entries, they were (partially) incorrect:

   - DK8S2 (was "DK8X", copypaste)
   - 939A785GMH (was "MAHOGANY", copypaste)
   - X6DHE-G (was "X6DHE", incomplete board name)
   - H8DME-2 (was "H8DMR", copypaste)
   - H8QME-2+ (was "H8QME", incomplete board name)
   - X6DHE-G2 (was "X6DHE", incomplete board name)
   - X6DHR-iG2 (was "X6DHR-iG", incomplete board name)
   - GA-M57SLI-S4 (was "M57SLI", incomplete board name)
   - KINO-780AM2 (was "KINO", incomplete board name)
   - DL145 G1 (was "DL145G1", small fix as per vendor website)
   - DL145 G3 (was "TREX", wrong board name)
   - DL165 G6 (was "HP DL165 G6", drop vendor)
   - S2912 (was "S2895", copypaste)
   - VT8454c (was "VIA VT8454C", drop vendor, lower-case "c")
   - EPIA-N (was "P4DPE", copypaste)
   - pc2500e (was "PC2500", incorrect name)
   - S1850 (was "S2850", copy-paste)
   - MS-7135 (was "MS7135")
   - MS-9282 (was "MS9282")
   - MS-9185 (was "MS9185")
   - MS-9652 (was "K9ND MS-9652")
   - Ultra 40 (was "ultra40")
   - E326 (was "E325", copypaste)
   - M4A785-M (was "TILAPIA", copypaste)
   - P2B-D (was "ASUS P2B-D", drop vendor)
   - P2B-DS (was "ASUS P2B-DS", drop vendor)

 - Adapt the mptable utility to use mptable_init() too.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-25 15:32:07 +00:00
Peter Stuge 11abcc0ae5 Make ectool -i work; add missing break
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-25 02:12:04 +00:00
Scott Duplichan 7c1fb7b798 Running a checked build of Windows is needed for understanding its various BIOS related BSODs. Win7 checked build complains when running coreboot+seabios:
FADT revision inconsistent with length.
     Revision:        0x1
     Length:          0xf4
     Expected Length: 0x74

Change the FADT revision from 1 to 3 to match its length and prevent the Windows checked build assert.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-24 16:22:11 +00:00
Uwe Hermann 7015989464 Add small comment about LDN 5 on F71872F/FG / F71806F/FG.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-24 14:19:09 +00:00
Jonathan Kollasch 760498f8ea Fix superiotool build on non-NetBSD x86_64.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-24 14:18:55 +00:00
Jonathan Kollasch 51ac8382dc Provide for I/O space access on NetBSD.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-24 14:10:35 +00:00
Idwer Vollering 3f91d813ef Add inteltool support for FreeBSD.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-24 13:50:13 +00:00
Idwer Vollering a4d77dc74d Update superiotool support for FreeBSD, Makefile fixes.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-24 13:42:32 +00:00
Jonathan Kollasch d74c7748aa Teach superiotool about the registers in a Fintek F71806 (and F71872).
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-24 12:43:41 +00:00
Uwe Hermann 1c009276f1 Revert sblk/sblink change, use sblk like the rest of the codebase does.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-20 20:21:27 +00:00
Myles Watson fa78d998d5 Now that no boards set RAMBASE < 1M, get rid of some dead code. Trivial.
It's probably time to reconsider moving all fam10 boards to RAMBASE = 1M.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-20 19:23:22 +00:00
Scott Duplichan bda153be73 For AMD family 10h processors, msr c0010058 is always programmed
for 256 buses, even if fewer are configured. This patch lets msr
c0010058 programming use the configured bus count, CONFIG_MMCONF_BUS_NUMBER.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 21:08:11 +00:00
Jonathan Kollasch 115e66018a Drop duplicate SB_HT_CHAIN_ON_BUS0 in Kconfig for MS-7135.
Trivial.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 15:25:06 +00:00
Jonathan Kollasch 6f566b7a60 Use the correct (W83627THF, not W83627HF) superio code in MS-7135 romstage.
This is consistent with the device tree and the chip actually on the board.
Trivial.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 15:17:18 +00:00
Jonathan Kollasch 4e6f4cfa9c Copy ICH4 hard_reset() for 6300ESB.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 14:02:10 +00:00
Jonathan Kollasch 7b8700b502 Remove unused variables from 6300ESB smbus_write_block().
#ifdef DEADCODE out smbus_write_byte() and smbus_write_block() as
they are static and nothing uses them or are incompletely implemented.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 13:49:11 +00:00
Jonathan Kollasch 9fe5069584 Correct spelling of "spacing" (in comments).
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 13:39:38 +00:00
Jonathan Kollasch d208c1aa2c Use mptable_write_buses().
Remove unhelpful comment.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 13:11:56 +00:00
Jonathan Kollasch 6b0ade7550 Modernize socket_754 Kconfig with CAR and address bits information.
Also, update the board that uses this socket to match.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 13:03:34 +00:00
Scott Duplichan 1ba2eee2b4 Revision 5966 changed the end of line style of the 3 modified files. This change restores the original end of line style.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 04:58:49 +00:00
Scott Duplichan 236aef238f To reduce boot time, remove the double startup IPI and 10 ms delay from lapic_cpu_init.c. The change is
currently restricted to recent model AMD processors, though it could be applied to others after successful testing.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 04:36:42 +00:00
Scott Duplichan af786b618d When debug logging is enabled, a message such as '* AP 02 timed out:02010501'
is sometimes logged. The reason is that the AP first sets a completion value
such as 0x13, which is what function wait_cpu_state() is waiting for. Then a
short time later, the AP calls function init_fidvid_ap(). This function sets
a completion value of 01. When logging is off, wait_cpu_state is fast enough
to see the initial completion value for each of the APs. But with logging
enabled, one or more APs may go on to complete function init_fidvid_ap, which
sets the completion value to 01. While mostly harmless, the timeout does
increase boot time. This patch eliminates the timeout by making function
wait_cpu_state recognize 01 as an additional valid AP completion value.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 04:26:17 +00:00
Scott Duplichan d7acdfb44a This patch enables SB700 option PrefetchEnSPIFromHost in early setup.
It affects only systems booting from SPI flash, not those booting from
LPC flash. By default, the SB700 reads dwords from the SPI flash chip.
Setting PrefetchEnSPIFromHost causes the SB700 to read entire cache
lines from the flash chip. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 04:01:12 +00:00
Stefan Reinauer c104cb0d9d update intel microcode files.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 00:21:39 +00:00
Uwe Hermann 321ebe0953 Make update-microcodes.sh executable.
This also has an additional benefit:

I was running "sh update-microcodes.sh" previously which broke with

  update-microcodes.sh: 102: Bad substitution

due to the script requiring /bin/bash instead of /bin/sh (uses bash-specific
stuff). Running "bash update-microcodes.sh" works fine.

Making the script executable in svn reduces the likelyhood of people
running the script with differing shells that may not work.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 00:20:40 +00:00
Uwe Hermann d453dd0c4d Cosmetics and coding style fixes in devices/*.
- Whitespace and indentation fixes in various places.
 
 - Fix various typos.
 
 - Use u8, u16 etc. everywhere.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 00:00:57 +00:00
Stefan Reinauer a600a3f700 update intel microcode update script
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 23:55:17 +00:00
Keith Hui a14b117269 Removes model_65x CPUIDs from model_6xx code.
They now have their own home at cpu/intel/model_65x.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 22:07:08 +00:00
Liu Tao 676d0298a1 In the RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set
to zero, so for boards with RS780 not on CPU's HT chain 0, the function will
mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3()
function will hang when it visits the MMIO.

The following patch fixes the problem, and is tested on a K8 board with RS780
on HT chain 1.

Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 21:59:43 +00:00
Liu Tao dfecd2740b We currently read the CPU HT speed from HT chain 0's register.
Fix that to read the register from the chain where the SB chip is on.

Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 21:34:45 +00:00
Uwe Hermann c6a106286b Add more missing GPL-headers, fix inconsistencies in others.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 19:30:58 +00:00
Uwe Hermann 8af6d5574b Use common GPL-header format in CK804 files, add missing ones (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 19:13:18 +00:00
Uwe Hermann c1ee429135 Various Doxygen comment fixes, typo fixes, etc.
- Fix incorrect argument names for @param entries.

 - Add missing @param and @return entries, partly as TODOs.

 - s/@returns/@return/, that's a typo.
 
 - Small whitespace fixes while I'm at it.
 
 - Drop useless @brief commands, they just clutter the comments and make them
   harder to read. Doxygen has an option to always use the first sentence
   of a Doxygen-comment as @brief automatically (should be on per default).
   
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 19:01:48 +00:00
Keith Hui b14fb6abd6 Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory.
abuild-tested. I have no Deschutes CPUs to boot test this with.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-16 08:45:31 +00:00
Uwe Hermann af8b2b91b4 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.
This CAR implementation hardcodes the Cache-as-RAM base address to:

  0xd0000 - CacheSize

so the DCACHE_RAM_BASE is never actually used for this implementation
and these sockets.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-15 07:47:51 +00:00
Uwe Hermann e49903650c Cosmetics in ioapic.c (trivial, no functional changes).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-14 23:40:10 +00:00
Uwe Hermann 212d0a2eae Remove various .c #includes from Intel i810/i82801ax/i82801bx boards.
This is pretty much the same mechanism as in r5929.

 - Use 'romstage-y' to turn i82801ax_early_smbus.c and i82801bx_early_smbus.c
   into distinct compilation units, and don't #include the files anymore
   in romstage.c files.

 - Ditto for northbridge/intel/i82810/raminit.c, and
   northbridge/intel/i82810/debug.c.

 - Add various header files which are now needed, drop unused includes.

 - Make functions that need to be visible non-static.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 23:00:41 +00:00
Keith Hui 6529c2a717 Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.
abuild-tested. Boot tested on P2B-LS.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 17:00:42 +00:00
Uwe Hermann ab50d62ea6 Convert all Intel i810 boards to CAR.
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff.

 - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the
   usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables.

 - In socket_PGA370/Makefile.inc add:
   cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

 - Other smaller related fixes.

Abuild-tested and boot-tested on MSI MS-6178.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 08:21:44 +00:00
Peter Stuge 51eafdeae6 Enable or disable the power button in Kconfig
Some mainboards need to disable the power button to avoid turning off
right after being turned on, while other boards ship with a jumper over
the power button and should allow the user to configure the behavior.

This adds infrastructure in the form of four mutually exclusive options
which can be selected in a mainboard Kconfig (power button forced on/off,
and user-controllable with default on/off) and one result bool which
source code can test. (Enable the button or not.)

The options have been implemented in CS5536 code and for all mainboards
which select SOUTHBRIDGE_AMD_CS5536, but should be used also by other
chipsets where applicable. Note that if chipset code uses the result
bool ENABLE_POWER_BUTTON, then every board using that chipset must
select one out of the four control options in order to build.

All touched boards should have unchanged behavior, except
pcengines/alix1c, traverse/geos and lippert/hurricane-lx where the
power button can now be configured by the user.

Build tested for alix1c, alix2d, hurricane-lx and wyse-s50. Confirmed
to work as advertised on alix1c both with button enabled and disabled.

Includes additional traverse/geos changes from Nathan and
lippert/hurricane-lx changes from Jens to correctly use the new
feature on those boards.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 06:23:02 +00:00
Zheng Bao f2573bd237 Fix a stupid bug in rs780 and rs690 code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 05:16:48 +00:00
Zheng Bao 89122856e0 Trivial. Clean up code and add some comments.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 02:46:59 +00:00
Keith Hui 5e9c1cd693 Add missing include of model_6bx for slot_1.
I could no longer boot my P3B-F with my Tualeron and r5938. Dies with
"unknown CPU". I believe it will happen with any Slot 1 440BX boards
that supports model_6bx CPUs.

I need to make the change below to make it work. abuild tested. Boot
tested on P2B-LS and P3B-F.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 23:22:08 +00:00
Uwe Hermann f1aa9841a9 Move translate_spd_to_i82810[] from .h to .c file (trivial).
This is in preparation of further i810 fixes and switching it to CAR.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 21:37:03 +00:00
Uwe Hermann 74d1a6e8a1 We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 17:34:08 +00:00
Warren Turkal 4ffde94c4e Reduce duplicate definition in CAR code.
Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.

I also added a few macros to the amd mtrr.h to make the MSR naming more
consistent.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 06:13:40 +00:00
Warren Turkal 9c814d2e9e Build bootblock.S instead of bootblock.c.
The file is actually just including a bunch of assembly. The build rule
for bootblock.c even states that the file will be "assembler-with-cpp."

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 06:12:00 +00:00
Sylvain Hitier 5b2fd1ea15 Fix typo after r5925.
BTW, embed the always-the-same string instead of referencing it through "%s".

Do the same for i82371EB while we're at it.

Signed-off-by: Sylvain Hitier <sylvain.hitier@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11 23:22:24 +00:00
Uwe Hermann e62fc0d355 Build fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11 22:49:39 +00:00
Uwe Hermann 0ea281f700 First round of ICH2/ICH2-M cleanups after split from i82801xx.
- Drop all non-ICH2 "struct pci_driver" entries from all files.

 - Kconfig: Add missing USE_WATCHDOG_ON_BOOT.

 - Drop i82801bx_sata.c and i82801bx_usb_ehci.c, ICH2 doesn't have SATA/EHCI.

 - Simplify lots of code, getting rid of i82801xx remainders.

 - Use u8 et al (instead of uint8_t) in a few more places.

 - Use #defines from header files where possible.

 - Various other fixes and updates.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11 21:38:49 +00:00