Commit Graph

33380 Commits

Author SHA1 Message Date
Nico Huber 0f6f70c394 Makefile.inc: Adapt $(spc) definition
GNU Make 4.3 is more picky about the $(spc) definition. It seems, the
variable ends up empty. The old definition worked for nearly 8 years,
RIP.

Tested with GNU Make 4.2.1 and 4.3.

Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38790
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-12 21:20:12 +00:00
Nico Huber 1c08a9a9c4 Makefile.inc: Use `define` for cbfs-files-processor-defconfig
The body contains a `#` and GNU make 4.3 disagrees with earlier versions
if it should be treated as a comment. Turn it into a `define` which has
clearer semantics regarding comments (interpretation is supposed to be
deferred until the variable is expanded).

Change-Id: I589542abbd14082c3ecc4a2456ebd809fb6911ea
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38793
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-12 20:07:21 +00:00
Nico Huber cccb2d76c5 arch/arm64/Makefile.inc: Avoid # in variable definition
Interpretation if # starts a comment inside a variable definition varies
between GNU make versions. Use a wildcard to match the first # and use
`sed` instead of `grep | cut` to avoid unbalanced quoting chars.

Tested with GNU make 4.2.1 and 4.3. Both produce the same output as
4.2.1 did before the patch.

Change-Id: Ib7c4d7323e112968d3f14ea0590b7dabc57c9c45
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-12 20:07:04 +00:00
Elyes HAOUAS 65718760fa crossgcc: Upgrade IASL to version 20200110
Changes:
  20200110: https://acpica.org/node/176
  20191213: https://acpica.org/node/175
  20191018: https://acpica.org/node/174
  20190816: https://acpica.org/node/172

Change-Id: Ifaa0d1c79802872c1a822c1108d2a50bc60c8fd8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38347
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-12 19:48:58 +00:00
Patrik Tesarik 5aa043b800 doc/tutorial/part1.md: Add commands for yum- & pacman-based distro
* Add additional information on non-debian cli tools
* Improve spellings and descriptions to the best of my knowledge

Adding info about needed tools in other distribution's package
managers was requested at the coreboot beginner's workshop at 36C3.

Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237
Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-12 18:45:31 +00:00
Patrick Rudolph 5a62427e14 nb/intel/sandybridge/acpi: Fix MMCONF size computation
Calculate the correct MMCONF size, which was only correct for
256MiB, but not for smaller values.

Tested on HP Z220:
Fixes "Not using MMCONF" warning in dmesg.

Change-Id: I986681126637c28f6442ab7c34acea5bb58ea3d2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
2020-02-12 18:37:44 +00:00
Patrick Rudolph 516f0acbb0 nb/intel/sandybridge/acpi: Update PEG code
* Use new ACPI syntax
* Return either 0 or 0xf for PCI root port. That will make the
  device show up in Windows. This might help users and possibly
  Windows drivers working with PCIe ports.

Change-Id: I1e76b735ab1472f6a4ea493c733cd6b2e6fca29e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-12 18:37:15 +00:00
Sridhar Siricilla 3d27705d27 soc/intel/{skl, common}: Move ME Firmware SKU Types to common code
1. Move ME firmware SKU types into common code.
2. Define ME_HFS3_FW_SKU_CUSTOM SKU.

TEST=Verified on hatch & soraka.

Change-Id: Iaa4cf8d5b41c1008da1e7aa63b5a6960bb9a727b
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-12 06:13:08 +00:00
Johanna Schander f538d74e9c vendorcode/intel: Remove Ice Lake FSP Bindings
By updating the FSP submodule we now got all FSP headers from within
that repo. This commit changes the default paths to use these and
fixes some include paths to allow the usage of
vendorcode/intel/edk2/UDK2017 together with the official Intel
distribution.

We are also adding back the CHANNEL_PRESENT enum, that is
missing in the official headers.

This was tested on the Razer Blade Stealth (late 2019).

Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37579
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11 09:09:39 +00:00
Nick Vaccaro 75f0124c44 mb/google/volteer: use new Tiger Lake memory config
Some of the common memory code that was being performed in
mainboard has moved into the soc to reduce redundant code.
This change adapts volteer to use Tiger Lake's new common code.

BUG=b:145642089, b:145238504, b:145564831
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, boot to kernel, "cat /proc/meminfo" and verify it reports
"MemTotal:        8038196 kB".

Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-11 07:52:47 +00:00
Marshall Dawson 5b43484db3 Documentation/soc/amd/family17: Update to match current design
The Picasso no longer intends to implement a hybrid romstage,
opting instead for a more traditional bootblock/romstage/ramstage.
Update the documentation to reflect this.  Clarify additional
details that have come to light since the last revision.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I6c98c007ddb8a4a05810f19e4215bde719de7bb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-11 07:52:04 +00:00
Marshall Dawson 5a1ba1bc29 Documentation/soc/amd: Add PSP integration information
Change-Id: I05187365158eb5c055be0d4a32f41324d2653f71
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-11 07:51:53 +00:00
Wim Vervoorn 6cd5243295 arch/x86/acpi: Change message in acpi_write_dbg2_pci_uart to BIOS_DEBUG
When acpi_write_dbg2_pci_uart is called and no pci uart is available the
function prints "Device not found" as an error. This is not correct.

Change the error level to BIOS_DEBUG so coreboot reports the device is
not available but doesn't flag this as an error.

BUG=N/A
TEST=build

Change-Id: I14567bcfcf5a6ff427e418d15bc2675ae7a28f53
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-11 07:51:21 +00:00
Wim Vervoorn 737b77c4bb mb/facebook/monolith: Enable the 2nd EC UART at 0x2f8
BUG=N/A
TEST=tested on facebook monolith

Change-Id: I36e652e66c66eeb770a5a5d987bb57c7eaa11382
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38749
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11 07:50:59 +00:00
Wim Vervoorn e6db9105ec soc/intel/common/block/lpc: Add lpc_get_fixed_io_decode
Add function to return the fixed io decode ranges contained in register
0x80 of the LPC interface.

BUG=N/A
TEST=build

Change-Id: Ie46d7c9d7a399a8489c030d906f75ba61db19cc4
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38745
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11 07:50:32 +00:00
Martin Roth 12e9c5ee86 Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint
We haven't been able to update IASL in 8 months because of this
conflict.  Ignoring it doesn't make things any worse than they are now.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-11 07:49:38 +00:00
Elyes HAOUAS 804b560704 sb/intel/lynxpoint: Don't use_ADR and _HID
To be compliant with ACPI specification, device object requires either
a _HID or _ADR, but not both.

Change-Id: I45cf2b8d455aa4d288de1ac53cf9ae801f758a9a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38351
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11 07:46:30 +00:00
Peter Lemenkov 32c63e050c mb/lenovo/x201/acpi_tables: Default to lid open
It's really hard to power up this laptop with the lid closed so let's
make it open by default, as done on many other laptops.

Change-Id: I5bb2f716865c2bb569a4735f135842526043713c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-11 07:46:14 +00:00
Subrata Banik 1cb26a6300 Kconfig: Add CONFIG_PCI dependency for CONFIG_MINIMAL_PCI_SCANNING
Make sure MINIMAL_PCI_SCANNING has right dependency over PCI kconfig
symbol.

Change-Id: I30b18345976e5d21ccedf8906985ff71e7d2815c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38801
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11 02:34:50 +00:00
Subrata Banik 37bead6d26 Kconfig: Guard CONFIGURABLE_RAMSTAGE
This patch guards CONFIGURABLE_RAMSTAGE symbol (which is default
enable for all x86 systems) with another Kconfig that can be selected
by platform that actually planning to use it.

TEST=CONFIG_CONFIGURABLE_RAMSTAGE is not enabled by default.

Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-11 02:34:32 +00:00
Joel Kitching 8a3bc3be92 vboot: correct workbuf size when VBOOT_STARTS_IN_ROMSTAGE
Part of the design of vboot persistent context is that the workbuf gets
placed in CBMEM and stays there for depthcharge to use in kernel
verification.  As such, the space allocated in CBMEM needs to be at least
VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE.

In the VBOOT_STARTS_IN_ROMSTAGE case, prior to this CL, vboot_get_context()
would get invoked for the first time after CBMEM comes up, and it would
only allocate VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE.

Initialize the workbuf directly in vboot_setup_cbmem() instead with the
correct VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE.

BUG=b:124141368, chromium:994060
TEST=make clean && make test-abuild
TEST=boot on GOOGLE_EVE with VBOOT_STARTS_IN_ROMSTAGE set
BRANCH=none

Change-Id: Ie09c39f960b3f14f3a64c648eee6ca3f23214d9a
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38778
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-10 21:25:14 +00:00
Nico Huber 9f78faedab intel/stm: Add platform opt-in Kconfig
Selecting STM on an arbitrary platform would likely result in a brick,
so let's hide the prompt by default.

Change-Id: I50f2106ac05c3efb7f92fccb1e6edfbf961b68b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <cedarhouse1@comcast.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-09 19:36:32 +00:00
Elyes HAOUAS eabb0c06f5 cpu/intel: Drop unused file
Change-Id: I1b41ddc5e99838f0585089974e995f3de7be1791
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37161
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:34:32 +00:00
Nico Huber 089790c7a3 mb/lenovo/t400: Configure panel-power sequencing
If the panel-power sequencer is not configured, libgfxinit falls back
to very conservative defaults (210ms before EDID is probed). This
results in a boot penalty of >100ms (depending on how long it takes
to probe other ports).

Values are taken from the VBTs already checked in. Untested.

Change-Id: I189776ce8684b4c3c01acd6d2fc433ca33a050d5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09 19:33:40 +00:00
Nico Huber d666ee86a4 mb/lenovo/t400: Correct display port list for R500 variant
The second digital display connector is unused, but strapped as if it
were used.

Versions with a discrete GPU seem to use PM45 (i.e. no IGD), so we can
ignore these.

Based on schematics only, not tested.

Change-Id: Ibb47fdeef2adb9c574b7f3ec8e2b1d61d28f21da
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-02-09 19:33:08 +00:00
Nico Huber 20b03bb706 mb/lenovo/t400: Correct display port list for [TW]500 variants
T500 and W500 (Coronado-5) use both digital display connectors. Both
with the DP AUX channel implemented, so add DP2 to the list.

Versions with a discrete GPU don't use external, digital connectors
but seem to have the straps correctly configured. So we hopefully
won't have to handle these specifically.

Based on schematics only, not tested.

Change-Id: I31e1415eff2d5d00c4a231906e3d861d2a59b629
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09 19:32:27 +00:00
Nico Huber 15ffb63db9 mb/lenovo/t400: Correct display port list for [RT]400 variants
The first digital display connector is unused, but strapped as if it
were on later revisions. The DP AUX channel of the second connector
is implemented, though, so add DP2 to the list.

Versions with a discrete GPU don't use external, digital connectors
but seem to have the straps correctly configured. So we hopefully
won't have to handle these specifically.

Based on schematics only, not tested.

Change-Id: I7d3e8b3a2123ddc407bb5a0cce86a3634b575f4a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09 19:32:11 +00:00
Nico Huber 1c40cdf360 mb/lenovo/t400: Move `gma-mainboard.ads` to variants
Some board revisions have the straps for display port detection
wrongly configured. So with a single list covering all variants'
possible outputs, we make libgfxinit probe unimplemented ports
which may stall the GMBUS controller and delay the boot for some
hundred milliseconds.

This just copies the list to the various variants with different
display ports, so we can test the actual changes individually.

Change-Id: I48cdea1d71d9553b6bdbce432eae986996329239
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09 19:31:55 +00:00
Patrick Rudolph e7ad0f2a2a Documentation: Remove qemu aarch64 from project ideas
This has been implemented last year.

Change-Id: I24e40a7a9a9d7238b8c9d34656d5b62a26b8252b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38533
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:31:21 +00:00
Piotr Kleinschmidt cb03065074 sb/amd/{agesa,pi}/hudson/Kconfig: Change default SATA mode to AHCI
The attempt to install pfSense on hard disk on PC Engines apu2 board
ended up in a SATA driver error. The problem is related only to BSD
and didn't occur with Linux kernel. Changing SATA mode from IDE to
AHCI solved the problem.

Additionally AHCI is faster than IDE so it speeds up the installation.
Since AHCI works perfectly with SeaBIOS, Linux and BSD, make it a default
choice for all Hudson southbridges.

Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940
Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35891
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:30:58 +00:00
Hash.Hung e653ad07ca mb/google/octopus/variants/lick: Increase TCC offset to 15
Change tcc offset from 0 to 15 degree celsius for lick.

BUG=b:147198431
BRANCH=octopus
TEST=Build, and verify test result by thermal team.

Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com>
Change-Id: Ife6b02321145837e05c82f979998466b83317f86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38506
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:30:29 +00:00
Paul Fagerburg e967cfa409 util/mainboard/google: add support for Zork
Update the create_coreboot_variant.sh and kconfig.py to support the
zork baseboard. Full template files will be added in a later CL.

BUG=b:148161697, b:148281637
BRANCH=None
TEST=`./create_coreboot_variant.sh zork dalboz` and verify that the
changes staged are correct.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie0a29bb9f4bb8f3bb7eaeae8799cef861c395e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-09 19:30:18 +00:00
Karthikeyan Ramasubramanian c015bcc304 mb/google/dedede: Add initial configuration for serial IO ports
Add initial configuration for GSPI, I2C and UART ports and leave them in
disabled state.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-02-09 19:29:51 +00:00
Karthikeyan Ramasubramanian 441867d2f0 mb/google/dedede: Turn on ESPI device in devicetree
BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38739
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:29:41 +00:00
Karthikeyan Ramasubramanian cc633f2e3a mb/google/dedede: Add GPE configuration
Configure the GPIO groups to be routed to the GPE0 block.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09 19:29:15 +00:00
Karthikeyan Ramasubramanian 118e9755ec mb/google/dedede: Add Compute & PCH Global device IDs
Add compute and PCH Global device IDs with the concerned devices turned
off.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09 19:28:27 +00:00
T Michael Turney 540b8ecc1e trogdor: update python scripts for python3
Change-Id: I46525243729c1dbcd30b346d4603452eea14ad9d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-09 19:27:00 +00:00
Nick Vaccaro b1fa25fab7 soc/intel/tigerlake: add memory configuration support
Move some of the common memory code that was being performed in
mainboard into the soc to reduce redundant code going forward.

BUG=b:145642089
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, log into kernel and verify memory size shows 8GB.

Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09 19:26:36 +00:00
Nick Vaccaro f978191b64 mb/google/volteer: add volteer mainboard initial support
Created a new Google baseboard named volteer from scratch.

BUG=b:142961277
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.

Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09 19:26:23 +00:00
Ian Feng 7bac50e824 mb/google/drallion: Add new SPD files for drallion
Add new SPD files for drallion:
1. Hynix H5AN8G6NDJR-XNC
2. Samung K4AAG165WA-BCWE
3. Samung K4A8G165WC-BCWE

BUG=b:148642500
TEST=Compile successfully and check SPD info in cbmem log.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38731
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:26:01 +00:00
Eric Lai bfe0948f7d mb/google/drallion: Tuning WWAN power sequence
Change GPP_C10 from pltrst to deep to meet the warmboot power sequence.

BUG=b:146935222
TEST=measure WWAN power sequence is meet spec

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-09 19:25:44 +00:00
Karthikeyan Ramasubramanian 3fde8c9977 mb/google/dedede: Log mainboard events to elog
BUG=b:148410914
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7dffa5c021787dca75786ead42164bd29ba56828
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09 19:25:27 +00:00
Chris Morgan f8a13d5a22 mb/lenovo/t440p: Enable dGPU on Lenovo T440P
Enable the dGPU on the Lenovo T440P.  It uses the same code (roughly) of
the T430S.  By default, it is set to be disabled however it can be
enabled via the nvram option enable_dual_graphics. Removed hybrid graphics
options too as they are not valid for the T440p. Tested on a T440P with
Ubuntu 18.04.4 with Kernel 5.3.0-29 (successful). Tested on same machine
with Windows 10 1909 (machine check exception bluescreen).

Change-Id: Idf8c2c0d1ae34bda8736448d3e350396e3cf7a93
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-09 19:24:30 +00:00
Paul Menzel 75372e5a75 Documentation: Mark up register names as code
Change-Id: I708385bca8edcd74b0d4c0a3ecc181b6ccd30c2b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38721
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:23:58 +00:00
Paul Menzel cedd4525f2 Documentation: Indent code blocks instead of using ```
Both versions are correct, but especially for one liners indenting them
with four spaces instead of using ``` blocks helps readability of the
source file.

Change-Id: Ie2543c8c4cccefd74e966f784e651ed7dc3a9252
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38720
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:23:49 +00:00
Tony Huang f9bb675690 mb/google/octopus: Override VBT selection for Bloog
Since most of Bloog series SKUs need to disable DRRS support.

If Bloog and Unprovisioned SKUs then return vbt.bin to enable DRRS support,
return vbt_blooguard.bin for other SKUs to disable DRRS support.

Bipship follow blooguard to disable DRRS support.

BUG=b:148892903, b:147021309
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
     check i915_drrs_status shows DRRS supported NO when SKU ID is bipship.

Change-Id: I61f12d4ddea17a05255751fde2a5ce822dd2e782
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-02-09 19:23:07 +00:00
Marcello Sylvester Bauer 6f9a77851b util/ifdtool: Support modification of single Flash Descriptor
Add the capability to update the Flash Descriptor directly instead
of raising a Segmentation Fault. In this way it will be possible to
add a Kconfig options to modify the ifd descriptor at build-time.

Change-Id: Id3db09291af2bd2e759c283e316afd5da1fb4ca7
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-09 19:22:42 +00:00
Sridhar Siricilla f2eb687d19 soc/intel/{cnl,icl,skl,tgl,common}: Make changes to send_heci_reset_req_message()
Below changes have been implemented in send_heci_reset_req_message():
1. Modify return values to align with other functions in the same file.
2. Add additional logging.
3. Replace macro definitions of reset types with ENUM.
4. Make changes to caller functions to sync with new return values.
5. Rename send_heci_reset_req_message() to cse_request_global_reset().

Test=Verified on hatch board.

Change-Id: I979b169a5bb3a5d4028ef030bcef2b8eeffe86e3
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37584
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:20:44 +00:00
Sridhar Siricilla 63be9181cb soc/intel/common: Add description to HMRFPO status
Below changes are implemented:
1. Fix typos.
2. Rename 'padding' field of hmrfpo_get_status_resp struct to
   'reserved' to match with ME BWG Guide.
3. Add documentation for HMRFPO Status.

TEST=Build and boot hatch

Change-Id: I4db9bdf7386c48e17ed0373cf334ccff358d1951
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09 19:20:16 +00:00
Sridhar Siricilla ff072e6ebf soc/intel/common: Rename functions for consistent naming
Below changes are done:
1. Rename below functions to have consistent naming:
	set_host_ready() -> cse_set_host_ready()
        wait_cse_sec_override_mode() -> cse_wait_sec_override_mode()
	send_hmrfpo_enable_msg()     -> cse_hmrfpo_enable()
	send_hmrfpo_get_status_msg() -> cse_hmrfpo_get_status()

2. Additional debug messages are added in cse_wait_sec_override_mode().

TEST=Build and Boot hatch board.

Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09 19:20:00 +00:00